16-Elec-A4, May 2019 Page 1 of 6 National Exams May 2019 16-Elec-A4, Digital Systems and Computers 3 hours duration NOTES: 1. If doubt exists as to the interpretation of any question, the candidate is urged to submit with the answer paper, a clear statement of any assumptions made 2. This is a Closed Book exam. Ganuiuales may use one of two calculators, the Casio or Sharp approved models. 3. FIVE (5) questions constitute a complete exam. Clearly indicate your choice of any five of the six questions given otherwise the first five answers tound will be considered your pick. 4. All questions are worth 12 points. See below for a detailed breakdown of the marking. Marking Scheme 1. @3,()3, (€)3, (4) 3, total = 12 2. (a)3, )3, (©)3, )3, total = 12 3. (a) 6, (b) 6, total = 12 4. (a3, (b)4, (©) 3, (@) 2, total = 12 5. (a) 3, (b) 3, (c) 3, (d) 3, total = 12 6. (a) 4.5, (b) 4.5, (c) 3, total = 12 ‘The number beside each part above indicates the points that part is worth16-Elec-A4, May 2019 Page 2 of 6 1+ Given the following function in product-of-suns (PoS) form: 7(4,8,6,0) = []m(0.2.6,7.8,10.14,15) ‘Map the function f in a K-map and: (a) Find the minimized PoS expression for f. (b) Check if the minimized expression found in (a) is hazard-free, Justify. Lt tas not hazard-free provide the smallest PoS hazard-free expression for f (c) Find the minimized sum-of-products (SoP) expression for f. (@) Check if the minimized expression found in (c) is hazard-free. Justify. If it is not hazard-free provide the smallest SoP harard-free expression for f 2 Design a sequential circuit with two JK flip-flops, A and B, and two inputs E and X that performs as follows - If E=0 the circuit remains in the same state regardless the value of X, - When E = I and X = I the circuit goes through the state transitions AB = 00 to 01 to 10 to 11 back to 00, and repeats, - When E = | and X = 0 the circuit goes through the state transitions AB = 00 to 11 to 10 to 01 back to 00, and repeats. Provide: (a) the state transition diagram, (b) the state transition table, (©) the K-map simplification of the combinational logic required, as well as (@) a drawing of the resulting logic cirenit diagram. Note: Consult flip-flop excitation tables at:ached at the end as needed.16-Elec-A4, May 2019 Page 3 of 6 3. The following is a truth table of a 3-input, 4-output combinational circuit. (a) Use K-maps to obtain the simplified expressions for A, B, C and D. (©) Implement them nsing a Programmable Logic Array (PLA) architecture. Clk Inputs Ourputs, A B c xX ¥. Zz Ww o ° ° 0 1 1 1 0 0 1 0 1 1 L 0 1 0 1 0 0 1 0 1 1 0 al 0 1 1 o 0 0 0 o 0 1 0 1 0 if 1 1 1 1 0 1 i 0 1 i 1 1 1 i o 0 ‘The following circuit with input X and output Y uses one RS flip-flop and a T flip-flop. = my (a) Write the logic expressions for Ra, Sa, Te and Y. (b) Obtain the state transition table for the circuit Include A, B, X, Ra, Sa, Ta, A’, B*, Y in this order. (©) Sketch the state transition diagram for the circuit (@) Is this a Moore or a Mealy machine? Explain. Note: Consult flip-flop excitation table attached at the end as needed.46-Flec-A4, May 2019 Page 4 of 6 5. The diagram below shows the use a D flip~lop governing two digital switches in order to route line PDo of the HC11 microcontroller unit (MCU) to one of two connectors: the HOST computer /O port or the MCU V/O port connector. Digitals switches close when control input Cis at a logic 'I' and remain open when C is 0. HCI1 address lines Ats - Ais are connected to the 3 address inputs of a 3:8 decoder as shown in the figure, the most significant adress input of the decoder is Az and the least significant is Ao. Assume the decoder is enabled and towards the end of the execution of each instruction cycle all its active-low outputs Yo - 77 go back to their inactive logic ‘1 state. ‘The least significant data bus line of the HC1I (Do) is connected to the flip-flop D input. Knowing that instruction Idaa #$xx means load HC11 CPU register accumulator A with hexadecimal value xx, and staa Szzzz means store the value in accumuletor A to address $2722, which of the following set of instructions will direct HC11 line PDo to the HOST computer VO port, which to the MCU Y/O port connector and which will not affect the current routing. ‘Mark your choice with an X and justify your selection in each case. (a) Ida ¥$10, sta $8000 [ ] HOST Comp V/O port, [ ] MCU V/O port, [ ] No Action (b) Ida #829, sta $4000 [ ] HOST Comp VO port, [ ] MCU VO port, [ ] No Action (©) Ida #$B4, staa $5000 [ ] HOST Comp V/O port, [ } MCU VO port, [ ] No Action (d) Ida #$05, sta $2500 [ ] HOST Comp VO port, [ ] MCU VO port, [ ] No Action a yi 3:8 % DEcovER ES HCH Ais] a HCH Aus} ey HCL Aus tA az Host Comp <——_———__-______ W/O PorT PDo Digital [Jc Switch 1 Q ck HCL non {AC PDs Data Bus ; Line D Mcu Digtal [J 9p _ Switeh 2 L Mcu PDo vo Port16-Elec-A4, May 2019 Page 5 of 6 6. Provide this 8-bit CPU with a 64Kbyte memory space by making use of 16K. x 4 memory modules like the ones provided in the figure below. (a) Fill in the blanks beside and inside the memory module with the appropriate ‘numbers. The number on top of this symbol —7“— represents the number of lines on that bus. The spaces besides the A’s and the D's are to indicate which lines of the address and data busses are connected :o each module, respectively. (6) Complete the connections in the figure below adding logic gates where needed to produce the chip select (CS) signals ueeded in the decoding logic. Explain the reasons for the connections made, include expressions for the Boolean logic used. (c) Provide the address range allocated to each of the modules used. Note: R/W & clock signals are omitted for simplicity. 16 Address Bus (A1s~ Ao) 8-bit CPU Data Bus (Dr— Do)16-Elec-A4, May 2019 Page 6 of 6 Excitation Table Q Qe IR Ss {5 Kir ip) 0 0 x 0 0 x 0 ons 0 1 0 1 1 xX 1 1 1 0 1 0 x 1 1 0 1 1 0 x x 0 0 1 Comments 1 Operations with 0 and 1 2 Operations with 0 and 1 3, Idompotent 4. Complementarity 5. Operations with 0 and 4 6. Operations with 0 and 1. 7. Tdompotent 8 Complementarity 9. Involution 10. Commutative i ABaBA Commutative 12, Associative 13, Associative 4, A.(BHC)=(A-A)4(A-O) Distributive 15. A¥(B-C)=(A+ B)- (A+) Distributive 16. A+(A-B)=A Absorption 7 Absorption 18. (A-R)+(4-0)+(B-0)=(A-B)+(A-C) Consensus 19, A¥B+CH.. De Morgan 20, ABC nH A+ Bs C+. De Morgan 21. (A+B): BAB Simplification 2 (A-B)+B=A+B Simplification