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Quiz AICD

This document appears to be a quiz for a class on analog integrated circuit design. It contains 10 multiple choice questions testing concepts related to MOSFET device physics, operational amplifier design and performance parameters. The questions cover topics such as how device dimensions and biases affect MOSFET resistance, operational amplifier circuit analysis, temperature effects on MOSFET mobility, parasitic BJT structures in MOSFETs, compensation techniques in op amp design, common mode rejection ratio calculations, threshold voltage dependence on source-bulk voltage, typical electron mobility values in silicon MOSFETs, and analyzing a simple MOSFET circuit to determine the voltage at a node.

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Anil Rawat
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358 views2 pages

Quiz AICD

This document appears to be a quiz for a class on analog integrated circuit design. It contains 10 multiple choice questions testing concepts related to MOSFET device physics, operational amplifier design and performance parameters. The questions cover topics such as how device dimensions and biases affect MOSFET resistance, operational amplifier circuit analysis, temperature effects on MOSFET mobility, parasitic BJT structures in MOSFETs, compensation techniques in op amp design, common mode rejection ratio calculations, threshold voltage dependence on source-bulk voltage, typical electron mobility values in silicon MOSFETs, and analyzing a simple MOSFET circuit to determine the voltage at a node.

Uploaded by

Anil Rawat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Roll No.

_______________ Name_____________

Thapar Institute of Engineering and Technology, Patiala


Electronics and Communication Engineering Department
Quiz Test
Time: 10 min. Analog IC Design (PVL206) M.M. 10
Note: There may be more than one correct answer in a question. Please give most
appropriate answer.
1) A long channel NMOS transistor is biased in the liner region Vds= 20 mv and is used as a resistance.
Which one of the following statements is NOT correct?
a) If the device width W is increased, the resistance decrease.
b) If the threshold voltage is reduced, the resistance decreases.
c) If the device length L is increased, the resistance decreases.
d) If Vgs is increased, the resistance increases.
2) An Op – Amp has offset voltage of 1mV and is ideal in all other respects. If this Op –Amp is used in
the circuit shown in figure. The output voltage will be

a) 1 mV
b) 1V
c) ± 1V
d) 0V

3) Which of the following effects can be caused by a rise in temperature?


a) Increase in mobility of MOSFET
b) Decrease in mobility of MOSFET
c) No change in mobility of MOSFET
d) It increases for PMOS and decreases for NMOS
4) The relation between noise generated from resistor and the noise generated from transistor is
a) Correlated
b) Uncorrelated
c) Equal
d) None of the above
5) In the internal structure of a MOSFET, a parasitic BJT exists between the
a) source & gate terminals
b) source & drain terminals
c) drain & gate terminals
d) there is no parasitic BJT in MOSFET
6) In two-stage op-amp, what is the purpose of compensation circuitry?
a) To provide high gain
b) To lower output resistance & maintain large signal swing
c) To establish proper operating point for each transistor in its quiescent state
d) To achieve stable closed-loop performance
7) If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48
dB and 2 dB respectively, then its common mode rejection ratio is
a) 24 dB
b) 46 dB
c) 25 dB
d) 50 dB

8) For an n – channel enhancement type MOSFET, if the source is connected at a lower


potential than that of the bulk (i.e. VSB ˂ 0), the threshold voltage VT of the MOSFET will
(a) Remain unchanged (b) Decrease (c) Change polarity (d) Increase
9) At room temperature, a possible value for the mobility of electrons in the inversion layer of a
silicon n – channel MOSFET is
(a) 450 cm2 / V – s (b) 1350 cm2 / V – s (c) 1800 cm2 / V – s (d)3600 cm2 / V – s
10) In the circuit shown below, for the MOS transistors, 𝜇𝑛 𝐶𝑂𝑋 = 100 𝜇𝐴/𝑉 2 and the threshold
voltage VT = 1 V. The voltage VX at the source of the upper transistor is

(a) 1 V (b)2 V (c) 3 V (d)3.6 V

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