Implementation of Smart Attendance On FPGA
Implementation of Smart Attendance On FPGA
FPGA
Athira Shanker, Debolina Roy, Mebin P M, Sivasankaran K.
M.Tech VLSI Design, Dept. of Micro & Nano electronics, SENSE, Vellore Institute of Technology, Vellore, Tamil Nadu,
India
D. Cascade Classifier
Fig.7 PCA Block Diagram
The main function of the classifier is to store the Haar
features in number of stages to increase the speed of detection.
A face is detected only if a sub window passes all the
mentioned stages. A classifier will detect the errors of the
previous stage and will assign weights to those features which
are more erroneous. It will then pass on to the next sub
V. IMPLEMENTATION
VI. RESULTS
Viola Jones algorithm was implemented in Fig.10 Displaying captured video on a VGA monitor
MATLAB (Fig.8).
Verilog code for reading an image from a specified
memory location in RGB format was implemented. The
read RGB image was then converted into grayscale format
and stored into another Bitmap image.
REFERENCES
[1] Alahmadi and S. M. Qaisar, “Robust Real-time Embedded Face
Detection Using Field Programmable Gate Arrays (FPGA),” 2019
Advances in Science and Engineering Technology International
Conferences (ASET), 2019.
[2] S. V. Chakrasali and S. Kuthale, “Optimized face detection on
FPGA,” 2016 International Conference on Circuits, Controls,
Communications and Computing (I4C), 2016.
[3] Raghuwanshi and P. D. Swami, “An automated classroom
attendance system using video based face recognition,” 2017 2nd
IEEE International Conference on Recent Trends in Electronics,
Information & Communication Technology (RTEICT), 2017.
[4] S. Poornima, N. Sripriya, B. Vijayalakshmi, and P. Vishnupriya,
“Attendance monitoring system using facial recognition with audio
output and gender classification,” 2017 International Conference
on Computer, Communication and Signal Processing (ICCCSP),
2017.
[5] L. Schaffer, Z. Kincses, and S. Pletl, “FPGA-based low-cost real-
time face recognition,” 2017 IEEE 15th International Symposium
on Intelligent Systems and Informatics (SISY), 2017.
[6] V. P. Korakoppa, Mohana, and H. V. R. Aradhya, “An area
efficient FPGA implementation of moving object detection and
face detection using adaptive threshold method,” 2017 2nd IEEE
International Conference on Recent Trends in Electronics,
Information & Communication Technology (RTEICT), 2017.
[7] Ahmad, A. Amira, P. Nicholl, and B. Krill, “FPGA-based IP cores
implementation for face recognition using dynamic partial
reconfiguration,” Journal of Real-Time Image Processing, vol. 8,
no. 3, pp. 327–340, 2011.
[8] D. N. Arya, S. K.l.v., R. Reddy, S. S, and S. K, “A face detection
system implemented on FPGA based on RCT colour
segmentation,” 2016 Online International Conference on Green
Engineering and Technologies (IC-GET), 2016.
[9] Liton Chandra Paul, Abdulla Al Sumam, “Face Recognition Using
Principal Component Analysis Method,”International Journal of
Advanced Research in Computer Engineering & Technology
(IJARCET) Volume 1, Issue 9, November.
[10] N. Çevik and T. Çevik, “A novel high-performance holistic
descriptor for face retrieval,” Pattern Analysis and Applications,
2019