TLV 320 Aic 3100
TLV 320 Aic 3100
TLV 320 Aic 3100
TLV320AIC3100
SLAS667C – NOVEMBER 2009 – REVISED OCTOBER 2016
1.1
1
Features
• Stereo Audio DAC With 95-dB SNR • Pin Control or Register Control for Digital-Playback
• Mono Audio ADC With 91-dB SNR Volume-Control Settings
• Supports 8-kHz to 192-kHz Separate DAC and • Digital Sine-Wave Generator for Beep
ADC Sample Rates • Integrated PLL Used for Programmable Digital
• Mono Class-D BTL Speaker Driver (2.5 W Into Audio Processor
4 Ω or 1.6 W Into 8 Ω) • I2S, Left-Justified, Right-Justified, DSP, and TDM
• One Differential and Three Single-Ended Inputs Audio Interfaces
With Mixing and Level Control • I2C Control With Register Auto-Increment
• Microphone With Bias, Preamp PGA, and AGC • Full Power-Down Control
• Built-In Digital Audio Processing Blocks (PRB) • Power Supplies:
With User-Programmable Biquad and FIR Filters – Analog: 2.7 V–3.6 V
• Digital Mixing Capability – Digital Core: 1.65 V–1.95 V
• Programmable Digital Audio Processor for Bass – Digital I/O: 1.1 V–3.6 V
Boost/Treble/EQ With up to Five Biquads for – Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)
Record and up to Six Biquads for Playback
• 5-mm × 5-mm 32-QFN Package
1.2 Applications
• Portable Audio Devices • Adaptive Filtering Applications
• Mobile Internet Devices
1.3 Description
The TLV320AIC3100 is a low-power, highly integrated, high-performance codec which provides a stereo audio
DAC, a mono audio ADC, and a mono class-D 4-Ω speaker driver.
The TLV320AIC3100 features a high-performance audio codec with 24-bit stereo playback and monaural record
functionality. The device integrates several analog features, such as a microphone interface, headphone drivers,
and speaker drivers. The TLV320AIC3100 has built-in digital audio processing blocks (PRB) for both the DAC
and ADC paths. The digital audio data format is programmable to work with popular audio standard protocols
(I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ can be supported by
the programmable digital signal-processing block. An on-chip PLL provides the high-speed clock needed by the
digital signal-processing block. The volume level can be controlled by either pin control or by register control. The
audio functions are controlled using the I2C serial bus.
The TLV320AIC3100 has a programmable digital sine-wave generator and is available in a 32-pin QFN package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV320AIC3100 VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV320AIC3100
SLAS667C – NOVEMBER 2009 – REVISED OCTOBER 2016 www.ti.com
2 V/2.5 V/AVDD
MICBIAS
P1/R33–R34 De-Pop
7-Bit and Audio Output Stage
VOL/
Vol Soft- Power Management
MICDET ADC Start
P1/R30
Class A/B Analog Attenuation
Headphone/Lineout 0 dB to –78 dB and Mute
Driver (0.5-dB Steps / Nonlinear)
P1/R40 P1/R36 MIX_L
HPL
P1/R31 0 dB to 9 dB (1-dB Steps) Note: Normally,
MCLK is PLL input;
P1/R44 P1/R41 P1/R37 MIX_R however, BCLK,
HPR GPIO1, etc., can
also be PLL input.
MIX_R
MIX_L PLL MCLK
MIC1LP
DAC_L ∆-∑
Σ Σ Σ
DAC
MIC1LM Σ
OSC
VCOM
Input CM P1/R49
Selectable RC CLK
P1/R50 Gain/Input
Impedance
Table of Contents
1 Device Overview ......................................... 1 6 Parameter Measurement Information .............. 19
1.1 Features .............................................. 1 7 Detailed Description ................................... 20
1.2 Applications ........................................... 1 7.1 Overview ............................................ 20
1.3 Description ............................................ 1 7.2 Functional Block Diagram ........................... 21
1.4 Functional Block Diagram ............................ 2 7.3 Feature Description ................................. 21
2 Revision History ......................................... 3 7.4 Register Map ........................................ 78
3 Device Comparison ..................................... 5 8 Application and Implementation ................... 120
4 Pin Configuration and Functions ..................... 6 8.1 Application Information ............................ 120
4.1 Pin Attributes ......................................... 6 8.2 Typical Application ................................. 120
5 Specifications ............................................ 8 9 Power Supply Recommendations ................. 123
5.1 Absolute Maximum Ratings .......................... 8 10 Layout ................................................... 124
5.2 ESD Ratings .......................................... 8 10.1 Layout Guidelines .................................. 124
5.3 Recommended Operating Conditions ................ 8 10.2 Layout Example .................................... 124
5.4 Thermal Information .................................. 9 11 Device and Documentation Support .............. 125
5.5 Electrical Characteristics ............................. 9 11.1 Receiving Notification of Documentation Updates. 125
5.6 Power Dissipation Ratings .......................... 11 11.2 Community Resources............................. 125
5.7 I2S, LJF, and RJF Timing in Master Mode .......... 11 11.3 Trademarks ........................................ 125
5.8 I2S, LJF, and RJF Timing in Slave Mode ........... 11 11.4 Electrostatic Discharge Caution ................... 125
5.9 DSP Timing in Master Mode ........................ 11 11.5 Glossary............................................ 125
5.10 DSP Timing in Slave Mode ......................... 12 12 Mechanical Packaging and Orderable
5.11 I2C Interface Timing ................................. 12 Information ............................................. 125
5.12 Typical Characteristics .............................. 15 12.1 Packaging Information ............................. 125
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
3 Device Comparison
RHB Package
(Top View)
SPKVDD
SPKVDD
SPKVSS
SPKM
SPKM
DVSS
AVDD
SPKP
24 23 22 21 20 19 18 17
SPKVSS 25 16 AVSS
SPKP 26 15 MIC1LM
HPL 27 14 MIC1RP
HPVDD 28 13 MIC1LP
HPVSS 29 12 MICBIAS
HPR 30 11 VOL/MICDET
RESET 31 10 SCL
GPIO1 32 9 SDA
1 2 3 4 5 6 7 8
DVDD
DIN
IOVSS
BCLK
MCLK
DOUT
WCLK
IOVDD
P0048-15
5 Specifications
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 × (log(ΔVHPL / ΔVHPVDD)
(4) DAC to speaker-out PSRR is a differential measurement and is calculated as PSRR = 20 × log(ΔVSPK(P + M) / ΔVSPKVDD).
WCLK
td(WS) tr
BCLK
td(DO-WS) td(DO-BCLK) tf
DOUT
tS(DI) th(DI)
DIN
T0145-08
WCLK
th(WS) tr
tH(BCLK) tS(WS)
BCLK
tL(BCLK) td(DO-WS)
td(DO-BCLK) tf
DOUT
tS(DI) th(DI)
DIN
T0145-09
2
Figure 5-2. I S/LJF/RJF Timing in Slave Mode
WCLK
td(WS) td(WS)
tf
BCLK
td(DO-BCLK) tr
DOUT
tS(DI) th(DI)
DIN
T0146-07
WCLK
tS(WS) tS(WS)
th(WS) th(WS)
tL(BCLK) tf
BCLK
tH(BCLK) td(DO-BCLK) tr
DOUT
tS(DI) th(DI)
DIN
T0146-08
SDA
SCL
2
Figure 5-5. I C Interface Timing Diagram
14 Specifications Copyright © 2009–2016, Texas Instruments Incorporated
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Product Folder Links: TLV320AIC3100
TLV320AIC3100
www.ti.com SLAS667C – NOVEMBER 2009 – REVISED OCTOBER 2016
20 20
AVDD = HPVDD = 3.3 V AVDD = HPVDD = 3.3 V
0 IOVDD = SPKVDD = 3.3 V 0 IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V DVDD = 1.8 V
−20 −20
−40 −40
Amplitude − dBFS
Amplitude − dBFS
−60 −60
−80 −80
−100 −100
−120 −120
−140 −140
−160 −160
0 5 10 15 20 0 5 10 15 20
f − Frequency − kHz f − Frequency − kHz
G001 G002
20 20
AVDD = HPVDD = 3.3 V AVDD = HPVDD = 3.3 V
0 IOVDD = SPKVDD = 3.3 V 0 IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V DVDD = 1.8 V
−20 −20
−40 −40
Amplitude − dBFS
Amplitude − dBFS
−60 −60
−80 −80
−100 −100
−120 −120
−140 −140
−160 −160
0 5 10 15 20 0 5 10 15 20
f − Frequency − kHz f − Frequency − kHz
G003 G004
0 100
AVDD = HPVDD = 3.3 V
−10 IOVDD = SPKVDD = 3.3 V 95
DVDD = 1.8 V Diff = 10k
−20 90
Diff = 20k
−30 85
Amplitude − dBFS
−50 75
SE = 10k
−60 70
−70 65 SE = 20k
−80 60
SE = 40k
−90 55
−100 50
0 50 100 150 200 −10 0 10 20 30 40 50 60 70 80
f − Frequency − kHz Channel Gain − dB
G005 G006
Figure 5-10. Amplitude vs Frequency Figure 5-11. SNR vs PGA Channel Gain
Frequency Response, Audio ADC Channel
0 0
AVDD = HPVDD = 3.3 V AVDD = HPVDD = 3.3 V
−20 IOVDD = SPKVDD = 3.3 V −20 IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V DVDD = 1.8 V
−40 −40
Amplitude − dBFS
Amplitude − dBFS
−60 −60
−80 −80
−100 −100
−120 −120
−140 −140
−160 −160
0 5 10 15 20 0 5 10 15 20
f − Frequency − kHz f − Frequency − kHz
G001 G002
0
THD+N − Total Harmonic Distortion + Noise − dB
HPVDD = 2.7 V
−10
CM = 1.35 V
−20
−30
HPVDD = 3 V
−40 CM = 1.5 V
0 0
AVDD = HPVDD = 3.3 V SPKVDD = 3.3 V
THD+N − Total Harmonic Distortion + Noise − dB
SPKVDD = 3.6 V
Driver Gain
−30 = 24 dB −30
SPKVDD = 4.3 V
Figure 5-15. Total Harmonic Distortion + Noise vs Output Power Figure 5-16. Total Harmonic Distortion + Noise vs Output Power
Max Class-D Speaker-Driver Output Power (RL = 4 Ω) Class-D Speaker-Driver Output Power (RL = 4 Ω)
0 0
AVDD = HPVDD = 3.3 V SPKVDD = 3.3 V
THD+N − Total Harmonic Distortion + Noise − dB
Figure 5-17. Total Harmonic Distortion + Noise vs Output Power Figure 5-18. Total Harmonic Distortion + Noise vs Output Power
Max Class-D Speaker-Driver Output Power (RL = 8 Ω) Class-D Speaker-Driver Output Power (RL = 8 Ω)
0 0
AVDD = HPVDD = 3.3 V AVDD = HPVDD = 3.3 V
−20 IOVDD = SPKVDD = 3.3 V −20 IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V DVDD = 1.8 V
−40 −40
Amplitude − dBFS
Amplitude − dBFS
−60 −60
−80 −80
−100 −100
−120 −120
−140 −140
−160 −160
0 5 10 15 20 0 5 10 15 20
f − Frequency − kHz f − Frequency − kHz
G008 G009
2.5
Micbias = 2.5 V
V − Voltage − V
2.0
Micbias = 2 V
1.5
1.0
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
I − Current − mA
G016
7 Detailed Description
7.1 Overview
The TLV320AIC3100 device is a highly integrated stereo-audio DAC and monaural ADC for portable
computing, communication, and entertainment applications. A register-based architecture eases
integration with microprocessor-based systems through standard serial-interface buses. This device
supports the two-wire I2C bus interface which provides full register access. All peripheral functions are
controlled through these registers and the onboard state machines.
The TLV320AIC3100 device consists of the following blocks:
• Microphone interfaces (analog and digital)
• Audio codec (mono ADC and stereo DAC)
• AGC and DRC
• Two digital signal-processing blocks (record and playback paths)
• Digital sine-wave generator for beep
• Stereo headphone and lineout amplifier
• Pin-controlled or register-controlled volume level
• Power-down de-pop and power-up soft start
• Analog inputs
• I2C control interface
• Power-down control block
Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C
interface is used to write to the control registers to configure the device.
The I2C address assigned to the TLV320AIC3100 device is 001 1000. This device always operates in an
I2C slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device
auto-increments to support sequential addressing and can be used with the I2C fast mode. When the
device is reset, all appropriate registers are updated by the host processor to configure the device as
needed by the user.
2 V/2.5 V/AVDD
MICBIAS
P1/R33–R34 De-Pop
7-Bit and Audio Output Stage
VOL/
Vol Soft- Power Management
MICDET ADC Start
P1/R30
Class A/B Analog Attenuation
Headphone/Lineout 0 dB to –78 dB and Mute
Driver (0.5-dB Steps / Nonlinear)
P1/R40 P1/R36 MIX_L
HPL
P1/R31 0 dB to 9 dB (1-dB Steps) Note: Normally,
MCLK is PLL input;
P1/R44 P1/R41 P1/R37 MIX_R however, BCLK,
HPR GPIO1, etc., can
also be PLL input.
MIX_R
MIX_L PLL MCLK
MIC1LP
DAC_L ∆-∑
Σ Σ Σ
DAC
MIC1LM Σ
OSC
VCOM
Input CM P1/R49
Selectable RC CLK
P1/R50 Gain/Input
Impedance
1. Power up SPKVDD
2. Power up IOVDD
3. Power up DVDD shortly after IOVDD
4. Power up AVDD and HPVDD
Although not necessary, if the system requires, during shutdown, remove the power supplies in the
reverse order of the above sequence.
7.3.2 Reset
The TLV320AIC3100 internal logic must be initialized to a known condition for proper device function. To
initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low
for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up.
TI recommends that while the DVDD supply powers up, the RESET pin is pulled low.
The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the
device.
7.3.8.3 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V
DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B)
Power consumption = 24.28 mW
7.3.8.4 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V
DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B)
Power consumption = 15.4 mW
7.3.8.5 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V
DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B)
Power consumption = 22.44 mW
7.3.8.6 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V
DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B)
Power consumption = 14.49 mW
7.3.8.7 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V
DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C)
Power consumption = 27.05 mW
7.3.8.8 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V,
HPVDD = 3 V
DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)
Power consumption = 12.85 mW
During normal operation, MICBIAS can be set to 2.5 V for better performance. However, based on the
model of the selected microphone, optimal performance can be obtained at another setting and therefore
the performance at a given setting must be verified.
The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current
consumption occurs when MICBIAS is set at AVDD.
Because of the oversampling nature of the audio ADC and the integrated digital-decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3100 device integrates a
second-order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the
digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.
The MIC PGA supports analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. These gain levels are
controlled by writing to page 1 / register 47, bits D6–D0. The PGA gain changes are implemented with
internal soft-stepping. This soft-stepping ensures that volume-control changes occur smoothly with no
audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with soft-stepping enabled. The
ADC soft-stepping control is enabled or disabled by writing to page 0 / register 81, bits D1–D0. ADC soft-
stepping timing is provided by the internal oscillator and internal divider logic block.
The input feed-forward resistance for the MIC1LP input of the microphone PGA stage has three settings,
10 kΩ, 20 kΩ, and 40 kΩ, which are controlled by writing to page 1 / register 48, bits D7 and D6. The input
feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for
the MIC1LP input depends on the setting of page1 / register 48 and page 1 / register 49, bits D7–D6. If
D7–D6 are set to 01, then the ADC PGA has 6 dB more gain with respect to the value programmed using
page 1 / register 47. If D7–D6 are set to 10, then the ADC PGA has the same gain as programmed using
page 1 / register 47. If D7–D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the
value programmed using page 1 / register 47. The same gain scaling is also valid for the MIC1RP and
MIC1LM input, based on the feed-forward resistance selected using page 1 / register 48, bits D5–D2.
Table 7-15 lists the effective gain applied by the PGA.
The MIC PGA gain is either controlled by an AGC loop or as a fixed gain. See for the various analog input
routings to the MIC PGA that are supported in the single-ended and differential configurations. The AGC is
enabled by writing to page 0 / register 86, bit D7. If the AGC is not enabled, then setting a fixed gain
occurs by writing to page 1 / register 47, bits D6–D0. Because the TLV320AIC3100 device supports soft-
stepping gain changes, a read-only flag on page 0 / register 36, bit D7 is set whenever the gain applied by
PGA equals the desired value set by the gain register. The MIC PGA is enabled by writing to page 1 /
register 47, bit D7. ADC muting occurs by writing to page 0 / register 82, bit D7 and page 1 / register 47,
bit D7. Disabling the MIC PGA sets the gain to 0 dB. Muting the ADC causes the digital output to mute so
that the output value remains fixed. When soft-stepping is enabled, the CODEC_CLKIN signal must stay
active until after the ADC power-down register is written, in order to ensure that soft-stepping to mute has
had time to complete. When the ADC POWER UP flag is no longer set, the CODEC_CLKIN signal can
shut down.
Max PGA applicable allows the user to restrict the maximum gain applied by the AGC. This can be used
for limiting PGA gain in situations where environmental noise is greater than the programmed noise
threshold. Microphone input maximum PGA can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.
Programming the maximum PGA gain allowed by the AGC is done by writing to page 0 / register 88,
bits D6–D0.
See Table 7-16 for various AGC programming options. AGC can be used only if the microphone input is
routed to the ADC channel.
Input
Signal
Output Target
Signal Level
AGC
Gain
The AGC settings should be set based on user and system conditions such as microphone selection and
sensitivity, acoustics (plastics) around the microphone which affect the microphone pattern, expected
distance and direction between microphone and sound source, and acoustic background noise.
One example of AGC code follows, but actual use of code should be verified based on application usage.
Note that the AGC code should be set up before powering up the ADC.
####################### AGC ENABLE EXAMPLE CODE #####################
## Switch to page 0
w 30 00 00
# Set AGC enable and Target Level = -10 dB
# Target level can be set lower if clipping occurs during speech
# Target level is adjusted considering Max Gain also
w 30 56 A0 # AGC hysteresis=DISABLE, noise threshold = -90dB
# Noise threshold should be set at higher level if noisy background is present in application
w 30 57 FE # AGC maximum gain= 40 dB
# Higher Max gain is a trade off between gaining up a low sensitivity MIC, and the background
# acoustic noise
# Microphone bias voltage (MICBIAS) level can be used to change the Microphone Sensitivity
w 30 58 50
# Attack time=864/Fs w 30 59 68
# Decay time=22016/Fs
w 30 5A A8
# Noise debounce 0 ms
# Noise debounce time can be increased if needed
w 30 5B 00
# Signal debounce 0 ms
# Signal debounce time can be increased if needed
w 30 5C 00
######################## END of AGC SET UP #################################
AGC
From
Digital Vol. Ctrl
To Analog PGA
AGC
From
Digital Vol. Ctrl
To Analog PGA
From Delta-Sigma st
AGC
Modulator or 1 Order Gain To Audio
Filter A 25-Tap FIR ´ IIR
Digital Microphone Compen Interface
sation
AGC
From
Digital Vol. Ctrl
To Analog PGA
AGC
From Delta-Sigma st
1 Order Gain To Audio
Modulator or Filter B ´ IIR
Digital Microphone Compen Interface
sation
To Audio
Interface
AGC
From
Digital Vol. Ctrl
To Analog PGA
AGC
From
Digital Vol. Ctrl
To Analog PGA
From Delta-Sigma st
AGC
1 Order Gain To Audio
Modulator or Filter B 20-Tap FIR ´ IIR Compen Interface
Digital Microphone
sation
AGC
From
Digital Vol. Ctrl
To Analog PGA
st AGC
From Delta-Sigma
1 Order Gain To Audio
Modulator or Filter C ´ IIR Compen Interface
Digital Microphone
sation
AGC
From
Digital Vol. Ctrl
To Analog PGA
AGC
From
Digital Vol. Ctrl
To Analog PGA
From Delta-Sigma st
AGC
1 Order Gain To Audio
Modulator or Filter C 25-Tap FIR ´ IIR Compen Interface
Digital Microphone sation
AGC
From
Digital Vol. Ctrl
To Analog PGA
The coefficients of these filters are each 16 bits wide, in 2s-complement format, and occupy two
consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15)
format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF), as shown in Figure 7-11.
–15
2 Bit
–4
2 Bit Largest Positive Number:
= 0.111111111111111111
–1 = 0.999969482421875 = 1.0 – 1 LSB
2 Bit
S...xxxxxxxxxxxxxxxxxx
The frequency response for the first-order IIR section with default coefficients is flat at a gain of 0 dB.
The default values for each biquad section yield an all-pass (flat) frequency response at a gain of 0 dB.
The coefficients of the FIR filters are 16-bit 2s-complement format (2 bytes each) and correspond to the
ADC coefficient space as listed in Table 7-20. Note that the default (reset) coefficients are not valid for the
FIR filter. When the FIR filter is used, all applicable coefficients must be reprogrammed by the user. To
reprogram the FIR filter coefficients as an all-pass filter, write value 0x00 to page 4 / registers 24, 25, 34,
35, 44, 45, 54, and 55.
Magnitude – dB
–40
–50
–60
–70
–80
–90
–100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequency Normalized to fS
–20
Magnitude – dB
–30
–40
–50
–60
–70
–80
–90
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequency Normalized to fS
–20
Magnitude – dB
–40
–60
–80
–100
–120
Record - Paused
Update
Digital Filter ADC Volume Ramp Up Time (B)
Coefficients
For fS = 32 kHz ® 10 ms
Wait 20 ms
Restore Previous
Volume Level (Ramp)
in (B) ms
Record - Continue
F0023-02
D-S Signal
ADC Mono ADC
Processing DOUT
CIC Filter
Blocks
DIG_MIC_IN
ADC_MOD_CLK
GPIO1 DIN
The TLV320AIC3100 outputs internal clock ADC_MOD_CLK on the GPIO1 pin (page 0 / register 51,
bits D5–D2 = 1010). This clock can be connected to the external digital microphone device. The single-bit
output of the external digital microphone device can be connected to the DIN pin. Internally, the
TLV320AIC3100 latches the steady value of the mono ADC data on the rising edge of ADC_MOD_CLK.
ADC_MOD_CLK
DIG_MIC_IN Mono Data No Data Mono Data No Data Mono Data No Data
When the digital microphone mode is enabled, the analog section of the ADC can be powered down and
bypassed for power efficiency. The AOSR value for the ADC channel must be configured to select the
desired decimation ratio to be achieved, based on the external digital microphone properties.
7.3.9.7 DC Measurement
The TLV320AIC3100 supports a highly flexible dc-measurement mode using the high-resolution
oversampling and noise-shaping ADC. This mode can be used when the ADC channel is not used for the
voice/audio record function. This mode can be enabled by programming page 0 / register 102, bit D7. The
converted data is 24 bits, using the 2.22 numbering format. The value of the converted data for the ADC
channel can be read back from page 0 / register 104 through page 1 / register 106. Before reading back
the converted data, page 0 / register 103, bit D6 must be programmed to 1 in order to latch the converted
data into the read-back registers. After the converted data is read back, page 0 / register 103, bit D6 must
be immediately reset to 0. In dc-measurement mode, two measurement modes are supported.
Mode A
In dc-measurement mode A, a variable-length averaging filter is used. The length of averaging filter D can
be programmed from 1 to 20 by programming page 0 / register 102, bits D4–D0. To choose mode A,
page 0 / register 102, bit D5 must be programmed to 0.
Mode B
To choose mode B, page 0 / register 102, bit D5 must be programmed to 1. In dc-measurement mode B,
a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0 / register 102,
bits D4–D0. The nature of the filter is given in Table 7-24.
By programming page 0 / register 103, bit D5 to 1, the averaging filter is periodically reset after 2R number
of ADC_MOD_CLK periods, where R is programmed in page 0 / register 103, bits D4–D0. When page 0 /
register 103, bit D5 is set to 1, then the value of D should be less than the value of R. When page 0 /
register 103, bit D5 is programmed to 0, the averaging filter is never reset.
7.3.10.1 DAC
The TLV320AIC3100 stereo-audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the
stereo audio-DAC consists of a signal-processing engine with fixed processing blocks, a digital
interpolation filter, a multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is
designed to provide enhanced performance at low sampling rates through increased oversampling and
image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal
images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and
optimize power dissipation and performance, the TLV320AIC3100 device allows the system designer to
program the oversampling rates over a wide range from 1 to 1024 by configuring page 0 / register 13 and
page 0 / register 14. The system designer can choose higher oversampling ratios for lower input data
rates and lower oversampling ratios for higher input data rates.
The TLV320AIC3100 DAC channel includes a built-in digital interpolation filter to generate oversampled
data for the delta-sigma modulator. The interpolation filter can be chosen from three different types,
depending on required frequency response, group delay, and sampling rate.
DAC power up is controlled by writing to page 0 / register 63, bit D7 for the left channel and bit D6 for the
right channel. The left-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit
D7. The right-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D6.
Figure 7-19. Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15
Interp.
IIR BiQuad BiQuad BiQuad BiQuad BiQuad BiQuad ´ to
Filter
A B C D E F Modulator
from A,B
Interface Digital
Volume
Ctrl
Figure 7-20. Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16
Interp.
IIR Filter ´ to
B,C Modulator
from
Interface Digital
Volume
Ctrl
Figure 7-21. Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20
From
Left- + Biquad Biquad Interp.
Channel
+ BL CL Filter A
´ To
Interface Modulator
+
Digital
Volume
Ctrl
+ Biquad Biquad 3D
+ AL AR
– PGA
From +
Right- – Biquad Biquad Interp.
Channel
+ BR CR Filter A
´ To
Modulator
Interface
Digital
Volume
Ctrl
NOTE: AL means biquad A of the left channel, and similarly, BR means biquad B of the right channel.
$
! !
"
"
# !
$
! !
"
"
# !
!
!" "! !
#
#
$! "
$! "
!
!" "! !
#
#
$! "
The user-programmable coefficients C1 to C70 are defined on pages 8, 9, 10, and 11 for buffer A and
pages 12, 13, 14, and 15 for buffer B.
The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit
registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a
range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 7-11.
The frequency response for the first-order IIR section with default coefficients is flat.
–10
–20
Magnitude – dB
–30
–40
–50
–60
–70
–80
–90
1 2 3 4 5 6 7
Frequency Normalized to fS
G016
–10
–20
Magnitude – dB
–30
–40
–50
–60
–70
–80
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Frequency Normalized to fS
G017
–10
–20
Magnitude – dB
–30
–40
–50
–60
–70
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Frequency Normalized to fS
G018
24 dB to Mute
Digital
DAC_L ∆-∑ Programmable
Vol DSP
DAC Ctl Engine
24 dB to Mute
AVDD
Digital
VREF DAC_R Programmable
IN
AVDD ∆-∑ Vol DSP
DAC Ctl
R1 Engine
VOL/
MICDET 18 dB to Mute
P1
7- Bit ADC
R2 CVOL
Tone Generator and Mixer Are
NOT Shown
Volume Level 24 dB to Mute
Register Controlled
AVSS
B0210-05
Copyright © 2016, Texas Instruments Incorporated
Figure 7-32. Digital Volume Controls for Beep Generator and DAC Play Data
As shown in Table 7-32, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB,
and mute. However, if less maximum gain is required, then a smaller range of voltage must be applied to
the VOL/MICDET pin. Applying a smaller range of voltage occurs by increasing the value of R2 relative to
the value of (P1 + R1), so that more voltage is available at the bottom of P1. The circuit must also be
designed such that for the values of R1, R2, and P1 chosen, the maximum voltage (top of the
potentiometer) does not exceed AVDD/2 (see Figure 7-32). The recommended values for R1, R2, and P1
for several maximum gains are shown in Table 7-33. Note that in typical applications, R1 must not be 0 Ω,
as the VOL/MICDET pin must not exceed AVDD/2 for proper ADC operation.
The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable
through register write as given in Table 7-34.
The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_fS,
and a low-pass filter with a cutoff at 0.00033 × DAC_fS.
The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The
absolute value of the DRC LPF filter is used for energy estimation within the DRC.
The gain in the DAC digital volume control is controlled by page 0 / register 65 and page 0 / register 66.
When the DRC is enabled, the applied gain is a function of the digital volume control register setting and
the output of the DRC.
The DRC parameters are described in sections that follow.
#Go to Page 0
w 30 00 00
#DAC => 12 db gain left
w 30 41 18
#DAC => 12 db gain right
w 30 42 18
#DAC => DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB
w 30 44 7F
#DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs'
w 30 45 00
#Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e-5 dB/Frame
w 30 46 B6
#Go to Page 9
w 30 00 09
#DRC HPF
w 30 0E 7F AB 80 55 7F 56
#DRC LPF W 30 14 00 11 00 11 7F DE
s s HPR
g g
s s HPL
Micpga
m m
VOL/MICDET
MICBIAS
Micbias
Headset Detection is enabled by programming page 0 / register 67, bit D1. In order to avoid false
detections because of mechanical vibrations in headset jacks or microphone buttons, a debounce function
is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32
ms to 512 ms is provided. This can be programmed through page 0 / register 67, bits D4–D2. For
improved button-press detection, the debounce function has a range of 8 ms to 32 ms by programming
page 0 / register 67, bits D1–D0.
The TLV320AIC3100 device also provides feedback to the user through register-readable flags as well as
an interrupt on the I/O pins when a button press or a headset insertion or removal event is detected. The
value in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset
insertion. Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is
detected. Page 0 / register 44, bit D4 is a sticky flag which is set when the headset insertion or removal
event is detected. These sticky flags are set by the event occurrence, and are reset only when read. This
requires polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320AIC3100
device also provides an interrupt feature, whereby events can trigger the INT1, the INT2, or both
interrupts. These interrupt events can be routed to one of the digital output pins. See Section 7.3.10.6 for
details.
The TLV320AIC3100 device not only detects a headset insertion event, but also is able to distinguish
between the different headsets inserted, such as stereo headphones or cellular headphones. After the
headset-detection event, the user can read page 0 / register 67, bits D6–D5 to determine the type of
headset inserted.
The headset detection block requires AVDD to be powered. The headset detection feature in the
TLV320AIC3100 device is achieved with very low power overhead, requiring less than 20 μA of additional
current from the AVDD supply.
7.3.10.6 Interrupts
Some specific events in the TLV320AIC3100 device that can require host processor intervention are used
to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The
TLV320AIC3100 device has two defined interrupts, INT1 and INT2, that are configured by programming
page 0 / register 48 and page 0 / register 49. A user can configure interrupts INT1 and INT2 to be
triggered by one or many events, such as:
• Headset detection
• Button press
• DAC DRC signal exceeding threshold
• Noise detected by AGC
• Overcurrent condition in headphone drivers and speaker drivers
• Data overflow in the ADC and DAC processing blocks and filters
• DC measurement data available
Each of these INT1 and INT2 interrupts can be routed to output pins GPIO1 or DOUT. These interrupt
signals can either be configured as a single pulse or a series of pulses by programming page 0 /
register 48, bit D0 and page 0 / register 49, bit D0. If the user configures the interrupts as a series of
pulses, the events trigger the start of pulses that stop when the flag registers in page 0 / registers 44, 45,
and 50 are read by the user to determine the cause of the interrupt.
This functionality is intended for generating key-click sounds for user feedback. The sine-wave generator
is very flexible (see Table 7-36) and is completely register programmable. Programming page 0 / register
71 through page 0 / register 79 (8 bits each) completely controls the functionality of this generator and
allows for differentiating sounds.
The two registers used for programming the 16-bit sine-wave coefficient are page 0 / register 76 and
page 0 / register 77. The two registers used for programming the 16-bit cosine-wave coefficient are
page 0 / register 78 and page 0 / register 79. This coefficient resolution allows virtually any frequency of
sine wave in the audio band to be generated, up to fS / 2.
The three registers used to control the length of the sine-burst waveform are page 0 / register 73 through
page 0 / register 75. The resolution (bit) in the registers of the sine-burst length is one sample time, so this
allows great control on the overall time of the sine-burst waveform. This 24-bit length timer supports
16 777 215 sample times. For example, if fS is set at 48 kHz, and the register value equals 96 000 d
(01 7700h), then the sine burst lasts exactly 2 seconds. The default settings for the tone generator, based
on using a sample rate of 48 kHz, are 1-kHz (approximately) sine wave, with a sine-burst length of five
cycles (5 ms).
Two registers are used to control the left sine-wave volume and the right sine-wave volume independently.
The 6-bit digital volume control used allows level control of 2 dB to –61 dB in 1-dB steps. The left-channel
volume is controlled by writing to page 0 / register 71, bits D5–D0. The right-channel volume is controlled
by writing to page 0, register 72, bits D5–D0. A master volume control that controls the left and right
channels of the beep generator are set up by writing to page 0 / register 72, bits D7–D6. The default
volume control setting is 2 dB, which provides the maximum tone-generator output level.
For generating other tones, the three tone-generator coefficients are found by running the following script
using MATLAB™ :
Sine = dec2hex(round(sin(2*π*Fin/Fs)*2^15))
Cosine = dec2hex(round(cos(2*π*Fin/Fs)*2^15))
Beep Length = dec2hex(floor(Fs*Cycle/Fin))
where,
Fin = Beep frequency desired
Fs = Sample rate
Cycle = Number of beep (sine wave) cycles that are required
dec2hex = Decimal to hexadecimal conversion function
NOTES:
1. Fin must be less than Fs / 4.
2. For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused
MSBs must be written as 0s.
3. For the beep-length values, if number of bits is less than the full 24-bit value, then the unused MSBs
must be written as 0s.
Following the beep-volume control is a digital mixer that mixes in a playback data stream whose level has
already been set by the DAC volume control. Therefore, once the key-click volume level is set, the key-
click volume is not affected by the DAC volume control, which is the main control available to the end
user. shows this functionality.
Following the DAC, the signal can be further scaled by the analog output volume control and power-
amplifier level control.
To insert a beep in the middle of an already-playing signal over DAC, use the following sequence.
Before the beep is desired, program the desired beep frequency, volume, and length in the configuration
registers. When a beep is desired, use the example configuration script.
w 30 00 00 # change to Page 0
w 30 40 0C # mute DACs
f 30 26 xxx1xxx1 # wait for DAC gain flag to be set
w 30 0B 02 # power down NDAC divider
w 30 47 80 # enable beep generator with left channel volume = 0dB, volume level could
# be different as per requirement
w 30 0B 82 # power up NDAC divider, in this specific example NDAC = 2, but NDAC could
# be different value as per overall setup
w 30 40 00 # un-mute DAC to resume playing audio
Note that in this scheme the audio signal on the DAC is temporarily muted to enable beep generation.
Because powering down of NDAC clock divider is required, do not use the DAC_CLK or DAC_MOD_CLK
for generation of I2S clocks.
Play - Paused
Update
Digital Filter DAC Volume Ramp Up Time (B)
Coefficients
For fS = 32 kHz ® 25 ms
Wait 20 ms
Restore Previous
Volume Level (Ramp)
in (B) ms
Play - Continue
F0024-02
Figure 7-34. Example Flow For Updating DAC Digital Filter Coefficients During Play
Table 7-38. Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) (1)
REGISTER ANALOG REGISTER ANALOG GAIN REGISTER ANALOG GAIN REGISTER ANALOG GAIN
VALUE GAIN (dB) VALUE (dB) VALUE (dB) VALUE (dB)
(D6–D0) (D6–D0) (D6–D0) (D6–D0)
0 0 30 –15 60 –30.1 90 –45.2
1 –0.5 31 –15.5 61 –30.6 91 –45.8
2 –1 32 –16 62 –31.1 92 –46.2
3 –1.5 33 –16.5 63 –31.6 93 –46.7
4 –2 34 –17 64 –32.1 94 –47.4
5 –2.5 35 –17.5 65 –32.6 95 –47.9
6 –3 36 –18.1 66 –33.1 96 –48.2
7 –3.5 37 –18.6 67 –33.6 97 –48.7
8 –4 38 –19.1 68 –34.1 98 –49.3
9 –4.5 39 –19.6 69 –34.6 99 –50
10 –5 40 –20.1 70 –35.2 100 –50.3
11 –5.5 41 –20.6 71 –35.7 101 –51
12 –6 42 –21.1 72 –36.2 102 –51.4
13 –6.5 43 –21.6 73 –36.7 103 –51.8
14 –7 44 –22.1 74 –37.2 104 –52.2
15 –7.5 45 –22.6 75 –37.7 105 –52.7
16 –8 46 –23.1 76 –38.2 106 –53.7
17 –8.5 47 –23.6 77 –38.7 107 –54.2
18 –9 48 –24.1 78 –39.2 108 –55.3
19 –9.5 49 –24.6 79 –39.7 109 –56.7
20 –10 50 –25.1 80 –40.2 110 –58.3
21 –10.5 51 –25.6 81 –40.7 111 –60.2
22 –11 52 –26.1 82 –41.2 112 –62.7
23 –11.5 53 –26.6 83 –41.7 113 –64.3
24 –12 54 –27.1 84 –42.1 114 –66.2
25 –12.5 55 –27.6 85 –42.7 115 –68.7
26 –13 56 –28.1 86 –43.2 116 –72.2
27 –13.5 57 –28.6 87 –43.8 117–127 –78.3
28 –14 58 –29.1 88 –44.3
29 –14.5 59 –29.6 89 –44.8
(1) Mute when D7 = 0 and D6–D0 = 127 (0x7F).
The TLV320AIC3100 device has a short-circuit protection feature for the speaker drivers that is always
enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent
condition. (Current limiting is not an available option for the higher-current speaker driver output stage.) In
case of a short circuit on either channel, the output is disabled and a status flag is provided as a read-only
bit on page 1 / register 32, bit D0.
If shutdown occurs because of an overcurrent condition, then the device requires a reset to re-enable the
output stage. Resetting occurs in two ways. First, the device master reset can be used, which requires
either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the
registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device
settings. The speaker power-stage reset occurs by setting page 1 / register 32, bit D7 The speaker power-
stage reset is done by setting page 1 / register 32, bit D7 for SPKP and SPKM. If the fault condition has
been removed, then the device returns to normal operation. If the fault is still present, then another
shutdown occurs. Repeated resetting (more than three times) is not recommended as this could lead to
overheating.
To minimize battery current leakage, the SPKVDD voltage levels must not be less than the AVDD
voltage level.
The TLV320AIC3100 device has a thermal protection (OTP) feature for the speaker drivers which is
always enabled to provide protection. If the device overheats, then the output stops switching. When the
device cools down, the device resumes switching. An overtemperature status flag is provided as a read-
only bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die
temperature can be controlled at the system or board level, then overtemperature does not occur.
the reference clocks on MCLK, BCLK, or GPIO1, the TLV320AIC3100 device also provides the option of
using the on-chip PLL which supports a wide range of fractional multiplication values to generate the
required clocks. Starting from CODEC_CLKIN, the TLV320AIC3100 device provides several
programmable clock dividers to help achieve a variety of sampling rates for the ADC, DAC, and clocks for
the audio processing blocks.
BCLK DIN
MCLK GPIO1
PLL_CLKIN
PLL
´ (R ´ J.D)/P
BCLK
MCLK GPIO1
PLL_CLK
CODEC_CLKIN
¸ NDAC NDAC = 1, 2, ..., 127, 128 ¸ NADC NADC = 1, 2, ..., 127, 128
To DAC_PRB
DAC_CLK
Clock Generation
To ADC_PRB
ADC_CLK Clock Generation
¸ MDAC MDAC = 1, 2, ..., 127, 128 ¸ MADC MADC = 1, 2, ..., 127, 128
ADC_MOD_CLK
DAC_MOD_CLK
¸ DOSR DOSR = 1, 2, ..., 1023, 1024 ¸ AOSR AOSR = 1, 2, ..., 1023, 1024
DAC_fS ADC_fS
B0357-05
The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel,
DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 /
register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the
device internally initiates a power-down sequence for proper shutdown. During this shutdown sequence,
the NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not
take place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 /
register 37, bit D3. When both of the flags indicate power-down, the MDAC divider may be powered down,
followed by the NDAC divider. Note that when the ADC clock dividers are powered down, the ADC clock
is derived from the DAC clocks.
The ADC modulator is clocked by ADC_MOD_CLK. For proper power-up of the ADC channel, these
clocks are enabled by the NADC and MADC clock dividers (page 0 / register 18, bit D7 = 1 and page 0 /
register 19, bit D7 = 1). When the ADC channel is powered down, the device internally initiates a power-
down sequence for proper shutdown. During this shutdown sequence, the NADC and MADC dividers must
not be powered down, or else a proper low-power shutdown may not take place. The user can read back
the power-status flag from page 0 / register 36, bit D6. When this flag indicates power down, the MADC
divider may be powered down, followed by NADC divider.
When ADC_CLK (ADC DSP clock) is derived from the NDAC divider output, the NDAC must be kept
powered up until the power-down status flags for ADC do not indicate power down. When the input to the
AOSR clock divider is derived from DAC_MOD_CLK, then MDAC must be powered up when ADC_fS is
needed (for example, when WCLK is generated by the TLV320AIC3100 device or AGC is enabled) and
can be powered down only after the ADC power-down flags indicate power-down status.
In general, for proper operation, all the root clock dividers must power down only after the child clock
dividers have powered down.
The TLV320AIC3100 device also has options for routing some of the internal clocks to the output pins of
the device to be used as general-purpose clocks in the system. The feature is shown in Figure 7-37.
DAC_MOD_CLK ADC_MOD_CLK
DAC_CLK ADC_CLK
BDIV_CLKIN
BCLK
In the mode when the TLV320AIC3100 device is configured to drive the BCLK pin (page 0 / register 27,
bit D3 = 1), the device is driven as the divided value of BDIV_CLKIN. The division value is programmed in
page 0 / register 30, bits D6–D0 from 1 to 128. The BDIV_CLKIN is configurable to be one of DAC_CLK
(DAC DSP clock), DAC_MOD_CLK, ADC_CLK (ADC DSP clock) or ADC_MOD_CLK by configuring the
BDIV_CLKIN multiplexer in page 0 / register 29, bits D1–D0. Additionally, a general-purpose clock can be
driven out on either GPIO1 or DOUT.
This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be
programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. CDIV_CLKIN can also be
programmed as one of the clocks among the list shown in Figure 7-37. This is controlled by programming
the multiplexer in page 0 / register 25, bits D2–D0.
CDIV_CLKIN
CLKOUT
GPIO1 DOUT
7.3.11.1 PLL
For lower power consumption, the best process is to derive the internal audio processing clocks using the
simple dividers. When the input MCLK or other source clock is not an integer multiple of the audio
processing clocks then using the on-board PLL is necessary. The TLV320AIC3100 fractional PLL
generates an internal master clock that produces the processing clocks required by the ADC, DAC, and
processing blocks. The programmability of this PLL allows operation from a wide variety of clocks that
may be available in the system.
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register-programmable to enable
generation of the required sampling rates with fine resolution. The PLL turns on by writing to page 0 /
register 5, bit D7. When the PLL is enabled, the PLL output clock, PLL_CLK, is given by Equation 9.
PLL_CLKIN ´ R ´ J.D
PLL_CLK =
P
where
• R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)
• J = 1, 2,3, … , 63, (page 0 / register 6, default value = 4)
• D = 0, 1, 2, …, 9999 (page 0 / register 7 and page 0 / register 8, default value = 0)
• P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1) (9)
The PLL turns on through page 0 / register 5, bit D7. The variable P is programmed through page 0 /
register 5, bits D6–D4. The variable R is programmed through page 0 / register 5, bits D3–D0. The
variable J is programmed through page 0 / register 6, bits D5–D0. The variable D is 14 bits and is
programmed into two registers. The MSB portion is programmed through page 0 / register 7, bits D5–D0,
and the LSB portion is programmed thrugh page 0 / register 8, bits D7–D0. For proper update of the D-
divider value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8.
The new value of D does not take effect unless the write to page 0 / register 8 is complete.
When the PLL is enabled, the following conditions must be satisfied:
• When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
PLL _ CLKIN
512 kHz £ £ 20 MHz
P (10)
80 MHz ≤ (PLL_CLKIN × J.D. × R / P) ≤ 110 MHz
4 ≤ R × J ≤ 259
• When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:
PLL _ CLKIN
10 MHz £ £ 20 MHz
P (11)
80 MHz ≤ PLL_CLKIN × J.D. × R / P ≤ 110 MHz
R=1
The PLL can power up independently from the ADC and DAC blocks, and can also be used as a general-
purpose PLL by routing the PLL output to the GPIO output. After powering up the PLL, PLL_CLK is
available typically after 10 ms.
The clocks for the codec and various signal processing blocks, CODEC_CLKIN, are generated from the
MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).
If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last.
Table 7-42 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to
achieve a sample rate fS of either 44.1 kHz or 48 kHz.
7.3.12 Timer
The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce
logic, and interrupts. The MCLK divider must be set in such a way that the divider output is approximately
1 MHz for the timers to be closer to the programmed value.
Powered on if
internal oscillator is
selected
Internal
Oscillator ÷8 0
MCLK Programmable
1
Divider
P3/R16, Bit D7
The TLV320AIC3100 device further includes programmability (page 0 / register 27, bit D0) to place the
DOUT line in the high-impedance state during all bit clocks when valid data is not being sent. By
combining this capability with the ability to program at what bit clock in a frame the audio data begins,
time-division multiplexing (TDM) is accomplished, enabling the use of multiple codecs on a single audio
serial data bus. When the audio serial data bus is powered down while configured in master mode, the
pins associated with the interface are put into a high-impedance output condition. Also, DOUT control on
page 0 / register 53, bit D4 allows the bus-keeper feature to be enabled or disabled. When enabled, the
last valid data on DOUT is held (weakly driven) during the non-data time. When disabled, DOUT is placed
in a high-impedance state when page 0 / register 27, bit D0 is enabled (1).
By default, when the word clocks and bit clocks are generated by the TLV320AIC3100 device, these
clocks are active only when the codecs (ADC, DAC or both) are powered up within the device. This is
done to save power. However, it also supports a feature when both the word clocks and bit clocks can be
active even when the codec in the device is powered down. This is useful when using the TDM mode with
multiple codecs on the same bus, or when word clocks or bit clocks are used in the system as general-
purpose clocks.
1/fs
WCLK
BCLK
For the right-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice
the programmed word length of the data.
WORD
LEFT CHANNEL RIGHT CHANNEL
CLOCK
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - -
1 2 3 1 2 3 1 2 3
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
WORD
LEFT CHANNEL RIGHT CHANNEL
CLOCK
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - -
1 2 3 1 2 3 1 2 3
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3
1 2 3 1 2 3 1 2 3
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
Figure 7-42. Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock
For the left-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
WORD
LEFT CHANNEL RIGHT CHANNEL
CLOCK
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3
1 2 3 1 2 3 1 2 3
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
WORD
LEFT CHANNEL RIGHT CHANNEL
CLOCK
BIT
CLOCK
DATA N N N
- 5 4 3 2 1 0 - 5 4 3 2 1 0 - 5
1 1 1
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
2
Figure 7-44. Timing Diagram for I S Mode With Offset = 2
WORD
LEFT CHANNEL RIGHT CHANNEL
CLOCK
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3
1 2 3 1 2 3 1 2 3
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
2
Figure 7-45. Timing Diagram for I S Mode With Offset = 0 and Bit Clock Inverted
For I2S mode, the number of bit clocks per channel should be greater-than or equal-to the programmed
word length of the data. Also, the programmed offset value should be less than the number of bit clocks
per frame by at least the programmed word length of the data.
Figure 7-46 shows the timing diagram for I2S mode for the monaural audio ADC.
T0202-03
n–1
LSB
0
ADC Mono Channel (D1)
1
2
n–1 n–2 n–3
MSB
1/fS
LSB
ADC Mono Channel (D1)
0
1
2
n–1 n–2 n–3
MSB
LSB
0
ADC Mono Channel (D0)
1
2
n–1 n–2 n–3
MSB
1/fS
LSB
ADC Mono Channel (D0)
0
1
2
1 Clock Before MSB
MSB
DOUT
WCLK
BCLK
Figure 7-46. Timing Diagram for I2S Mode for Monaural Audio ADC
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3
1 2 3 1 2 3 1 2 3
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - -
1 2 3 1 2 3 1 2 3
LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data
WORD
LEFT CHANNEL RIGHT CHANNEL
CLOCK
BIT
CLOCK
N N N N N N N N N
DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3
1 2 3 1 2 3 1 2 3
Figure 7-49. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For the DSP mode, the number of bit clocks per frame should be greater-than or equal-to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
BCLK BCLK
BCLK
BCLK_INT
S_BCLK
S_BCLK
BCLK_OUT
WCLK WCLK
WCLK
S_WCLK DAC_WCLK_INT
S_WCLK
DAC_fS
ADC_fS Audio
DOUT DIN
Digital
WCLK
Serial
ADC_WCLK_INT
DOUT_int Interface
ADC_WCLK
DOUT
DIN
S_DIN
Primary
Audio DIN
Processor DIN_INT
S_DIN
GPIO1 ADC_WCLK
ADC_fS
GPIO1
S_BCLK BCLK
BCLK BCLK2
DOUT
BCLK_OUT
Secondary BCLK_OUT
Audio
Processor DAC_fS
Clock
Generation
GPIO1 WCLK
WCLK2 S_WCLK
WCLK DOUT ADC_fS
DAC_fS
ADC_fS
GPIO1 S_DIN
DOUT
DOUT_int
GPIO1
DIN
(S_DOUT) DIN
SCL
Start 7-bit Device Address Write Slave 8-bit Register Address Slave 8-bit Register Data Slave Stop
(M) (M) (M) Ack (M) Ack (M) Ack (M)
(S) (S) (S)
SCL
Start 7-bit Device Address Write Slave 8-bit Register Address Slave Repeat 7-bit Device Address Read Slave 8-bit Register Data Master Stop
(M) (M) (M) Ack (M) Ack Start (M) (M) Ack (S) No Ack (M)
(S) (S) (M) (S) (M)
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next
incremental register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the
addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of the SDA bus
and transmits for the next eight clocks the data of the next incremental register.
NOTE
Note that the page and register numbers are shown in decimal format. For use in microcode,
these decimal values may need to be converted to hexadecimal format. For convenience,
the register numbers are shown in both formats, whereas the page numbers are shown only
in decimal format.
7.4.2 Registers
7.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags,
Interrupts, and GPIOs
Table 7-77. Page 0 / Register 33: Codec Secondary Interface Control 3 (continued)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D0 R/W 0 0: Secondary DOUT = primary DIN
1: Secondary DOUT = DOUT from codec serial interface block
(1) Note that these times are generated using the 1 MHz reference clock which is defined in Page 3 / Register 16.
94 Detailed Description Copyright © 2009–2016, Texas Instruments Incorporated
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Product Folder Links: TLV320AIC3100
TLV320AIC3100
www.ti.com SLAS667C – NOVEMBER 2009 – REVISED OCTOBER 2016
(1)
Table 7-112. Page 0 / Register 71: Left Beep Generator
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Beep generator is disabled.
1: Beep generator is enabled (self-clearing based on beep duration).
D6 R/W 0 Reserved. Write only reset value.
D5–D0 R/W 00 0000 00 0000: Left-channel beep volume control = 2 dB
00 0001: Left-channel beep volume control = 1 dB
00 0010: Left-channel beep volume control = 0 dB
00 0011: Left-channel beep volume control = –1 dB
...
11 1110: Left-channel beep volume control = –60 dB
11 1111: Left-channel beep volume control = –61 dB
(1) The beep generator is only available in PRB_P25 DAC processing mode.
Table 7-123. Page 0 / Register 82: ADC Digital Volume Control Fine Adjust
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 1 0: ADC channel not muted
1: ADC channel muted
Delta-Sigma Mono ADC Channel Volume Control Fine Gain
000: 0 dB
001: –0.1 dB
D6–D4 R/W 000 010: –0.2 dB
011: –0.3 dB
100: –0.4 dB
101–111: Reserved
D3–D0 R/W 0000 Reserved. Write only zeros to these bits.
Table 7-124. Page 0 / Register 83: ADC Digital Volume Control Coarse Adjust
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved
D6–D0 000 0000 Delta-Sigma Mono ADC Channel Volume-Control Coarse Gain
100 0000–110 0111: Reserved
110 1000: –12 dB
110 1001: –11.5 dB
...
111 1111: –0.5 dB
000 0000: 0 dB
000 0001: 0.5 dB
...
010 0111: 19.5 dB
010 1000: 20 dB
010 1001–011 1111: Reserved
Table 7-140. Page 0 / Register 107 Through Page 0 / Register 115: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Do not write to these registers.
Table 7-141. Page 0 / Register 116: VOL/MICDET-Pin SAR ADC — Volume Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: DAC volume control is controlled by control register. (7-bit Vol ADC is powered down)
1: DAC volume control is controlled by pin.
D6 R/W 0 0: Internal on-chip RC oscillator is used for the 7-bit Vol ADC for pin volume control.
1: MCLK is used for the 7-bit Vol ADC for pin volume control.
D5–D4 R/W 00 00: No hysteresis for volume control ADC output
01: Hysteresis of ±1 bit
10: Hysteresis of ±2 bits
11: Reserved. Do not write this sequence to these bits.
D3 R/W 0 Reserved. Write only reset value.
D2–D0 R/W 000 Throughput of the 7-bit Vol ADC for pin volume control, frequency based on MCLK or internal oscillator.
MCLK = 12 MHz Internal Oscillator Source
000: Throughput = 15.625 Hz 10.68 Hz
001: Throughput = 31.25 Hz 21.35 Hz
010: Throughput = 62.5 Hz 42.71 Hz
011: Throughput = 125 Hz 8.2 Hz
100: Throughput = 250 Hz 170 Hz
101: Throughput = 500 Hz 340 Hz
110: Throughput = 1 kHz 680 Hz
111: Throughput = 2 kHz 1.37 kHz
Note: These values are based on a nominal oscillator
frequency of 8.2 MHz. The values scale to the actual
oscillator frequency.
Table 7-143. Page 0 / Register 118 Through Page 0 / Register 127: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Do not write to these registers.
7.4.2.2 Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls, and MISC Logic-
Related Programmability
Table 7-146. Page 1 / Register 30: Headphone and Speaker Amplifier Error Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D2 R/W 0000 00 Reserved
D1 R/W 0 0: Reset speaker driver power-up control bits on short-circuit detection.
1: Speaker driver power-up control bits remain unchanged on short-circuit detection.
D0 R/W 0 0: Reset HPL and HPR power-up control bits on short-circuit detection if page 1 / register 31, D1 = 1.
1: HPL and HPR power-up control bits remain unchanged on short-circuit detection.
Table 7-149. Page 1 / Register 33: HP Output Drivers POP Removal Settings
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: If the power down sequence is activated by device software, power down using page 1 / register 46,
││ bit D7, then power down the DAC simultaneously with the HP and SP amplifiers.
1: If the power down sequence is activated by device software, power down using page 1 / register 46,
││ bit D7, then power down DAC only after HP and SP amplifiers are completely powered down. This is to
││ optimize power-down POP.
D6–D3 R/W 0111 0000: Driver power-on time = 0 μs
0001: Driver power-on time = 15.3 μs
0010: Driver power-on time = 153 μs
0011: Driver power-on time = 1.53 ms
0100: Driver power-on time = 15.3 ms
0101: Driver power-on time = 76.2 ms
0110: Driver power-on time = 153 ms
0111: Driver power-on time = 304 ms
1000: Driver power-on time = 610 ms
1001: Driver power-on time = 1.22 s
1010: Driver power-on time = 3.04 s
1011: Driver power-on time = 6.1 s
1100–1111: Reserved. Do not write these sequences to these bits.
Note: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual
oscillator frequency.
D2–D1 R/W 11 00: Driver ramp-up step time = 0 ms
01: Driver ramp-up step time = 0.98 ms
10: Driver ramp-up step time = 1.95 ms
11: Driver ramp-up step time = 3.9 ms
Note: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual
oscillator frequency.
D0 R/W 0 0: Weakly driven output common-mode voltage is generated from resistor divider of the AVDD supply.
1: Reserved
Table 7-150. Page 1 / Register 34: Output Driver PGA Ramp-Down Period Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved. Write only the reset value to this bit.
D6–D4 R/W 000 Speaker power-up wait time (duration based on using internal oscillator)
000: Wait time = 0 ms
001: Wait time = 3.04 ms
010: Wait time = 7.62 ms
011: Wait time = 12.2 ms
100: Wait time = 15.3 ms
101: Wait time = 19.8 ms
110: Wait time = 24.4 ms
111: Wait time = 30.5 ms
Note: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual
oscillator frequency.
D3–D0 R/W 0000 Reserved. Write only the reset value to these bits.
Table 7-151. Page 1 / Register 35: DAC_L and DAC_R Output Mixer Routing
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 00: DAC_L is not routed anywhere.
01: DAC_L is routed to the left-channel mixer amplifier.
10: DAC_L is routed directly to the HPL driver.
11: Reserved
D5 R/W 0 0: MIC1LP input is not routed to the left-channel mixer amplifier.
1: MIC1LP input is routed to the left-channel mixer amplifier.
D4 0 0: MIC1RP input is not routed to the left-channel mixer amplifier.
1: MIC1RP input is routed to the left-channel mixer amplifier.
D3–D2 R/W 00 00: DAC_R is not routed anywhere.
01: DAC_R is routed to the right-channel mixer amplifier.
10: DAC_R is routed directly to the HPR driver.
11: Reserved
D1 R/W 0 0: MIC1RP input is not routed to the right-channel mixer amplifier.
1: MIC1RP input is routed to the right-channel mixer amplifier.
D0 R/W 0 0: HPL driver output is not routed to the HPR driver.
1: HPL driver output is routed to the HPR driver input (used for differential output mode).
Table 7-164. Page 1 / Register 48: Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-
Terminal
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 00: MIC1LP is not selected for the MIC PGA.
(1)
01: MIC1LP is selected for the MIC PGA with feed-forward resistance RIN = 10 kΩ.
10: MIC1LP is selected for the MIC PGA with feed-forward resistance RIN = 20 kΩ.
11: MIC1LP is selected for the MIC PGA with feed-forward resistance RIN = 40 kΩ.
D5–D4 R/W 00 00: MIC1RP is not selected for the MIC PGA.
01: MIC1RP is selected for the MIC PGA with feed-forward resistance RIN = 10 kΩ
10: MIC1RP is selected for the MIC PGA with feed-forward resistance RIN = 20 kΩ
11: MIC1RP is selected for the MIC PGA with feed-forward resistance RIN = 40 kΩ
D3–D2 R/W 00 00: MIC1LM is not selected for the MIC PGA.
01: MIC1LM is selected for the MIC PGA with feed-forward resistance RIN = 10 kΩ
10: MIC1LM is selected for the MIC PGA with feed-forward resistance RIN = 20 kΩ
11: MIC1LM is selected for the MIC PGA with feed-forward resistance RIN = 40 kΩ
D1–D0 R/W 00 Reserved. Write only zeros to these bits.
(1) Input impedance selection affects the microphone PGA gain. See Section 7.3.9.1 for details.
Table 7-165. Page 1 / Register 49: ADC Input Selection for M-Terminal
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 00: CM is not selected for the MIC PGA.
(1)
01: CM is selected for the MIC PGA with feed-forward resistance RIN = 10 kΩ.
10: CM is selected for the MIC PGA with feed-forward resistance RIN = 20 kΩ.
11: CM is selected for the MIC PGA with feed-forward resistance RIN = 40 kΩ.
D5–D4 00 00: MIC1LM is not selected for the MIC PGA.
01: MIC1LM is selected for the MIC PGA with feed-forward resistance RIN = 10 kΩ.
10: MIC1LM is selected for the MIC PGA with feed-forward resistance RIN = 20 kΩ.
11: MIC1LM is selected for the MIC PGA with feed-forward resistance RIN = 40 kΩ.
D3–D0 R/W 0000 Reserved. Write only zeros to these bits.
(1) Input impedance selection affects the microphone PGA gain. See Section 7.3.9.1 for details.
7.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
Default values shown for this page only become valid 100 μs following a hardware or software reset.
The only register used in page 3 is register 16. The remaining page-3 registers are reserved and must not
be written to.
The remaining page-4 registers are either reserved registers or are used for setting coefficients for the
various filters in the TLV320AIC3100. Reserved registers must not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient
are interpreted as a 2s-complement integer, with possible values ranging from –32 768 to 32 767. When
programming any coefficient value for a filter, the MSB register must always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both
registers must be written in this sequence. is a list of the page-4 registers, excepting the previously
described register 0.
The remaining page-8 registers are either reserved registers or are used for setting coefficients for the
various filters in the TLV320AIC3100. Reserved registers must not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient
are interpreted as a 2s-complement integer, with possible values ranging from –32 768 to 32 767. When
programming any coefficient value for a filter, the MSB register must always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both
registers must be written in this sequence. is a list of the page-8 registers, excepting the previously
described register 0.
The remaining page-9 registers are either reserved registers or are used for setting coefficients for the
various filters in the TLV320AIC3100. Reserved registers must not be written to.
The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient
are interpreted as a 2s-complement integer, with possible values ranging from –32 768 to 32 767. When
programming any coefficient value for a filter, the MSB register must always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both
registers must be written in this sequence. is a list of the page-9 registers, excepting the previously
described register 0.
7.4.2.7 Control Registers, Page 12: DAC Programmable Coefficients Buffer B (1:63)
7.4.2.8 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
SVDD +3.3VA
4W SPKP
SPKP GPIO1
SPKM
SPKM
SDA
VOL/MICDET
SCL
2.2 kW
MICBIAS
HOST PROCESSOR
0.1 mF
MCLK
MIC1RP
47 mF
HPLOUT
DOUT
Headset 47 mF
HPROUT WCLK
DIN
BCLK
1 mF
Analog_In1 MIC1LP
RESET
1 mF
Analog_In2 MIC1LM
+1.8VD IOVDD
0.1 mF 10 mF 0.1 mF 10 mF
S0400-07
Copyright © 2016, Texas Instruments Incorporated
0 3.5
THD+N − Total Harmonic Distortion + Noise − dB
HPVDD = 2.7 V
−10
CM = 1.35 V
3.0 Micbias = AVDD (3.3 V)
−20
−30 2.5
HPVDD = 3 V Micbias = 2.5 V
V − Voltage − V
10 Layout
10.1 Layout Guidelines
PCB design is made considering the application and the review is specific for each system requirements.
However, general considerations can optimize the system performance.
• The TLV320AIC3100 thermal pad must be connected to analog output driver ground using multiple
VIAS to minimize impedance between the device and ground.
• Analog and digital grounds must be separated to prevent possible digital noise form affecting the
analog performance of the board.
• The TLV320AIC3100 requires the decoupling capacitors to be placed as close as possible to the
device power supply terminals.
• If possible, route the differential audio signals differentially on the PCB. This is recommended to get
better noise immunity.
SPKM
SPKP
10.1 μF
SPKVSS
Analog
DVSS
Ground If possible, route
SPKVDD
SPKVDD
22.1 μF
22.1 μF
differential audio
AVDD
Plane signals differentially
SPKVSS AVSS
1 μF
SPKP MIC1LM
47 μF 1 μF
HPL MIC1RP
HPVDD 1 μF
Thermal pad MIC1LP
10.1 μF connected to analog
HPVSS ground plane MICBIAS
47 μF
HPR VOL/MICDET
DVDD
points
Digital
10.1 μF
DOUT 10.1 μF
Ground
Place the decoupling
capacitors close to Plane
RESET’
GPIO1
WCLK
MCLK
BCLK
power terminals
SDA
SCL
DIN
System Processor
11.3 Trademarks
E2E is a trademark of Texas Instruments.
MATLAB is a trademark of The MathWorks, Inc.
All other trademarks are the property of their respective owners.
11.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2009–2016, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 125
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Product Folder Links: TLV320AIC3100
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TLV320AIC3100IRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC3100
& no Sb/Br)
TLV320AIC3100IRHBT ACTIVE VQFN RHB 32 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC3100
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Oct-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Oct-2016
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32 VQFN - 1 mm max height
5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5.1 B
A
4.9
5.1 (0.1)
4.9
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
2X 3.5
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17 SEE SIDE WALL
DETAIL
2X SYMM
33
3.5
0.3
32X
0.2
24 0.1 C A B
1
0.05 C
32 25
PIN 1 ID SYMM
(OPTIONAL) 0.5
32X
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32 25
32X (0.6)
1 24
32X (0.25)
(1.475)
28X (0.5)
33 SYMM
(4.8)
( 0.2) TYP
VIA
8 17
(R0.05)
TYP
9 16
(1.475)
(4.8)
SOLDER MASK
METAL OPENING
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)
1 24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
8 17
METAL
TYP
9 16
SYMM
(4.8)
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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