Microprocessor and Interfacing Notes Lab Reports
Microprocessor and Interfacing Notes Lab Reports
Revised Manuscript Received on April 14, 2019. DNA means deoxyribonucleic acid formed using 4 basic
Fazal Noorbasha, Department of ECE, Koneru Lakshmaiah Education nucleic acids namely Adenine (A), Cytosine (C), Guanine
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India (G), Thymine (T), the pairs as (A,T) as well as (C,G) are
S. Mohit Srinath, Department of ECE, Koneru Lakshmaiah Education complement each other. Figure 1 shows the structure of
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India
SK. Khadir Bhasha, Department of ECE, Koneru Lakshmaiah
DNA and Binary values assigned to A, C, G and T.
Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India
P. Jagadish, Department of ECE, Koneru Lakshmaiah Education
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India
K Hari Kishore, Department of ECE, Koneru Lakshmaiah Education
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India
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FPGA Based DNA Cryptography System for Medical Image Data Analysis Process
The Advanced Encryption Standard (AES) is 6 times replacing inputs by explicit yields (substitutions) and others
faster than triple DES. A modification for DES was required include rearranging bits around (stages). Interestingly, AES
as its key size was very small. With expanding processing performs all its computations on bytes instead of bits.
power, it was considered vulnerable against exhaustive key Consequently, AES treats the 128 bits of a plaintext block as
search attach [8]. Triple DES was designed to overcome this 16 bytes. These 16 bytes are arranged in four sections and
drawback but it was found slow. The highlights of AES are four columns for handling as a framework [9-10]. Unlike
symmetric key symmetric block cipher, 128-bit data, DES, the quantity of rounds in AES is variable and depends
128/192/256-bit keys, Stronger and faster than Triple-DES. upon the length of the key. AES utilizes 10 rounds for 128-
AES is an iterative instead of feistel cipher. It depends on piece keys, 12 rounds for 192-piece keys and 14 rounds for
'substitution– permutation network'. It includes a 256-piece keys. Every one of these rounds utilizes an
progression of connected activities, some of which include alternate 128-piece round key, which is determined from the
first AES key.
Fig. 2 DNA Encryption process [A] Flowchart and [B] Process Flow
The MRI scan image is converted into pixels and then into STEP3: Binary Key generation (AES algorithm).
binary values and then it is converted into DNA code. The STEP4: Encryption: X-OR operation between image binary
process of encryption is shown in Figure 2A. Figure 2B, data and binary key
shows the Image to DNA encryption cryptography process. STEP 5: Binary encryption data is converted into DNA code
The scanned image is converted to pixels using MATLAB in the form of A, C, G and T, Assigning binary as A=00,
and then binary to DNA process. C=01, G=10, T=11 respectively.
Steps of involved in the DNA based encryption process:
STEP1: Conversion of analog image into digital pixels
STEP2: Assigning the binary values to each pixel.
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International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8 Issue-6S, April 2019
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FPGA Based DNA Cryptography System for Medical Image Data Analysis Process
V. CONCLUSIONS 12. Bindu Bhargavi, K., Hari Kishore, K. Low Power Bist on Memory
Interface Logic (2015) International Journal of Applied Engineering
We have proposed a DNA based cryptography algorithm Research, 10 (8), pp. 21079-21090.
using AES key, that increase complexity in each round thus 13. Charan, N.S., Kishore, K.H. Recognization of delay faults in cluster
it can increase the security. So that it increases the efficiency based FPGA using BIST (2016) Indian Journal of Science and
Technology, 9 (28).
and gives high accuracy. By using same security algorithm, 14. Hari Kishore, K., Aswin Kumar, C.V.R.N., Vijay Srinivas, T.,
we are optimizing the resource utilization. To implement Govardhan, G.V., Pavan Kumar, C.N., Venkatesh, R.V. Design and
this designed we have used Verilog HDL. The total process analysis of high efficient UART on spartan-6 and virtex-7 devices
is tested on FPGA Spartan 3 Kit. The total power consumed (2015) International Journal of Applied Engineering Research, 10 (9),
pp. 23043-23052.
by encryption module is 11.493 W. The total power 15. Kante, S., Kakarla, H.K., Yadlapati, A. Design and verification of
consumed by decryption module is 3.619 W. The memory AMBA AHB-lite protocol using Verilog HDL (2016) International
utilization of encryption module is 682.5 MB with the gain Journal of Engineering and Technology, 8 (2), pp. 734-741.
of 383.3 as well as for the decryption module the memory 16. Bandlamoodi, S., Hari Kishore, K. An FPGA implementation of phase-
locked loop (PLL) with self-healing VCO (2015) International Journal
utilization is 685.7 MB with the gain of 386.3. For medical of Applied Engineering Research, 10 (14), pp. 34137-34139.
images data analysis this algorithm secures the data. New 17. Murali, A., Hari Kishore, K., Rama Krishna, C.P., Kumar, S., Trinadha
methodologies can help this algorithm in future to diminish Rao, A. Integrating the reconfigurable devices using slow-changing
the activity while keeping up the adequate level of security. key technique to achieve high performance (2017) Proceedings - 7th
IEEE International Advanced Computing Conference, IACC 2017, art.
no. 7976849, pp. 530-534.
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