ELEC4614 Power Electronics

Lecture 23 - Three-phase SPWM Inverters

Output voltage control of the three-phase inverter
Available methods are:
 Input DC voltage regulation - not suitable for
voltage source inverters except for slow adjustment
of output voltage.
 SPWM – the method now widely used for low to
medium power applications.
Unlike the case of a single-phase inverter, variable phase
displacement between inverter legs cannot be used as a
means for output voltage variation. This is due to the
restriction that phase displacement of 2/3 (120)
between phases must be maintained in order to obtain
balanced three-phase output voltage.

Three-phase SPWM Inverter

Three-phase SPWM inverters are controlled in the same
way as a single-phase SPWM inverter. Three sinusoidal
modulating signals at the frequency of the desired output
but displaced from each other by 120 are compared with
a triangular carrier waveform of suitably high frequency.
The resulting switching signals from each comparator are
used to drive the inverter switches of the corresponding
leg. The switching signals for each inverter leg are
complementary, and the switching signals for each
switch has 180 of conduction. These are shown in figure
23.2 for the inverter of figure 23.1.
Lecture 23 - Three-phase SPWM inverters 23-1 F. Rahman
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P id +Vd/2

T1 T3 T5
D1 D3 D5

A ia B ib C ic
Vd 0V
T4 T6 T2
D4 D6 D2

N Vd/2
B C
A

Figure 23.1
vcw ec,A ec,B ec,C

T1

T2

T3

T4

T5

T6

Lecture 23 - Three-phase SPWM inverters 23-2 F. Rahman

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+Vd vAB

Vd

+Vd vBC

Vd

+Vd vCA

Vd

Figure 23.2

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vcw ec,A ec,B ec,C

vAN
Vd

vBN
Vd

+Vd vAB

Vd

Figure 23.3
V1

mf 2m f 3m f
mf+ 2 2m f + 2 3m f + 2

H a rm o n ic s v l-l

Figure 23.4
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It should be noted from the above waveforms in figure

23.2-3 that an identical amount of DC voltage exists in
each line-neutral voltage vAN and vBN when these are
measured with respect to the negative DC link voltage
bus. The DC components are canceled when vAB is
obtained by subtracting vBN from vAN. It should also be
noted that the vAB waveform is 30 ahead of the control
voltage ( ecA ) for phase A.
The considerations for selecting the triangular carrier
frequency and their synchronization with the modulating
waveforms are similar to what have been described for
single-phase SPWM inverters. Thus, mf should be an odd
integer which is also a multiple of three when it is less
than 21 and that the slopes of the modulating waveforms
and the carrier waveforms at the zero crossings of the
modulating waveforms should be opposite.

When frequency variation in addition to voltage variation

is required, the above restrictions should be maintained at
all frequencies. In order to improve the inverter
efficiency, it is desirable to keep mf constant when the
output frequency is low, otherwise, too many switchings
would occur unnecessarily.

Linear Modulation Range, m < 1

Considering that the positive DC bus voltage is +Vd/2
and the negative DC bus voltage is Vd/2 with respect to
the center-tap of the DC supply, the output voltage
waveform of a phase leg is a pulsewidth modulated
Lecture 23 - Three-phase SPWM inverters 23-5 F. Rahman
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Vd
bipolar AC waveform of magnitude 2
. The RMS value
of the fundamental of this voltage varies linearly with the
depth of modulation m. Thus,

Vd
VAn,1  m   0.354 m  Vd (23.1)
2 2

where m is the depth of modulation. This has been

indicated as the line-neutral voltage because, with
SPWM and balanced three-phase load, the potential of
the load neutral point and that of the DC supply center-
tap should be the same. The RMS value of the
fundamental line-line voltage is

3Vd
VAB ,1  m   0.612m  Vd (23.2)
2 2

The calculation of harmonics in the output of a three

phase inverter is rather involved. It is best managed on a
computer. Figure 23.3 and Table I shows the relative
harmonic amplitudes of line-line RMS voltages for a
large and odd mf.

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Table I (Source: N. Mohan et al, Power Electronics)

m 0.2 0.4 0.6 0.8 1.0
n
1 0.122 0.245 0.367 0.490 0.612
mf  2 0.010 0.037 0.080 0.135 0.195
mf  4 0.005 0.011
2mf  1 0.116 0.200 0.227 0.192 0.111
2mf  5 0.008 0.020
3mf  2 0.027 0.085 0.124 0.108 0.038
3mf  4 0.007 0.029 0.064 0.096
4mf  1 0.100 0.096 0.005 0.064 0.042
4mf  5 0.021 0.051 0.073
4mf  7 0.010 0.030

Over-modulation, m > 1
If the peak amplitude of the control voltage is greater
than the peak of the carrier waveform, the fundamental
output voltage will increase, eventually becoming 0.78Vd
when m is infinite and the line-line output waveform
becomes a square-wave. Over-modulation is thus a
means of increasing the output voltage range of a SPWM
inverter. When over-modulation is used, more lower-
order and sideband harmonics and their multiples will
exist around mf. However, the dominant harmonics will
not be as large in amplitude as with operation in the
linear range.

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0.78

0.612

Vl  l ,1
Vd

1.0 3.24
m
Figure 23.5
The amplitude of the fundamental can be increased
further by adding a third harmonic to the modulating
waveform as indicated in the figure below. If the
modulating waveform is
1
ec ,A  m  sin o t    m  sin  3o t  (23.3)
6
for m  1.

Figure 23.6
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It can be shown that the fundamental line-line output

voltage can be raised to 1.155 of what is obtained with
only the fundamental frequency modulating waveform.
Although some third harmonic is added to the
modulating waveform, the third harmonic phase currents
in a star connected load will always cancel.

Figure 23.7 PWM switching signal for phase leg A.

+Vd

Vd

Figure 23.8. For m = 1, and 1/6th of third harmonic

injection

Note from figure 23.6 that even with m = 1 and 16.67%

of third harmonic injection in the reference voltages, the
amplitude of the modulating waveform does not exceed
Lecture 23 - Three-phase SPWM inverters 23-9 F. Rahman
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the amplitude of the career. Additional low-order

harmonics that are present in vAB is thus not as much as
they would be if m was increased beyond 1 to increase
the output voltage.

The DC Link current

With a sinusoidal output current which is at a phase
angle  (lagging) with respect to the line-neutral voltage,
the mean DC link current Id is

3 2
Id   I o1 cos  (23.4)


where Io1 is the RMS fundamental phase current of a Y-

connected load.

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Effect of dead time on inverter output waveform

In the forgoing sections on inverter circuits, it has been
assumed that switches in an inverter leg turn ON and
OFF instantly and that their switching signals have
complementary logic. However these switches have
finite turn-on and -off times, the off-times being
generally much longer than turn-on times. If a switch in a
leg turns on ahead of the other switch in the same leg
turning off, a catastrophic short-circuit of the DC source
may occur, because of the very low source impedance of
the DC source. Furthermore, gate drive signals are often
delayed through isolation circuits, with some the
likelihood for overlap of simultaneous conduction (short-
circuit). It is thus necessary to introduce dead-time
between the transition of switching from the top
transistor in a leg to the bottom transistor in the same leg
and vice versa as indicated in figure 23.8.

T1 D1
A ia
Vd

T4 D4

Figure 23.9

To prevent overlap of conduction, dead-time is

interposed into the switching signals as indicated in
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figure 23.8. The dead-time can be of the order of a few

microseconds for fast devices (such as MOSFETs) to a
few tens of microseconds for slower devices. Note that
both devices in an inverter leg are off during the dead-
time. Obviously, the dead-time affects the voltage at the
load terminals of an inverter. Depending on the direction
of load current flow the load terminal is clamped either
to the positive bus or to the negative bus which leads to
clamping of the load voltage to +Vd/2 or –Vd/2.

Consider the single-phase full-bridge inverter of figure

23.7 in which the bipolar switching scheme is employed.
Once dead-time Td is incorporated, the switching signals
T1 and T4 are modified to T1’ and T4’, so that both
switches remain off for Td at transitions. The dead-time
Td is selected according to the worst case requirement for
complete turn-off of a device in a circuit. Compared to
the ideal case of having no dead-time, it can be seen that
if iA > 0 and when T4 is turned off, the delay in turning
switch T1 ON means that the load terminal A continues
to have –Vd/2 due to the diode D4 conducting, instead of
+Vd/2. The shaded voltage pulse of amplitude +Vd and
duration Td is therefore lost from the incoming output
PWM voltage pulse.

Similarly, compared to the ideal case of having no dead-

time, it can be seen that if iA < 0 and when T1 is turned
off, the delay in turning switch T4 means that the load
terminal A continues to have +Vd/2 due to the diode D1
conducting, instead of –Vd/2. The shaded voltage pulse of

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amplitude +Vd and duration Td is therefore gained by the

outgoing output PWM voltage pulse.
v cw
e cA

T1

T4

T1'

T4'

Loss
v AN
+V d /2 Ideal
Actual
 V d /2
iA > 0

Gain
v AN
+V d /2 Actual
Ideal
 V d /2
iA < 0
Td Td Td Td

Figure 23.10

Thus, for ia > 0, the average loss of potential at terminal

A over a PWM switching period Ts is given by
TdVd
VAN   (23.5)
Ts

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Similarly, for ia < 0, the average gain of potential at

terminal A over a PWM switching period Ts is given by
TdVd
VAN  (23.6)
Ts

Note that over each PWM switching period Ts,

transitions of the switches from T1 to T4 or from T4 to
T1 occur once each PWM cycle. Thus, for a single-
phase, half-bridge SPWM inverter, the output voltage
TV
 d d
suffers a voltage drop of Ts when io > 0 and a
TdVd
voltage increase of T when io < 0.
s

For a single-phase full-bridge inverter, note that the

positive current at terminal A (current out of terminal A)
is actually a negative current at terminal B (current into
terminal B). Thus, the average gain of potential at
terminal B over switching period Ts for iA > 0 is
TdVd
VBN  (23.7)
Ts

Similarly, the average loss of potential at terminal B over

switching period Ts for iA < 0 is
TdVd
VBN   (23.8)
Ts

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Since vo = vAN  vBN, the change of output voltage due to

the dead-time Td is
2Td
Vo  VAN  VBN  Vd
for iA > 0. (23.9)
Ts
2Td
= T  Vd for iA < 0. (23.10)
s

The figure 23.11 shows the effect of dead-time on the

fundamental output voltage waveform of a full-bridge
single-phase SPWM inverter. Note that output voltage
level changes at the zero crossings of the load currents
imply that there is now a low order harmonic voltage in
the output which is at twice the output frequency. This
occurs in all inverter circuits.

Figure 23.11

It should be appreciated that the distortion (Vo) in the

output voltage and current due to dead-time is more
significant when Td is comparable to Ts, as it happens
Lecture 23 - Three-phase SPWM inverters 23-15 F. Rahman
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when the switching frequency is high and the dead-time

requirement for the switching devices in the inverter is
also large. With longer turn-off times of slower devices,
this problem is more prevalent. This is another reason
for the trend towards faster switching devices. Figure
23.11 show a few inverter output waveforms for such
cases.

(a) fs = 10 kHz, Td = 1 s

Lecture 23 - Three-phase SPWM inverters 23-16 F. Rahman

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(b) fs = 10 kHz, Td = 10 s

Figure 23.12

Because the fundamental voltage waveform contains two

shifts per cycle, the load voltage and current harmonics
will include second order harmonics.

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Current Source Inverters – Not included for 2010

Single-phase CSI
Current source inverters are supplied from currents
sources. Figure 23.13 shows a circuit in which the DC
link inductor L help render the supply a stiff current
source. If the supply current can not change appreciably
over one complete cycle of the output voltage or current
waveform because of the source inductance, then the
input source can be regarded as a stiff current source. A
sufficiently large inductance L is all that is required. If
the phase-controlled thyristor AC-DC converter (on the
left-hand side) is continuously regulated using firing
angle (a) control to maintain the DC link current to a
desired level, then the required DC link inductance size
can be further reduced. In some cases, the inductance in
the load may be sufficient to achieve the required current
source performance.

Figure 23.13

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The four inverter thyristor switches T1 – T4 are switched

as in a bipolar switched full-bridge inverter to produce an
AC output current waveform as shown in figure 23.14.
The switching scheme is T1T2 – T3T4 – T1T2 and so
on. If the DC link supply current IL is assumed to be
constant the load current waveform can be expressed as

+ Id

T 1T 2

T 3T 4
- Id
 

Figure 23.14
The capacitors C1, C2 and diodes D1 – D4 allow the four
thyristor switches to turn-off in pairs as required. Note
that thyristors can not naturally turn off in this circuit.
Consider a load current cycle in which the switches T1
and T2 are ON, and the load carries the DC link current
Id. Capacitors C1 and C2 are both charged through D3,
D4, and T2 to the load voltage which is positive on the
left-hand terminal. When T3 and T4 are triggered ON at
, capacitors C1 and C2 apply reverse bias to the anode-
cathode terminals of the thyristors. T3 and T4 divert the
currents in T1 and T2 respectively turning them off.
Form this point, capacitors C1 and C2 start to recharge
towards an opposite polarity voltage, ultimately reaching
the amplitude of the negative load voltage. While
capacitors C1 and C2 charge negatively, load current
falls to zero and then rises to the DC link current Id. If
constant Id is assumed, the capacitor and load currents
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must at times add up to Id. Note that diodes D1 – D4 also

prevent discharging of the capacitors into the load.

If the thyristor switches of figure 23.13 are replaced by

gate turn-off devices, the capacitors C1 and C2 can be
eliminated. These devices now allow quasi-square
current output waveforms in the load, allowing output
current control. This is achieved by allowing the DC link
current to be carried entirely by the left or right legs of
the inverter for part of the AC cycle.

The three-phase current source inverter circuit of figure

23.15 operates in same way as described in the above
paragraph. The switching signals (of 180 conduction
angle) for each inverter leg are displaced by 120 from
those of adjacent legs. For a constant DC link current Id,
quasi-square phase currents of amplitude Id and duration
120 () in a Y-connected load occur, as indicated in
figure 23.16.

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Figure 23.15

+ Id

ia
 = 120o
t
 = 120o 60o
 Id

Figure 23.16

Note that with a CSI employing gate turn-off switches,

the quality of the current supply to load can be improved
by using SPWM and modified SPWM.

Lecture 23 - Three-phase SPWM inverters 23-21 F. Rahman