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Sessional DLD

The document provides the details of an exam for the course EEE241 Digital Logic Design including 5 multiple choice questions covering various concepts such as Gray code to excess-3 code conversion, implementing Boolean functions using NAND-AND form, designing decoders, and completing an arithmetic circuit. The exam is worth 70 marks, takes place on April 25th 2018, and has a time limit of 70 minutes.

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Haseeb Arif
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81 views6 pages

Sessional DLD

The document provides the details of an exam for the course EEE241 Digital Logic Design including 5 multiple choice questions covering various concepts such as Gray code to excess-3 code conversion, implementing Boolean functions using NAND-AND form, designing decoders, and completing an arithmetic circuit. The exam is worth 70 marks, takes place on April 25th 2018, and has a time limit of 70 minutes.

Uploaded by

Haseeb Arif
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

COMSATS INSTITUTE INFORNATION TECHNOLOGY (CIIT)

Islamabad Campus
Department of Electrical Engineering
Sessional Exam II
Spring 2018
EEE241: Digital Logic Design
BEE 2(D)
Marks: 70 Time: 70 minutes
Date: 25th April, 2018 Instructor: Riaz Hussain
T.A.: Ms. Asma Ramay
• Only registered students are allowed to take the exam
• Mobile phones are not allowed
• Closed book, closed notes
• No marks without proper procedure and explanation

Q1. [CLO4] (15 marks)


Design a “Gray Code” to “8 4 –2 –1” code converter. For an input for which there is no corresponding
output “8 4 –2 –1” code the circuit should indicate invalid code.
Solution:

Min Input Number Output


Term
Gray Code 8 4 –2 –1 Code Invalid Code
A B C D w x y z wxyz
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 0 1 1 1
2 0 0 1 0 3 0 1 0 1
3 0 0 1 1 2 0 1 1 0
4 0 1 0 0 7 1 0 0 1
5 0 1 0 1 6 1 0 1 0
6 0 1 1 0 4 0 1 0 0
7 0 1 1 1 5 1 0 1 1
8 1 0 0 0 15 X X X X 0001
9 1 0 0 1 14 X X X X 0001
10 1 0 1 0 12 X X X X 0001
11 1 0 1 1 13 X X X X 0001
12 1 1 0 0 8 1 0 0 0
13 1 1 0 1 9 1 1 1 1
14 1 1 1 0 11 X X X X 0001
15 1 1 1 1 10 X X X X 0001

Since, there are few input Gray codes (corresponding 10, 11, 12, 13, 14, 15) that have no representation in
the “8 4 –2 –1” code our circuit must indicate this. To handle this situation, we pick a code that is not used
for output “8 4 –2 –1” code (i.e. 0001, 0010, 0011, 1100, 1101, 1110). In this case we pick (0000), i.e.
when wxyz all are low the error is indicated.

Page 1 of 6 EEE241DLD BEE-2D Spring2018 Sessional-2 Dr. Riaz Hussain


w:
AB \ CD
00 01 11 10
00 0 0 0 0
01 1 1 1 0
11 1 1 0 0
10 0 0 0 0

𝑤𝑤 = 𝐵𝐵𝐵𝐵′ + 𝐴𝐴′𝐵𝐵𝐷𝐷

x:
AB \ CD
00 01 11 10
00 0 1 1 1
01 0 0 0 1
11 0 1 0 0
10 0 0 0 0

𝑥𝑥 = 𝐴𝐴′𝐵𝐵′𝐷𝐷 + 𝐴𝐴′𝐶𝐶𝐷𝐷′ + 𝐴𝐴𝐵𝐵𝐵𝐵′𝐷𝐷


y:
AB \ CD
00 01 11 10
00 0 1 1 0
01 0 1 1 0
11 0 1 0 0
10 0 0 0 0

𝑦𝑦 = 𝐴𝐴′𝐷𝐷 + 𝐵𝐵𝐶𝐶′𝐷𝐷
z:
AB \ CD
00 01 11 10
00 0 1 0 1
01 1 0 1 0
11 0 1 1 1
10 1 1 1 1

𝑧𝑧 = 𝐴𝐴𝐵𝐵 ′ + 𝐴𝐴𝐷𝐷 + 𝐴𝐴𝐴𝐴 + 𝐵𝐵 ′ 𝐶𝐶 ′ 𝐷𝐷 + 𝐵𝐵𝐶𝐶𝐶𝐶 + 𝐵𝐵′𝐶𝐶𝐷𝐷′ + 𝐴𝐴′𝐵𝐵𝐵𝐵′𝐷𝐷′


err:
𝑒𝑒𝑒𝑒𝑒𝑒 = 𝐴𝐴′𝐵𝐵′𝐶𝐶′𝐷𝐷

Q2. [CLO3] (10 marks)


Implement the following Boolean function F, together with the don’t-care conditions d, using two-level
NAND-AND form of logic.
𝑭𝑭(𝑨𝑨, 𝑩𝑩, 𝑪𝑪, 𝑫𝑫) = � 𝟐𝟐, 𝟒𝟒, 𝟏𝟏𝟏𝟏, 𝟏𝟏𝟏𝟏, 𝟏𝟏𝟏𝟏

𝒅𝒅(𝑨𝑨, 𝑩𝑩, 𝑪𝑪, 𝑫𝑫) = � 𝟎𝟎, 𝟏𝟏, 𝟓𝟓, 𝟖𝟖

Solution:
00 01 11 10
00 X X 0 1
01 1 X 0 0

Page 2 of 6 EEE241DLD BEE-2D Spring2018 Sessional-2 Dr. Riaz Hussain


11 1 0 0 1
10 X 0 0 1

𝐹𝐹 = 𝐶𝐶′𝐷𝐷′ + 𝐴𝐴𝐴𝐴′ + 𝐵𝐵′𝐷𝐷′

00 01 11 10
00 X X 0 1
01 1 X 0 0
11 1 0 0 1
10 X 0 0 1

𝐹𝐹 ′ = 𝐷𝐷 + 𝐴𝐴′𝐵𝐵𝐵𝐵
𝐹𝐹 = (𝐷𝐷)′(𝐴𝐴′𝐵𝐵𝐵𝐵)′
NAND-AND

Q3. [CLO2] (10 marks)


Draw the truth table, logic diagram and symbol of a 3-to-8-line active low decoder.
Solution:
I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 1 1 1 1 1 1 1 0

0 0 1 1 1 1 1 1 1 0 1

0 1 0 1 1 1 1 1 0 1 1

0 1 1 1 1 1 1 0 1 1 1

1 0 0 1 1 1 0 1 1 1 1

1 0 1 1 1 0 1 1 1 1 1

1 1 0 1 0 1 1 1 1 1 1

1 1 1 0 1 1 1 1 1 1 1

Page 3 of 6 EEE241DLD BEE-2D Spring2018 Sessional-2 Dr. Riaz Hussain


Q4. [CLO3] (15 marks)
Implement the following Boolean function F, together with the don’t-care conditions d, using
i) 4x1 Mux (you can use external gates) [10]
ii) Two 3-to-8 line decoders with enable control [05]
𝑭𝑭(𝑨𝑨, 𝑩𝑩, 𝑪𝑪, 𝑫𝑫) = �(𝟏𝟏, 𝟐𝟐, 𝟑𝟑, 𝟓𝟓, 𝟔𝟔, 𝟕𝟕, 𝟏𝟏𝟏𝟏, 𝟏𝟏𝟏𝟏)
Solution:
i)
A B C D F
0 0 0 0 1
0 0 0 1 0 C’D’
I0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
C’D’ I1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 I2
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
D’ I3
1 1 1 0 1
1 1 1 1 0
S1 S0
ii.

Page 4 of 6 EEE241DLD BEE-2D Spring2018 Sessional-2 Dr. Riaz Hussain


Q5 [CLO4] (10 Marks)
The shown circuit was designed to perform the arithmetic operation S = X – 2 Y + 3. X and Y are 3-bit
operands, i.e. X = X2 X1 X0 and Y = Y2 Y1 Y0. Complete the design by connecting all 20 input lines, some of
them to X and Y, and the rest to 0 or 1. Note: You must not leave any input line without a connection.

Solution:

Page 5 of 6 EEE241DLD BEE-2D Spring2018 Sessional-2 Dr. Riaz Hussain


Q6. [CLO3] (10 marks)
Show the timing diagram for SR latch when Q = 0, Q’ = 0 and you apply SR = 10.

******************** GOOD LUCK ********************

Page 6 of 6 EEE241DLD BEE-2D Spring2018 Sessional-2 Dr. Riaz Hussain

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