UNIT – 5

Design Examples (using VHDL) & Sequential Logic Design

DESIGN EXAMPLES USING VHDL:
SEQUENTIAL LOGIC DESIGN
VHDL code for gated D Latch:
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity Dlatch is
Port(D,C: in std_logic;
Q: out std_logic);
End Dlatch;
Architecture behaviour of Dlatch is
Begin
process(D,C)
Begin
If (C=‘1’) then Q<=D;
end if;
QN <= NOT Q;
end process;
End behaviour;
VHDL code for gated D Flip-Flop using IF statement:
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity DFF is
Port(D,Clock: in std_logic;
Q: out std_logic);
End DFF;
Architecture behaviour of DFF is
Begin
process(Clock)
Begin
If (Clock’EVENT and clock=‘1’) then Q<=D;
end if;
end process; End behaviour;
VHDL code for Rising Edge D Flip Flop: architecture Behavioral of
Library IEEE; RisingEdge_DFlipFlop is
USE IEEE.Std_logic_1164.all; begin
process(Clk)
entity RisingEdge_DFlipFlop is begin
port( if(rising_edge(Clk)) then
Q : out std_logic; Q <= D;
Clk :in std_logic; end if;
D :in std_logic end process;
); end Behavioral;
end RisingEdge_DFlipFlop;
 T Flipflop truth table
VHDL Code for T FlipFlop
process (Clock)
library IEEE; begin
use IEEE.STD_LOGIC_1164.ALL; if Clock'event and Clock='1' then
entity T_FF is if T='0' then
port( T: in std_logic; tmp <=
Clock: in std_logic; tmp;
Q: out std_logic); elsif T='1' then
end T_FF; tmp <= not (tmp);
end if;
architecture Behavioral of T_FF is end if;
signal tmp: std_logic; end process;
begin Q <= tmp;
end Behavioral;
SR FlipFlop:
A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These
flip-flops are shown in Figure. Each flip-flop has two outputs, Q and Q’, and two inputs, set
and reset. This type of flip-flop is referred to as an SR flip-flop.

SR Flipflop truth table

VHDL Code for SR FlipFlop: if(CLOCK='1' and CLOCK'EVENT) then

library ieee; if(S='0' and R='0')then
use ieee. std_logic_1164.all; tmp:=tmp;
use ieee. std_logic_arith.all; elsif(S='1' and R='1')then
use ieee. std_logic_unsigned.all; tmp:='Z';
entity SR_FF is elsif(S='0' and R='1')then
PORT( S,R,CLOCK: in std_logic; tmp:='0';
Q, QBAR: out std_logic); else
end SR_FF; tmp:='1';
end if;
Architecture behavioral of SR_FF is end if;
begin Q <= tmp;
PROCESS(CLOCK) QBAR <= not tmp;
variable tmp: std_logic; end PROCESS;
begin end behavioral;

JK FlipFlop:
 entity JK_FF is
PORT( J,K,CLOCK: in std_logic;
Q, QB: out std_logic);
end JK_FF;

Architecture behavioral of JK_FF is

begin
JK Flipflop truth table PROCESS(CLOCK)
variable TMP: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(J='0' and K='0')then
TMP:=TMP;
elsif(J='1' and K='1')then
TMP:= not TMP;
elsif(J='0' and K='1')then
TMP:='0';
else
TMP:='1';
end if;
end if;
VHDL Code for JK FlipFlop
Q<=TMP;
library ieee;
Q <=not TMP;
use ieee. std_logic_1164.all;
end PROCESS;
use ieee. std_logic_arith.all;
end behavioral;
use ieee. std_logic_unsigned.all;

VHDL code for Rising Edge D Flip-Flop with );

Synchronous Reset: end RisingEdge_DFlipFlop_SyncReset;
Library IEEE; architecture Behavioral of
USE IEEE.Std_logic_1164.all; RisingEdge_DFlipFlop_SyncReset is
entity RisingEdge_DFlipFlop_SyncReset is begin
port( process(Clk)
Q : out std_logic; begin
Clk :in std_logic; if(rising_edge(Clk)) then
sync_reset: in std_logic; if(sync_reset='1') then
D :in std_logic Q <= '0';
 else end if;
Q <= D; end process;
end if; end Behavioral;

VHDL code for Rising Edge D Flip-Flop with Asynchronous Reset High Level:
Library IEEE; architecture Behavioral of
USE IEEE.Std_logic_1164.all; RisingEdge_DFlipFlop_AsyncResetHigh is
entity begin
RisingEdge_DFlipFlop_AsyncResetHigh is process(Clk,sync_reset)
port( begin
Q : out std_logic; if(sync_reset='1') then
Clk :in std_logic; Q <= '0';
sync_reset: in std_logic; elsif(rising_edge(Clk)) then
D :in std_logic Q <= D;
); end if;
end end process;
RisingEdge_DFlipFlop_AsyncResetHigh; end Behavioral;

VHDL code for Rising Edge D Flip-Flop with Asynchronous Reset Low Level:
Library IEEE; architecture Behavioral of
USE IEEE.Std_logic_1164.all; RisingEdge_DFlipFlop_AsyncResetLow is
entity begin
RisingEdge_DFlipFlop_AsyncResetLow is process(Clk,sync_reset)
port( begin
Q : out std_logic; if(sync_reset='0') then
Clk :in std_logic; Q <= '0';
sync_reset: in std_logic; elsif(rising_edge(Clk)) then
D :in std_logic); Q <= D;
end end if;
RisingEdge_DFlipFlop_AsyncResetLow; end process;
end Behavioral;

VHDL code for Falling Edge D Flip Flop:

Library IEEE; architecture Behavioral of

USE IEEE.Std_logic_1164.all; FallingEdge_DFlipFlop is
entity FallingEdge_DFlipFlop is begin
port( process(Clk)
Q : out std_logic; begin
Clk :in std_logic; if(falling_edge(Clk)) then
D :in std_logic); Q <= D;
end FallingEdge_DFlipFlop; end if; end process;
end Behavioral;
VHDL code for Falling Edge D Flip-Flop with Synchronous Reset:
Library IEEE; process(Clk)
USE IEEE.Std_logic_1164.all; begin
entity FallingEdge_DFlipFlop_SyncReset is if(falling_edge(Clk)) then
port( if(sync_reset='1') then
Q : out std_logic; Q <= '0';
Clk,D :in std_logic; else
sync_reset: in std_logic); Q <= D;
end FallingEdge_DFlipFlop_SyncReset; end if;
architecture Behavioral of end if;
FallingEdge_DFlipFlop_SyncReset is end process;
begin end Behavioral;

VHDL code for Falling Edge D Flip-Flop with Asynchronous Reset High Level:
Library IEEE; begin
USE IEEE.Std_logic_1164.all; process(Clk,sync_reset)
entity begin
FallingEdge_DFlipFlop_AsyncResetHigh is if(sync_reset='1') then
port( Q : out std_logic; Q <= '0';
Clk,D :in std_logic; elsif(falling_edge(Clk)) then
sync_reset: in std_logic); Q <= D;
end end if;
FallingEdge_DFlipFlop_AsyncResetHigh; end process;
architecture Behavioral of end Behavioral;
FallingEdge_DFlipFlop_AsyncResetHigh is

VHDL code for Falling Edge D Flip-Flop with Asynchronous Reset Low Level:
Library IEEE; architecture Behavioral of
USE IEEE.Std_logic_1164.all; FallingEdge_DFlipFlop_AsyncResetLow is
entity begin
FallingEdge_DFlipFlop_AsyncResetLow is process(Clk,sync_reset)
port( begin
Q : out std_logic; if(sync_reset='0') then
Clk :in std_logic; Q <= '0';
sync_reset: in std_logic; elsif(falling_edge(Clk)) then
D :in std_logic); Q <= D;
end end if;
FallingEdge_DFlipFlop_AsyncResetLow; end process;
end Behavioral;
Applications of flipflops:
1. Used as a memory element
2. Used to eliminate key debounce
3. Used as a delay element
Counters in VHDL:
VHDL code for a 4-bit Up-Counter:
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity upcounter is
Port(clock, resetn,EN : in std_logic;
Q : out std_logic_vector (3 downto 0));
End upcounter;
Architecture behaviour of upcounter is
Signal Count : std_logic_vector (3 downto 0);
Begin
Process (clock, resetn)
Begin
If resent = ‘0’ then count <= “0000”;
Elsif (clock’event and clock = ‘1’) then
If EN = ‘1’ then count <= count+1;
Else
count <= count;
end if;
end if;
end process;
Q<= count;
End behaviour;