1. An NMOS device is plugged into the test configuration shown below in Fig 3.

The input Vin

=2V. The current source draws a constant current of 50 μA. R is a variable resistor that can
assume values between 10 kΩ and 30 kΩ. Transistor M1 experiences short channel effects and
has following transistor parameters: k’ = 110*10-6 V/A2, VT = 0.4, and VDSAT = 0.6V. The
transistor has a W/L = 2.5μ/0.25μ. For simplicity body effect and channel length modulation
can be neglected. i.e λ=0, γ=0. [18 pts]

Fig. 3

a) When R =10kΩ find the operation region, VD and VS. [6 pts]

b) When R= 30kΩ again determine the operation region VD, VS. [6 pts]
c) For the case of R = 10kΩ, would VS increase or decrease if λ ≠ 0. Explain qualitatively. [6
pts]

a) When R=10k, VD=VDD-IR, so VD=2V, assume the device is in saturation (needs to be

verified eventually.).
𝑘′ 𝑊
𝐼𝐷 = (𝑉 − 𝑉𝑡 )2 = 50μA
2 𝐿 𝐺𝑆
So VGS-VT=0.3v, VGS=0.7v, Vs=1.3v.
𝑉𝑚𝑖𝑛 = min(𝑉𝐺𝑆 − 𝑉𝑇 , 𝑉𝐷𝑆𝐴𝑇 , 𝑉𝐷𝑆 ) = min(0.3,0.6,0.7) = 𝑉𝐺𝑆 − 𝑉𝑇
So saturation verified.
b) VD=2.5v-1.5v=1v, assume linear region.
𝑊 2
𝐼𝐷 = 𝑘 ′ ((𝑉𝐺𝑆 − 𝑉𝑡 )𝑉𝐷𝑆 − 𝑉𝐷𝑆 ) = 50μA
𝐿
So Vs=0.93v.
𝑉𝑚𝑖𝑛 = min(𝑉𝐺𝑆 − 𝑉𝑇 , 𝑉𝐷𝑆𝐴𝑇 , 𝑉𝐷𝑆 ) = 𝑉𝐷𝑆
So linear verified.
c) Increase. VD is fixed. (1+λ𝑉𝐷𝑆 ) term would try to increase the current more than available
50μA. Thus, VGS needs to reduce by increasing Vs
2. Figure 2 shows NMOS and PMOS devices with drains, sources, and gate ports annotated.
Determine the mode of operation (saturation, linear, or cutoff) and drain current ID for each of
the biasing configurations given below.
2 −1
Use the following transistor data: NMOS: k'n = 115μA/ V , VT0 = 0.43 V, λ = 0.06 V ,

2 −1
PMOS: k'p = 30 μA/ V VT0 = –0.4 V, λ = -0.1 V . Assume (W/L) = 1. [12 pts]
a) NMOS: VGS = 2.5 V, VDS = 2.5 V. PMOS: VGS = –0.5 V, VDS = –1.25 V. [4 pts]
b) NMOS: VGS = 3.3 V, VDS = 2.2 V. PMOS: VGS = –2.5 V, VDS = –1.8 V. [4 pts]
c) NMOS: VGS = 0.6 V, VDS = 0.1 V. PMOS: VGS = –2.5 V, VDS = –0.7 V. [4 pts]
Hint: Refer to Jan M. Rabaey’s book, chapter 3.

(a) NMOS:

VGS = 2.5V ,VDS = 2.5V ,VGS  VT 0 ,VGS − VT 0  VDS , saturation

k 'n W
ID = (VGS − VT 0 ) 2 (1 + VDS）
2 L
115 10−6
= 1 (2.5 − 0.43) 2 (1 + 0.06  2.5)=2.833 10-4 A
2
= 283.3 A

PMOS: VGS = −0.5V , VDS = −1.25V , VGS  VT 0 , VGS − VT 0  VDS saturation

k 'p W
ID = (VGS − VT 0 ) 2 (1 + VDS）
2 L
30
= 1（0.- 5-（0.
- 4））
（1
2
+（0.  -1.25））
- 1）（
2
=0.169 A

(b): NMOS: VGS = 3.3V ,VDS = 2.2V ,VGS  VT 0 ,VGS − VT 0  VDS ，linear

W 1
I D = k 'n 【(VGS − VT 0 )VDS - VDS 2）】
L 2
1
=115  1【（3.3-0.43） 2.2-  2.22】=447.81 A
2
PMOS: VGS = −2.5V , VDS = −1.8V , VGS  VT 0 , VGS − VT 0  VDS ，linear

W 1
I D = k 'p 【(VGS − VT 0 )VDS - VDS 2）】
L 2
1
=30  1【（2. - 5+0.4）（1.  - 8）- （1.- 8）2】=64.8 A
2

(c):NMOS: VGS = 0.6V ,VDS = 0.1V ,VGS  VT 0 ,VGS − VT 0  VDS ，linear

W 1
I D = k 'n 【(VGS − VT 0 )VDS - VDS 2）】
L 2
1
=115  1【（0.6-0.43） 0.1-  0.12】=1.38 A
2

PMOS: VGS = −2.5V , VDS = −0.7V , VGS  VT 0 ,VGS − VT 0  VDS ，linear

W 1
I D = k 'p 【(VGS − VT 0 )VDS - VDS 2）】
L 2
1
=30  1【（2. - 5+0.4）（0.  - 7）- （-0.7）2】=36.75 A
2
3. For the short-channel device shown in Figure 4, given that Vdd =2.5V, Vt0=0.4V,γ=0.1V0.5,
velocity saturation voltage VDSAT =1V, |2F| =0.6V. [15 pts]
a) Determine the different modes of the device while Vo is changed from 0 to Vdd. [7 pts]
b) Derive the condition for Vo at the boundary of each operation mode and give the
corresponding value of Vo. [8 pts]
Hint: Threshold voltage Vt= Vt0+γ(√2F + 𝑉𝑆𝐵 − √2F )

Vdd

Vo

Figure 4. The short-channel device.

Solution:
When 0<Vo<1.1V, velocity saturation mode
When 1.1V<Vo< 2V, saturation mode
When 2V <Vo< 2.5V, off
From velocity saturation mode to saturation mode, Vo ≈ 1.1V
Vgs-Vt = VDSAT , hence, 2.5-0.4-γ(√2F + 𝑉𝑜 − √2F)- 𝑉𝑜 =1V
From saturation mode to off, Vo ≈ 2V
𝑉𝑜 = Vg-Vt, hence, 2.5-0.4-γ(√2F + 𝑉𝑜 − √2F)= 𝑉𝑜
4. Given the data in Table 1 for a short channel NMOS transistor with VDSAT = 0.6 V and k′=100
μA/V2, calculate VT0, γ, λ, 2|φf|, and W/L. [10 pts]
Hint: Refer to Jan M. Rabaey’s book, chapter 3.

for a short channel NMOS transistor：

2
W Vmin
ID = k '
(VGT Vmin − ) +VDS）,
（1
L 2
when，V min = min(VGT , VDS , VDSAT ), VGT = VGS − VT
First，the operation region should be determined。

Supposed that these were to be in saturation， VT should be： VGT = VGS − VT  VDSAT

VGT = VGS − VT  VDSAT

 2 − VT  0.6  VT  1.4 ，this assumption is not reasonable.

We can assume that all data are taken in velocity saturation，then check this assumption。
In velocity saturation：
2
W VDSAT
ID = k '
((VGS − VT )VDSAT − ) +VDS）
（1
L 2
Group 1 and 2：
W 0.62
ID = k' [(2.5 − VT 0 )  0.6 − ](1 +   1.8) = 1812
L 2
W 0.62
I D = k ' [(2 − VT 0 )  0.6 − ](1 +   1.8) = 1297
L 2
0.62
(2.5 − VT 0 )  0.6 −
1812 2  V =0.44V
= T0
1297 0.62
(2 − VT 0 )  0.6 −
2
VT 0  1.4V , so 1,2,3 are in velocity saturation.
Group 2 and 3：
1297 1+ 1.8
=   =0.08V −1
1361 1+  2.5
W
Then we can get： = 15
L
0.62
(2 − 0.44)  0.6 −
1297 2  V = 0.587V
Group 2 and 4： = T
1146 0.62
(2 − VT )  0.6 −
2
0.62
(2 − 0.44)  0.6 −
1297 2  V = 0.692V
Group 2 and 5： = T
1039 0.62
(2 − VT )  0.6 −
2
All of the values satisfy ： VT 0  1.4V ，so the data in the table were taken in velocity saturation.

VT = VT 0 +  ( −2F + VSB − −2F )

sin ce：VT = 0.587V，VT = 0.692V，VT 0 = 0.44V，
 2F =0.6V, = 0.3V 1/2
5. Use the following table for the purpose of capacitance calculation.
Parameter Cox Co
[fF/m2] [fF/m]
NMOS 15 0.27
PMOS 14 0.25

Assume |VT| = 0.2 V for both NMOS and PMOS, and treat velocity saturation as saturation. [15
pts]

a) What is the tox of the NMOS transistor? [5 pts]

b) Consider a PMOS biased with VG = VD = VS = VB = 0 V. Assume W = 480 nm, L = 120 nm,

LD = LS = 240 nm. Calculate the Gate-to-Channel capacitance (CGC) and Gate-to-Source
capacitance (CGS). [5 pts]

c) Consider a NMOS biased with VG = VD = 0.8 V, VS = VB = 0 V. Assume W = 240 nm, L =

120 nm, LD = LS = 240 nm. Calculate the Gate-to-Channel capacitance (CGC) and Gate-to-
Source capacitance (CGS). [5 pts]

a)

b)

c)
6. The circuit of Figure 4 is known as a source-follower configuration. It achieves a DC level
shift between the input and output. The value of this shift is determined by the current I0.
Assume γ = 0.4, 2|φf| = 0.6 V, VT0 = 0.43 V, k′= 115 μA/V2, and λ= 0. The NMOS device has
W/L = 5.4μ/1.2μ such that the short channel effects are not observed. [15 pts]
a) Derive an expression of Vi as a function of Vo and VT(Vo). If we neglect body effect,
what is the nominal value of the level shift performed by this circuit? [5 pts]
b) The NMOS transistor experiences a shift in VT due to the body effect. Find VT as a
function of Vo for Vo ranging from 0 to 1.5V with 0.25 V intervals. Plot VT vs. Vo. [5
pts]
c) Plot Vo vs. Vi as Vo varies from 0 to 1.5 V with 0.25 V intervals. Plot two curves: one
neglecting the body effect and one accounting for it. How does the body effect influence
the operation of the level converter? At Vo (body effect) = 1.5 V, find Vo (ideal) and,
thus, determine the maximum error introduced by body effect. [5 pts]

A:
a):
kn' W
ID = (Vi − VO − VT ) 2
2 L
2I D , neglecting body effect， VT =VT 0 ，
=Vi − VO − VT
'W
kn
L

2I D
Vi = +VT 0 + VO
'W
kn
L
the nominal value of the level shift is:

2I D 2  35 A
+VT 0 = + 0.43 = 0.7978V
'W 2 5.4
kn 115 A / V
L 1.2
b)
 VT = VT 0 +  ( （- 2）F + VO − 2F )
=0.43+0.4（ VO + 0.6- 0.6）

Matlab command：

>> Vo=0:0.25:1.5;
>> Vt=0.43+0.4*((Vo-0.6).^0.5-0.6.^0.5);
>> plot(Vo,Vt);grid on

c)

2I D
VO =Vi - -VT ,body effect will increase the VT , so the VO will be decreased.
'W
kn
L

When VO (body effect) = 1.5V, VT =0.6998V, Vi =2.5676V,

Neglect the body effect ， VO （ideal）=2.2978V,

the maximum error introduced by body effect is：0.2698V.

matlab command
>> Vo=0:0.25:1.5;
>> Vi1=0.43+0.4*((Vo+0.6).^0.5-0.6.^0.5)+0.3678+Vo;
>> Vi2=Vo+0.7978;
>> hold on
>> plot(Vo,Vi1);grid on
>> hold on
>> plot(Vo,Vi2);grid on
7. Consider the following NMOS inverter. Assume that the bulk terminals of all
NMOS device are connected to GND. Assume that the input IN has a 0V to 2.5V
swing and there is no leakage current. VT0=0.43, ΦF=0.3. [24 pts]

Fig. 5

a) Set up the equation(s) to compute the voltage on node x. Assume the body effect

coefficient γ=0.5 [√𝑉]. [5 pts]

b) What are the modes of operation of device M2? Assume γ=0. [5 pts]
c) What is the value on the output node OUT for the case when IN =0V? Assume
γ=0. [5 pts]
d) Assuming devices are in velocity saturation region, VDSAT = 0.63V and γ=0,
derive an expression for the switching threshold (VM) of the inverter. Recall that
the switching threshold is the point where VIN= VOUT. Assume that the device
sizes for M1, M2 and M3 are (W/L)1, (W/L)2, and (W/L)3 respectively. What are
the limits on the switching threshold? For this, consider two cases:
i) (W/L)1 >> (W/L)2 [7 pts]
ii) (W/L)2 >> (W/L)1 [5 pts]
8. Short Channel MOS [7 pts]

In a long channel technology (without velocity saturation), assume a 2-stack with

NMOS widths of 2W has the same current as a single NMOS with a width of W (i.e.,
I1 = I2). In a short channel technology with velocity saturation, which of the following
is true?
a) I1 > I2
b) I1 < I2
Explain your answer.
Hint: Current of a velocity saturated device does not decrease as much as a long channel
device when Vds is reduced. Load line analysis can be helpful in figuring out the stack
current.
A: