Aec Q101-002a
Aec Q101-002a
Aec Q101-002a
ATTACHMENT 2
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Components Technical Committee.
AEC - Q101-002 - REV-A
July 18, 2005
METHOD - 002
DISCRETE COMPONENT
MACHINE MODEL (MM)
ELECTROSTATIC DISCHARGE (ESD) TEST
1. SCOPE
1.1 Description:
The purpose of this specification is to establish a reliable and repeatable procedure for
determining the MM ESD sensitivity for discrete components.
A condition in which a component does not meet all the requirements of the acceptance criteria,
as specified in section 5, following the ESD test.
An instrument that simulates the machine model ESD pulse as defined in this specification.
An ESD pulse meeting the waveform criteria specified in this test method, approximating an ESD
pulse from a machine or mechanical equipment.
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The time (tpm) measured between first and third zero crossing points.
The maximum ESD voltage at which, and below, the component is determined to pass the failure
criteria requirements specified in section 4.
1.3.9 PUT:
WCP is the pin and/or terminal pair representing the worst case waveform that is within the limits
and closest to the minimum or maximum parameter values as specified in Table 1. The WCP
shall be identified for each socket. It is permissible to use the worst case pin and/or terminal pair
that has been previously identified by the Discrete Component HBM ESD method (AEC - Q101-
001) when performing the Simulator Waveform Verification as defined in section 2.4.
2. EQUIPMENT:
The apparatus for this test consists of an ESD pulse simulator and DUT socket. Figure 1
shows a typical equivalent MM ESD circuit. Other equivalent circuits may be used, but the
actual simulator must be capable of supplying pulses which meet the waveform requirements
of Table 1, Figure 2, and Figure 3.
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S1
Terminal A
High Voltage
500 Ω
short
S2 DUT
R2
Pulse C1 200 pF socket
Generator R1
10k to 10M
ohm
Terminal B
Notes:
1. Figure 1 is shown for guidance only; it does not attempt to represent all associated circuit
components, parasitics, etc..
2. The performance of any simulator is influenced by its parasitic capacitance and
inductance.
3. Precautions must be taken in simulator design to avoid recharge transients and multiple
pulses.
4. R2, used for Equipment Qualification as specified in section 2.3, shall be a low
inductance, 1000 Volt, 500 ohm resistor with ±1% tolerance.
5. Piggybacking of DUT sockets (the insertion of secondary sockets into the main DUT
socket) is allowed only if the combined piggyback set (main DUT socket with the
secondary DUT socket inserted) waveform meets the requirements of Table 1, Figure 2,
and Figure 3.
6. Reversal of terminals A and B to achieve dual polarity is not permitted
7. S2 should be closed 10 to 100 milliseconds after the pulse delivery period to ensure the
DUT socket is not left in a charged state. S2 should be opened at least 10 milliseconds
prior to the delivery of the next pulse.
Equipment shall include an oscilloscope and current probe to verify conformance of the simulator
output pulse to the requirements of this document as specified in Table 1, Figure 2, and Figure 3.
The current probe shall have a minimum bandwidth of 350 Mhz and maximum cable length of 1
meter (Tektronix CT-1, CT-2, or equivalent). A CT-2 probe or equivalent should be used with
voltages greater than 800 volts.
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The two evaluation loads shall be: 1) a low inductance, 1000 volt, 500 ohm sputtered film resistor
with + 1% tolerance, and 2) an 18 AWG tinned copper shorting wire. The lead length of both the
shorting wire and the 500 ohm resistor shall be as short as possible and shall span the maximum
distance between the worst case pin and/or terminal pair (WCP) while passing through the
current probe as defined in section 2.2.1.
2.2.3 Oscilloscope:
The oscilloscope and amplifier combination shall have a minimum bandwidth of 350 Mhz, a
minimum sensitivity of 100 milliamperes per large division and a minimum visual writing speed of
4 cm per nanosecond.
Equipment qualification must be performed during initial acceptance testing or after repairs are
made to the equipment that may affect the waveform. The simulator must meet the requirements
of Table 1 and Figure 2 for five (5) consecutive waveforms at all voltage levels using the worst
case pin and/or terminal pair (WCP) on the highest pin count, positive clamp test socket DUT
board with the shorting wire per Figure 1. The simulator must also meet the requirements of
Table 1 and Figure 3 for five (5) consecutive waveforms at the 400 volt level using the worst case
pin and/or terminal pair (WCP) on the highest pin count, positive clamp test socket DUT board
with the 500 ohm load per Figure 1. Thereafter, the test equipment shall be periodically qualified
as described above; a period of one (1) year is the maximum permissible time between full
qualification tests.
The performance of the simulator can be dramatically degraded by parasitics in the discharge
path. Therefore, to ensure proper simulation and repeatable ESD results, it is recommended that
waveform performance be verified on the worst case pin and/or terminal pair (WCP) using only
the shorting wire per section 2.4.1. The worst case pin and/or terminal pair (WCP) for each
socket and DUT board shall be identified and documented. The waveform verification shall be
performed when a socket/mother board is changed or on a weekly basis (if the equipment is used
for at least 20 hours). If at any time the waveforms do not meet the requirements of Table 1 and
Figure 2 at the 400 volt level, the testing shall be halted until waveforms are in compliance.
a. With the required DUT socket installed and with no component in the socket, attach a
shorting wire in the DUT socket such that the worst case pin and/or terminal pair (WCP)
is connected between terminal A and terminal B as shown in Figure 1. Place the current
probe around the shorting wire.
b. Set the horizontal time scale of the oscilloscope at 20 nanoseconds per division or
greater.
c. Initiate a positive pulse at the 400 volt level per Table 1. The simulator shall generate
only one (1) waveform per pulse applied.
d. Measure and record the first peak current, second peak current, and major pulse period.
All parameters must meet the limits specified in Table 1 and Figure 2.
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e. Initiate a negative pulse at the 400 volt level per Table 1. The simulator shall generate
only one (1) waveform per pulse applied.
f. Measure and record the first peak current, second peak current, and major pulse period.
All parameters must meet the limits specified in Table 1 and Figure 2.
* The 500 ohm load is used only during Equipment Qualification as specified in section 2.3.
If using automated ESD test equipment, the system diagnostics test shall be performed on all
high voltage relays per the equipment manufacturer's instructions. This test normally measures
continuity and will identify any open or shorted relays in the test equipment. Relay verification
must be performed during initial equipment qualification and on a weekly basis. If the diagnostics
test detects relays as failing, all sockets boards using those failed relays shall not be used until
the failing relays have been replaced. The test equipment shall be repaired and requalified per
section 2.3.
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8.0
Ips1
4.0
Current in Amperes
2.0
0.0
-2.0
-4.0
Ips2
-6.0
tpm
-8.0
-20 0.0 20 40 60 80 100 120 140
Time in nanoseconds
1.2
Ipr
1.0
Current in Amperes
0.8
0.6
I100
0.4
0.2
0.0
-20 0.0 20 40 60 80 100 120 140 160 180
Time in nanoseconds
Figure 3: MM Current Waveform through a 500 Ohm Resistor *, 400 volt discharge
* The 500 ohm load is used only during Equipment Qualification as specified in section 2.3.
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3. TEST PROCEDURE:
Each sample group shall be composed of ten (10) components per stress voltage level (for a total
sample size of 30 components as specified in Table 1 of AEC - Q101). Each sample group shall
be stressed at one (1) stress voltage level, following the test flow diagram of Figure 4, using all
pin and/or terminal combinations specified in section 3.2. Each stress voltage level requires a
new sample group of ten (10) components.
Each pair of pins and/or terminals and all combinations of pin and/or terminal pairs for each
component shall be subjected to three (3) pulses at each stress voltage polarity following the
ESD levels stated in Figure 4. Any pin and/or terminal not under test shall be in an electrically
open (floating) state.
3.4 Measurements:
Prior to ESD testing, complete parametric testing (initial electrical verification) shall be performed
on all sample groups and all components in each sample group per applicable user device
specification at room temperature followed by hot temperature, unless specified otherwise in the
user device specification. A data log of each component shall be made listing all parameter
measurements as defined in Table 2. The data log will be compared to the parameters
measured during final electrical verification testing to determine the failure criteria of section 4.
The ESD testing procedure shall be per section 3.2, Figure 4, and as follows:
c. Connect an individual component pin and/or terminal to terminal A. Leave all other
component pins and/or terminals unconnected.
d. Apply one (1) positive pulse at the specified voltage to the PUT. Wait a minimum of one
(1) second before applying the next test pulse. The use of three (3) pulses at each
stress voltage polarity is required.
e. Apply one (1) negative pulse at the specified voltage to the PUT. Wait a minimum of one
(1) second before applying the next test pulse. The use of three (3) pulses at each
stress voltage polarity is required.
f. Disconnect the PUT from testing and connect the next individual component pin and/or
terminal to terminal A. Leave all other component pins and/or terminals unconnected.
g. Repeat steps (d) through (f) until every pin and/or terminal not connected to terminal B is
pulsed at the specified voltage (see section 3.2).
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h. Repeat steps (b) through (g) until all pin and/or terminal combinations have been
stressed.
i. Test the next component in the sample group and repeat steps (b) through (h) until all
components in the sample group have been tested at the specified voltage level.
j. Submit the components for complete parametric testing (final electrical verification) per
the user device specification at room temperature followed by hot temperature, unless
specified otherwise in the user device specification, and determine whether the
components meet the failure criteria requirements specified in section 4. It is permitted
to perform the parametric testing (final electrical verification) per user device specification
after all sample groups have been tested.
k. Using a new sample group, select the next stress voltage level as specified in Figure 4
and repeat steps (b) through (j)
l. Repeat steps (b) through (k) until failure occurs or the maximum withstanding voltage
level has been reached.
4. FAILURE CRITERIA:
A component will be defined as a failure if, after exposure to ESD pulses, the component fails
any of the following criteria:
1. The component exceeds the allowable shift values for the specific key parameters listed
in Table 2. Other component parameters and allowable shift values may be specified in
the user device specification. During initial parametric testing, a data log shall be made
for each component listing the applicable parameter measurement values. This data log
will be compared to the parameters measured during final parametric testing to
determine the shift value. Components exceeding the allowable shift value will be
defined as a failure.
2. The component no longer meets the user device specification requirements. Complete
parametric testing (initial and final electrical verification) shall be performed per
applicable user device specification at room temperature followed by hot temperature,
unless specified otherwise in the user device specification.
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Bipolar ICES, ICBO, and IEBO Ten times (10X) the initial
measurement
5. ACCEPTANCE CRITERIA:
A component passes a voltage level if all components stressed at that voltage level and below
pass. All the samples must meet the measurement requirements specified in section 3. and the
failure criteria requirements specified in section 4. Using the classification levels specified in
Table 3, classify the components according to the highest ESD voltage level survived during ESD
testing. The ESD withstanding voltage shall be defined for each component by the supplier.
M0 ≤ 25 V
M1A > 25 V to ≤ 50 V
M4 > 400 V
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100 V
FAIL PASS
50 V 200 V
25 V 50 V 100 V 400 V
Note 1: Classify the components according to the highest ESD voltage level survived during
ESD testing.
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Revision History
A July 18, 2005 Revised the following: Sections 1.2, 2.1, 3.1, and 5; Tables 1 and
3; Figures 1 and 3.
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