RAiO

RA8835
Dot Matrix
LCD Controller
Specification

Version 1.2
June 1, 2005

RAiO Technology Inc.

©Copyright RAiO Technology Inc. 2004, 2005

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 RA8835
Preliminary Version 1.2 Dot Matrix LCD Controller

1. Overview
The RA8835 is a controller IC that can display text and graphics on LCD panel. It can display layered text and
graphics, scroll the display in any direction and partition the display into multiple screens. It also stores text,
character codes and bitmapped graphics data in external frame buffer memory. Display controller functions
include transferring data from the controlling microprocessor to the buffer memory, reading memory data,
converting data to display pixels and generating timing signals for the buffer memory, LCD panel.

The RA8835 has an internal character generator with 160, 5 X 7 pixel characters in internal mask ROM. The
character generators support up to 64, 8 X 16 pixel characters in external character generator RAM and up to
256, 8 X 16 pixel characters in external character generator ROM.

2. Features
Text, graphics and combined text/graphics programmed character generator ROM
display modes Up to 64, 8 X 16 pixel characters in external
Three overlapping screens in graphics mode character generator RAM
Up to 640 X 256 pixel LCD panel display Up to 256, 8 X 16 pixel characters in external
resolution character generator ROM
Programmable cursor control 6800 and 8080 family microprocessor interfaces
Smooth horizontal and vertical scrolling of all or Low power consumption—3.5 mA operating
part of the display current (VDD = 3.5V), 0.05 μA standby current
1/2-duty to 1/256-duty LCD drive Package:
Up to 640 X 256 pixel LCD panel display RA8835P3N: QFP-60 pin (Lead Free)
resolution memory RA8835P4N: TQFP-60 pin (Lead Free)
160, 5 X 7 pixel characters in internal mask- Power: 2.7 to 5.5 V

3. Block Diagram
V A [1 5 :0 ], V D [7 :0 ],
VCE, VRD, VW R TEST

2 5 6 B yte D is p la y R A M S ys te m
CGROM I/F C o n f ig u r e

R e g is t e r s C u rs o r D a ta
B lo c k C o n t r o lle r L a tc h

MCU X ’t a l T im in g
I/F OSC G e n e ra to r

D [7 :0 ], C S , R D , W R XD XG Y D IS , L P , W F , X S C L ,
A0, R ES, SEL1, SEL2 Y D , Y S C L , X D [3 :0 ]

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 RA8835
Preliminary Version 1.2 Dot Matrix LCD Controller

4. Package

SEL1
SEL2

VWR

YSCL

XSCL
SECL
VRD
RES

VCE

YDIS
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7

GND
WR

VD4
VD5
VD6
VD7

XD0
XD1
XD2
XG

RD
NC
NC

WF
YD

LP
XD 50 45 40 35 VA8 45 31
VD3 46 30 XD3
CS VA9
A0
TM VA10 VD2 D7
VDD
D0
RAiO VA11
VA12
VD1
VD0 RAiO
TM D6
D5
VA15 D4
D1 60 30 VA13
VA14 D3
D2 1 RA8835P3N 29 TEST
VA13
VA12 RA8835P4N
D2
D1
D3 VA14 D0
VA11
D4 05xx VA15 VDD
D5 Index VD0
VA10 05xx
VA9 A0
D6 5 Date Code(Year 2005) 25 VD1 VA8 CS
VD2 Date Code(Year 2005) XD
VA7 Index
6 10 15 20 XG
VA6
NC 60 16 SEL1
1 15
YDIS
YD
YSCL
GND
LP
XECL
XSCL

WF
D7
XD3
XD2
XD1
XD0

VD7
VD6
VD5
VD4
VD3

VCE

RES
VWR

VRD

NC
NC
RD
WR
VS5

SEL2
VA4
VA3
VA2
VA1
VA0
Figure 4-1: RA8835P3N(QFP-60 Pin) Figure 4-2: RA8835P4N (TQFP-60 Pin)

5. Pin Descriptions
5.1.1. MCU Interface

Pin Name Function

MCU Data Bus.
D0 to D7 Tri-state input/output pins. Connect these pins to an 8- or 16-bit microprocessor
bus.
MCU Interface Select.
The RA8835 series supports both 8080 family processors (such as the 8085 and
Z80®) and 6800 family processors (such as the 6802 and 6809).

SEL1 SEL2* Interface A0 RD WR CS

8080
SEL1, 0 0 A0 RD WR CS
family
SEL2 6800
1 0 A0 E R/ W CS
family

SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does
appear on SEL1, decouple it to ground using a capacitor placed as close to the
pin as possible.

Read Control or Enable.

When the 8080 family interface is selected, this signal acts as the active-LOW
RD read strobe. The RA8835 series output buffers are enabled when this signal is
or active.
E When the 6800 family interface is selected, this signal acts as the active-HIGH
enable clock.
Data is read from or written to the RA8835 series when this clock goes HIGH.

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 RA8835
Preliminary Version 1.1 Dot Matrix LCD Controller

Write Control or Read/Write Control.

WR When the 8080 family interface is selected, this signal acts as the active-LOW
or write strobe. The bus data is latched on the rising edge of this signal.
When the 6800 family interface is selected, this signal acts as the read/write
R/ W control signal. Data is read from the RA8835 series if this signal is HIGH, and
written to the RA8835 series if it is LOW.
Chip Select.
This active-LOW input enables the RA8835 series. It is usually connected to the
CS
output of an address decoder device that maps the RA8835 series into the
memory space of the controlling microprocessor.
Command/Data Select.
8080 Family Interface:

A0 RD WR Function
0 0 1 Status flag read
Display data and cursor address
1 0 1
read
0 1 0 Display data and parameter write
1 1 0 Command write
A0
6800 Family Interface:
A0 R/ W E Function
0 1 1 Status flag read
Display data and cursor address
1 1 1
read
0 0 1 Display data and parameter write
1 0 1 Command write

Hardware Reset.
This active-LOW input performs a hardware reset on the RA8835 series. It is a
RES
Schmitt-trigger input for enhanced noise immunity; however, care should be
taken to ensure that it is not triggered if the supply voltage is lowered.

5.1.2 Display Memory Control

The RA8835 series can directly access static RAM and PROM. The designer may use a mixture of
these two types of memory to achieve an optimum trade-off between low cost and low power
consumption.

Pin Name Function

16-bit Display Memory Address.
VA0 to VA15 When accessing character generator RAM or ROM, VA0 to VA3, reflect the
lower 4 bits of the RA8835 row counter.
Display Memory Data Bus.
VD0 to VD7 8-bit tri-state display memory data bus. These pins are enabled when VRD or
VWR is LOW.
Display Memory Write Control.
VWR
Active-LOW display memory write control output.
Display Memory Read Control.
VRD
Active-LOW display memory read control output.
VCE Display Memory Chip Select.

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 RA8835
Preliminary Version 1.1 Dot Matrix LCD Controller

Active-LOW static memory standby control signal. VCE can be used with CS .

5.1.3 LCD Drive Signals

In order to provide effective low-power drive for LCD matrixes, the RA8835 series can directly
control both the X- and Y-drivers using an enable chain.

Pin Name Function

Data Output for Driver.
XD0 to XD3 4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs
of the X-driver chips.
Latch Clock.
The falling edge of XSCL latches the data on XD0 to XD3 into the input shift
XSCL
registers of the X-drivers. To conserve power, this clock halts between LP and
the start of the following display line (See section 6.3.7).
Trigger Clock for Chain Cascade.
XECL The falling edge of XECL triggers the enable chain cascade for the X-drivers.
Every 16th clock pulse is output to the next X-driver.
Latch Pulse.
LP latches the signal in the X-driver shift registers into the output data latches.
LP
LP is a falling-edge triggered signal, and pulses once every display line.
Connect LP to the Y-driver shift clock on modules.
AC Drive Output.
WF The WF period is selected to be one of two values with SYSTEM SET
command.
Latch Clock for YD.
The falling edge of YSCL latches the data on YD into the input shift registers of
YSCL
the Y-drivers. YSCL is not used with driver ICs which use LP as the Y-driver
shift clock.
Data Pulse Output for Y Drivers.
YD It is active during the last line of each frame, and is shifted through the Y drivers
one by one (by YSCL), to scan the display’s common connections.
Power-down Output Signal.
YDIS is HIGH while the display drive outputs are active. YDIS goes LOW one or
two frames after the sleep command is written to the RA8835 series. All Y-
YDIS driver outputs are forced to an intermediate level (de-selecting the display
segments) to blank the display. In order to implement power-down operation in
the LCD unit, the LCD power drive supplies must also be disabled when the
display is disabled by YDIS.

5.1.4. Oscillator and Power

Pin Name Function

Crystal Connection for Internal Oscillator
XG This pin can be driven by an external clock source that satisfies the timing
specifications of the EXT f0 signal (See section 7.3.6).
Crystal Connection for Internal Oscillator
XD
Leave this pin open when using an external clock source.
2.7 to 5.5V Supply.
VDD
This may be the same supply as the controlling microprocessor.
GND Ground

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 RA8835
Preliminary Version 1.1 Dot Matrix LCD Controller

Test Pin.
TEST
This is a test pins. No need for connection(NC).
Note: The peak supply current drawn by the RA8835 series may be up to ten times the average
supply current. The power supply impedance must be kept as low as possible by ensuring
that supply lines are sufficiently wide and by placing 0.47μF decoupling capacitors that have
good high-frequency response near the device’s supply pins.

6. System Application

LCD
SRAM Driver

LCD
MCU RA8835 Driver LCD Panel

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