1.

What is the difference between an initial and final block of

the systemverilog?
Ans: Final block is a new concept which was introduced in System Verilog.

The basic difference between these two are evident from the nomenclature, i.e,
Initial block starts getting executed during simulation time t=0 while the Final block
gets executed when the simulation is completed.

Before getting into details, there is one similarity between these two sequential block
of codes, both of them gets executed only once during the simulation

Now getting back to the difference between Initial and Final blocks, Initial blocks can
contain some # delays or wait statements or some wait for events, but the Final
block should not contains any such things.

Final block should get executed with 0 simulation time. Ideally this is used for test
case status reporting or some display statements that have to be printed after the
test case execution is completed

2. Explain the simulation phases of SystemVerilog verification?

As one uses systemverilog as a verification language, one needs to understand how to setup and
control the simulation environment to get maximum reporting without generating erroneous
reports.

Here are some pointers from “Systemverilog for Verification” by Chris Spear that will enhance
your understanding of the simulation phases for systemverilog.

Build Phase
– Generate configuration : Randomize the configuration of the DUT and surrounding environment
– Build environment : Allocate and connect the testbench components based on the
configuration.
A testbench component is one that only exists in the testbench, as opposed to physical
components in the design that are built with RTL.
– Reset the DUT
– Configure the DUT : Based on the generated configuration from the first step, load the DUT
command registers

Run Phase
– Start environment : Run the testbench components such as BFMs and stimulus generators
– Run the test : Start the test and then wait for it to complete. It is easy to tell when a directed
test has completed, but doing so can be complex for a random test. You can use the testbench
layers as a guide. Starting from the top, wait for layer to drain all the inputs from the previous
layer (if any), wait for the current layer to become idle, and wait for the next lower layer. You
should use time-out checkers to make sure the DUT or testbench does not lock up.

Wrap-up Phase
– Sweep : After the lowest layer completes, you need to wait for the final transactions to drain
out of the DUT.
– Report : Once DUT is idle, sweep the testbench for lost data. Sometimes the scoreboard holds
the transactions which never came out, perhaps because they were dropped by the DUT. Armed
with this information, you can create the final report on whether the test passed or failed. If it
failed, be sure to delete any functional coverage results, as they may not be correct.

3. What is the Difference between SystemVerilog packed and unpacked array?

In my last article on plain old Verilog Arrays, I discussed their very limited feature
set. In comparison, SystemVerilog arrays have greatly expanded capabilities
both for writing synthesizable RTL, and for writing non-synthesizable test
benches. In this article, we’ll take a look at the synthesizable features of
SystemVerilog Arrays we can use when writing design RTL.
Packed vs Unpacked SystemVerilog Arrays
Verilog had only one type of array. SystemVerilog arrays can be
either packed or unpacked. Packed array refers to dimensions declared after the
type and before the data identifier name. Unpacked array refers to the
dimensions declared after the data identifier name.

1 bit [7:0] c1; // packed array of scalar bit

2 real u [7:0]; // unpacked array of real

4 int Array[0:7][0:31]; // unpacked array declaration using ranges

5 int Array[8][32]; // unpacked array declaration using sizes

Packed Arrays

A one-dimensional packed array is also called a vector. Packed array divides a

vector into subfields, which can be accessed as array elements. A packed array
is guaranteed to be represented as a contiguous set of bits in simulation and
synthesis.

Packed arrays can be made of only the single bit data types (bit, logic, reg),
enumerated types, and other packed arrays and packed structures. This also
means you cannot have packed arrays of integer types with predefined widths
(e.g. a packed array of byte).
Unpacked arrays

Unpacked arrays can be made of any data type. Each fixed-size dimension is
represented by an address range, such as [0:1023], or a single positive number
to specify the size of a fixed-size unpacked array, such as [1024]. The notation
[size] is equivalent to [0:size-1].

Indexing and Slicing SystemVerilog Arrays

Verilog arrays could only be accessed one element at a time. In SystemVerilog

arrays, you can also select one or more contiguous elements of an array. This is
called a slice. An array slice can only apply to one dimension; other dimensions
must have single index values in an expression.
Multidimensional Arrays

Multidimensional arrays can be declared with both packed and unpacked

dimensions. Creating a multidimensional packed array is analogous to slicing up
a continuous vector into multiple dimensions.

When an array has multiple dimensions that can be logically grouped, it is a good
idea to use typedef to define the multidimensional array in stages to enhance
readability.

1 bit [3:0] [7:0] joe [0:9] // 10 elements of 4 8-bit bytes

2 // (each element packed into 32 bits)

3

4 typedef bit [4:0] bsix; // multiple packed dimensions with typedef

5 bsix [9:0] v5; // equivalent to bit[4:0][9:0] v5

7 typedef bsix mem_type [0:3]; // array of four unpacked 'bsix' elements

8 mem_type ba [0:7]; // array of eight unpacked 'mem_type' elements

9 // equivalent to bit[4:0] ba [0:3][0:7] - thanks Dennis!

SystemVerilog Array Operations

SystemVerilog arrays support many more operations than their traditional Verilog
counterparts.

+: and -: Notation

When accessing a range of indices (a slice) of a SystemVerilog array, you can

specify a variable slice by using the [start+:increment width] and [start-
:decrement width] notations. They are simpler than needing to calculate the exact
start and end indices when selecting a variable slice. The increment/decrement
width must be a constant.

1 bit signed [31:0] busA [7:0]; // unpacked array of 8 32-bit vectors

2 int busB [1:0]; // unpacked array of 2 integers

3 busB = busA[7:6]; // select a 2-vector slice from busA

4 busB = busA[6+:2]; // equivalent to busA[7:6]; typo fixed, thanks Tomer!

Assignments, Copying, and other Operations

SystemVerilog arrays support many more operations than Verilog arrays. The
following operations can be performed on both packed and unpacked arrays.
1A = B; // reading and writing the array

2 A[i:j] = B[i:j]; // reading and writing a slice of the array

3 A[x+:c] = B[y+:d]; // reading and writing a variable slice of the array

4 A[i] = B[i]; // accessing an element of the array

5A == B; // equality operations on the array

6 A[i:j] != B[i:j]; // equality operations on slice of the array

Packed Array Assignment

A SystemVerilog packed array can be assigned at once like a multi-bit vector, or

also as an individual element or slice, and more.

1 logic [1:0][1:0][7:0] packed_3d_array;

3 always_ff @(posedge clk, negedge rst_n)

4 if (!rst_n) begin

5 packed_3d_array <= '0; // assign 0 to all elements of array

6 end

7 else begin

8 packed_3d_array[0][0][0] <= 1'b0; // assign one bit

9 packed_3d_array[0][0] <= 8'h0a; // assign one element

10 packed_3d_array[0][0][3:0] <= 4'ha; // assign part select

11 packed_3d_array[0] <= 16'habcd; // assign slice

12 packed_3d_array <= 32'h01234567; // assign entire array as vector

13 end

Unpacked Array Assignment

All or multiple elements of a SystemVerilog unpacked array can be assigned at

once to a list of values. The list can contain values for individual array elements,
or a default value for the entire array.

1 logic [7:0] a, b, c;

2 logic [7:0] d_array[0:3];

3 logic [7:0] e_array[3:0]; // note index of unpacked dimension is reversed

4 // personally, I prefer this form

5 logic [7:0] mult_array_a[3:0][3:0];

6 logic [7:0] mult_array_b[3:0][3:0];

8 always_ff @(posedge clk, negedge rst_n)

9 if (!rst_n) begin

10 d_array <= '{default:0}; // assign 0 to all elements of array

11 end

12 else begin

13 d_array <= '{8'h00, c, b, a}; // d_array[0]=8'h00, d_array[1]=c, d_array[2]=b, d_array[3]=a

14 e_array <= '{8'h00, c, b, a}; // e_array[3]=8'h00, e_array[2]=c, e_array[1]=b, d_array[0]=a

15 mult_array_a <= '{'{8'h00, 8'h01, 8'h02, 8'h03},

16 '{8'h04, 8'h05, 8'h06, 8'h07},

17 '{8'h08, 8'h09, 8'h0a, 8'h0b},

18 '{8'h0c, 8'h0d, 8'h0e, 8'h0f}}; // assign to full array

19 mult_array_b[3] <= '{8'h00, 8'h01, 8'h02, 8'h03}; // assign to slice of array

20 end
Conclusion
This article described the two new types of SystemVerilog arrays—
packed and unpacked—as well as the many new features that can be used to
manipulate SystemVerilog arrays. The features described in this article are all
synthesizable, so you can safely use them in SystemVerilog based RTL designs
to simplify coding. In the next part of the SystemVerilog arrays article, I will
discuss more usages of SystemVerilog arrays that can make your SystemVerilog
design code even more efficient. Stay tuned!

4. What is "This " keyword in the systemverilog?

SystemVerilog this keyword

this keyword is used to refer to class properties. this keyword is used to unambiguously
refer to class properties or methods of the current instance. this is a pre-defined class
handle referring to the object from which it is used,
calling this.variable means object.variable.

 this keyword shall only be used within non-static class methods

 this keyword refers to the object handle in which it is invoked

this keyword SystemVerilog

*Click on image for a better view

this keyword example

In the example below,

The addr, data, write and pkt_type are the property of both class and an argument to the
function new, as the name in both are same.this will lead to an ambiguity in assignment and
values will not be assigned properly.

class packet;
 //class properties

bit [31:0] addr;

bit [31:0] data;

bit write;

string pkt_type;

//constructor

function new(bit [31:0] addr,data,bit write,string pkt_type);

addr = addr;

data = data;

write = write;

pkt_type = pkt_type;

endfunction

//method to display class prperties

function void display();

$display("---------------------------------------------------------");

$display("\t addr = %0h",addr);

$display("\t data = %0h",data);

$display("\t write = %0h",write);

$display("\t pkt_type = %0s",pkt_type);

$display("---------------------------------------------------------");

endfunction

endclass
module sv_constructor;

packet pkt;

initial begin

pkt = new(32'h10,32'hFF,1,"GOOD_PKT");

pkt.display();

end

endmodule

Simulator Output

addr = 0
data = 0
write = 0
pkt_type =

5. What is alias in SystemVerilog?

6. randomized in the systemverilog test bench?

7. in SystemVerilog which array type is preferred for memory declaration and
why?
8. How to avoid race round condition between DUT and test bench in
SystemVerilog verification?
9. What are the advantages of the systemverilog program block?
10. What is the difference between logic and bit in SystemVerilog?
11. What is the difference between datatype logic and wire?
12. What is a virtual interface?
13. What is an abstract class?
14. What is the difference between $random and $urandom?
15. What is the expect statements in assertions?
16. What is DPI?
17. What is the difference between == and === ?
18. What are the system tasks?
19. What is SystemVerilog assertion binding and advantages of it?
20. What are parameterized classes?
21. How to generate array without randomization?
22. What is the difference between always_comb() and always@(*)?
23. What is the difference between overriding and overloading?
24. Explain the difference between deep copy and shallow copy?
25. What is interface and advantages over the normal way?
26. What is modport and explain the usage of it?
27. What is a clocking block?
28. What is the difference between the clocking block and modport?
29. System Verilog Interview Questions, Below are the most frequently asked
questions.
30. What are the different types of verification approaches?
31. What are the basic testbench components?
32. What are the different layers of layered architecture?
33. What is the difference between a $rose and @ (posedge)?
34. What is the use of extern?
35. What is scope randomization?
36. What is the difference between blocking and non-blocking assignments?
37. What are automatic variables?
38. What is the scope of local and private variables?
39. How to check if any bit of the expression is X or Z?
40. What is the Difference between param and typedef?
41. What is `timescale?
42. Explain the difference between new( ) and new[ ] ?
43. What is the difference between task and function in class and Module?
44. Why always blocks are not allowed in the program block?
45. Why forever is used instead of always in program block?
46. What is SVA?
47. Explain the difference between fork-join, fork-join_none, and fork- join_any?
48. What is the difference between mailboxes and queues?
49. What is casting?
50. What is inheritance and polymorphism?
51. What is callback?
52. What is constraint solve-before?
53. What is coverage and what are different types?
54. What is the importance of coverage in SystemVerilog verification?
55. When you will say that verification is completed?
56. What are illegal bins? Is it good to use it and why?
57. What is the advantage of seed in randomization?
58. What is circular dependency?
59. What is “super “?
60. What is the input skew and output skew in the clocking block?
61. What is a static variable?
62. What is a package?
63. What is the difference between bit [7:0] and byte?
64. What is randomization and what can be
65. What are the constraints? Is all constraints are bidirectional?
66. What are in line constraints?
67. What is the difference between rand and randc?
68. Explain pass by value and pass by ref?
69. What are the advantages of cross-coverage?
70. What is the difference between associative and dynamic array?
71. What is the type of SystemVerilog assertions?
72. What is the difference between $display,$strobe,$ monitor?
73. Can we write SystemVerilog assertions in class?
74. What is an argument pass by value and pass by reference?