The Bhopal School of Social Sciences

Department of Computer Applications

BCA I Year 2019
Digital Computer Organization
Practice Questions
PART I

1 The NAND gate output will be low if the two inputs are_________

2   
The simplification of the Boolean expression ABC  ABC is_________
3 The number of control lines for a 8 to 1 multiplexer is___________
4 EPROM contents can be erased by exposing it to____________
5 The Boolean expression A.B  A.B  A.B is equivalent to__________
1.

6 The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either_____
7 When simplified with Boolean Algebra (x + y)(x + z) simplifies to_____________
8 The gates required to build a half adder are___________
9 The code where all successive numbers differ from their preceding number by single bit is______
10 -8 is equal to signed binary number______
11 DeMorgan’s first theorem shows the equivalence of___________
12 The device which changes from serial data to parallel data is__________
13 A device which converts BCD to Seven Segment is called_______
14 In a JK Flip-Flop, toggle means____________
15 The logic circuit shown in the given can be minimised to
16 How many AND gates are required to realize Y = CD+EF+G ___________
17 How many select lines will a 16 to 1 multiplexer will have__________
18 How many flip flops are required to construct a decade counter____________
19 In a RAM, information can be stored
i. By the user, number of times.
ii. By the user, only once.
iii. By the manufacturer, a number of times.
iv. By the manufacturer only once.
20 The chief reason why digital computers use complemented subtraction is that it
i. Simplifies the circuitry.
ii. Is a very simple process.
iii. Can handle negative numbers easily.
iv. Avoids direct subtraction.
21 In a positive logic system, logic state 1 corresponds to_______
22 The process of entering data into a ROM is called
(A) Burning in the ROM (B) programming the ROM (C) Changing the ROM (D) charging the ROM
23 The NOR gate output will be low if the two inputs are_____________
24 How many flip-flops are required to construct mod 30 counter
(A) 5 (B) 6 (C) 4 (D) 8
25 How many address bits are required to represent a 32 K memory_________
26 _______memory requires refreshing.
27 Shifting a register content to left by one bit position is equivalent to____________
28 For JK flip flop with J=1, K=0, the output after clock pulse will be
29 The output of SR flip flop when S=1, R=0 is__________
30 The number of control lines for 32 to 1 multiplexer is_______
31 How many two-input AND and OR gates are required to realize Y=CD+EF+G_________
32 ________ and ________ memory cannot be accessed randomly
33 When an input signal A=11001 is applied to a NOT gate serially, its output signal is

34 A full adder logic circuit has_________ input and _________output.

35 The information in ROM is stored
i. By the user any number of times.
ii. By the manufacturer during fabrication of the device.
iii. By the user using ultraviolet light.
iv. By the user once and only once.
36 How many address bits are required to represent 4K memory_______________
37 For JK flipflop J = 0, K=1, the output after clock pulse will be______________
38 _________ memories stores the most number of bits64K  8 memory.

PART – II
1 Define Logic Gate, Logic Circuit,Boolean algebra.
2 Describe positive and Negative logic?
3 Explain OR gate – Symbol , Truth table, Logic expression
4 Explain AND gate – Symbol , Truth table, Logic expression
5 Explain NAND gate – Symbol , Truth table, Logic expression
6 Explain NOR gate – Symbol, Truth table, Logic expression
7 Explain Ex-OR gate – Symbol, Truth table, Logic expression
8 Gives list of Boolean Postulates, Boolean Laws and Theorems?
9 Define Max term and Min Term, SOP and POS with example.
10 Prove the following using rules of Boolean algebra, OR simplify/Minimize
I. A+BC = (A+B)(A+C)
II. ABC+ABC+ABC+ABC+ABC = A+ABC
III. (A+B+C)(A+B+C) = A+BC+BC
IV. C (B +C) (A+B+C)
V. A’B+ABC’+ABC
VI. XY+X’Z+YZ= XY+X’Z
VII. X’Y’Z’+X’Y’Z+XY’Z=Y’(X’+Z)
VIII. (A’+B’).(A’+B).(A+B’)=A’+B’
IX. XY’+YZ’+ZX’=X’Y+Y’Z+Z’X
X. (x+y+z) (x+y+z’) (x’+y+z) (x’+y+z’) (x’+y’+z’)
XI. x’yz’+ x’yz+ xyz’
XII. (a+b)(a’+b’)=a’b+ab’
XIII. A(B + B’C + B’C’) = A
XIV. A + A’B’ = A + B'
XV. (x + y + z).(x’ + y + z) = y + z
XVI. A’B’C + A’BC + AB’C = A’C + B’C
XVII. A(B + B’C + B’C’) = A
XVIII. AB + AB’+ A’C + A’C’
XIX. XY + XYZ’ + XYZ’ + XZY
 XX. XY(X’YZ’+ XY’Z’+ XY’Z’)
XXI. AB + AB’ + A’C + A’C’
XXII. [(x + y)’ + (x + y)’]’ = x + y
11 Draw logic diagram for following Boolean expression
F=AB+CD
Y= AB+(B’+C)
Y= (A+B)(B+C’)
Y=(A+B’C’)(AC+B)
Y=ABC+ABC+ABC+ABC
Y= (A+B)’+(B.C)’
12 State and prove the two basic De Morgan’s theorems
13 Find the complement of the following Boolean function : F1 = AB’ + C’D’
14 Write the minterm and Maxterm for a function F(x,y,z) when x =0, y = 1, z = 0.
15 Write the minterm and Maxterm for a function F(x,y,z) when x =1, y = 0, z = 0.
16 What is a universal gate? Give examples. Realize the basic gates with any universal gate.
17 Construct a logic circuit diagram for the exclusive EX-OR function using only NAND gates.
18 Describe Half adder with truth table and circuit diagram.
19 Describe Full adder with truth table and circuit diagram.
20 Draw the logic diagram of a full Adder using half adders and explain its working
with the help of a truth table.
21 With the help of a truth table explain the working of a half subtractor. Draw the logic diagram
using gates.
22 Draw the logic diagram of a full subtractor using half subtractors
and explain its working with the help of a truth table.
23 Explain with block diagram Multiplexer with truth table and circuit diagram.
24 Explain with block diagram 2 to 1 and 4 to1 line multiplexer with truth table and circuit diagram.
25 Explain with block diagram demultiplexer with truth table and circuit diagram .
26 Explain with block diagram 1-2 line demultiplexer and 1 to 4 line
demultiplexer with truth table and circuit diagram .
27 Describe advantages and disadvantages of multiplexer and demultiplexer.
28 Describe block diagram of digital system with truth table and circuit diagram
a. Octal to Binary Encoder
b. Decimal to BCD Encoder
29 Explain 3-8 Decoder or Binary to Octal decoder with truth table and circuit diagram.
30 What is flip flop? List out the application of flip-flop.
31 Explain R-S flip flop with truth table?
32 How can a R-S flip-flop be constructed using NOR gate? Explain it’s working with truth table?
33 How can a R-S flip-flop be constructed using NAND gates? Explain it’s working with truth table?
34 Write short note on J-K flip-flop with truth table and circuit diagram?
35 Explain working of D and T flip flop with truth table and circuit diagram.
36 Explain Master-slave J-K flip-flop.
37 What is race around condition? How is it eliminated in a Master-slave J-K flip-flop?
38 Define Karnaugh Map with Pair, Quad and Octet on K-Map with example.
39 Define Redundancy and DON’T CARE Condition in K-Map with example.
40 Minimize the following logic function using K-maps
a) F(A,B,C,D)=Σ (1,3,5,6,7,9,11,13,14,15)
b) F(A,B,C,D)=Σ(0,2,4,5,7,8,10,12,13,15)
c) F(A,B,C,D) =Σ(0,3,4,5,7,8,9,11,12,13,15)
 d) F(U,V,W,Z)= π (0,1,3,5,6,7,10,14,15)
e) F(A,B,C,D) = Σ(5,6,7,8,9,12,13,14,15)
f) F(A,B,C)= π (1,3,5,6,7,9,11,13,14,15)
g) F(U,V,W,Z)= π (1,2,3,4,5,6,7,9,10,11,13,14,15)
h) F(A,B,C,D)=Σ (0,1,3,4,5,6,7,9,10,11,13, 15)
i) F(A,B,C,D)=Σ (1,3,5,6,7,9,11,13,14,15)
j) F(A,B,C,D)=Σ (1,3,7,11,15)+d(0,2,5)
k) F(A,B,C,D)=Σ (0,3,4,5,7)+d(8,9,,10,11,12,13,14,15)
PART III
1. Distinguish between ROM, PROM, EPROM, EEPROM.
2. Differentiation between Static RAM and Dynamic RAM
3. A certain memory has a capacity of 4K 8
i. How many data input and data output lines does it have?
ii. How many address lines does it have?
iii. What is its capacity in bytes?
4. Design a 32:1 multiplexer using two 16:1 multiplexers and a 2:1 multiplexer.
5. The capacity of 2K  16 PROM is to be expanded to 16 K  16. Find the number of PROM chips
required and the number of address lines in the expanded memory.
6. Implement the following function using a 3 line to 8 line decoder.
i. S(A,B,C) = ∑ m(1,2,4,7)
ii. C (A,B,C) = ∑ m ( 3,5,6,7)
7. Minimize the following logic function using K-maps and realize using NAND and NOR gates.
i. F(A, B, C, D)  ∑ m(1,3,5,8,9,11,15)  d(2,13)
8. A staircase light is controlled by two switches one at the top of the stairs and another at the
bottom of stairs
a. Make a truth table for this system.
b. Write the logic equation is SOP form.
c. Realize the circuit using AND-OR gates.
9. A combinational circuit has 3 inputs A, B, C and output F. F is true for following input
combinations
 A and C are False, B is True
 A and B are False, C is True
 A False , B and C are True
 A, B, C are False
 A, B, C are True
i. Write the Truth table for F. Use the convention True=1 and False = 0.
ii. Write the simplified expression for F in SOP form.
iii. Write the simplified expression for F in POS form.
iv. Draw logic circuit using minimum number of 2-input NAND gates.
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