VHDL Programs
VHDL Programs
VHDL Programs
Dataflow modeling:
AND GATE:
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port (x,y: in std_logic;
z: out std_logic);
end and2;
entity or2 is
port(x,y: in std_logic;
z: out std_logic);
end or2;
entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;
entity nor2 is
port(x,y: in std_logic;
z: out std_logic);
end nor2;
architecture nor2_ data of nor2 is
begin
z<=x nor y;
end nor2_ data;
XOR GATE:
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(x,y: in std_logic;
z: out std_logic);
end xor2;
entity xnor2 is
port(x,y: in std_logic;
z: out std_logic);
end xnor2;
entity not1 is
port(x:in std_logic;
z:out std_logic);
end not1;
entity and2 is
port (x,y: in std_logic;
z: out std_logic);
end and2;
entity or2 is
port(x,y: in std_logic;
z: out std_logic);
end or2;
entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;
entity nor2 is
port(x,y: in std_logic;
z: out std_logic);
end nor2;
entity xor2 is
port(x,y: in std_logic;
z: out std_logic);
end xor2;
entity xnor2 is
port(x,y: in std_logic;
z: out std_logic);
end xnor2;
entity not1 is
port(x:in std_logic;
z:out std_logic);
end not1;
entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;
Library ieee;
use ieee.std_logic_1164.all;
entity nand2_1 is
port(a,b:in std_logic;
c:out std_logic);
end nand2_1;
entity nor2 is
port (x,y: in std_logic;
z: out std_logic);
end nor2;
Library ieee;
use ieee.std_logic_1164.all;
entity nor2_1 is
port(a,b:in std_logic;
c:out std_logic);
end nor2_1;
entity xnor2 is
port (x,y: in std_logic;
z: out std_logic);
end xnor2;
Library ieee;
use ieee.std_logic_1164.all;
entity xnor2_1 is
port(a,b:in std_logic;
c:out std_logic);
end xnor2_1;
entity decoder is
port(a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0) );
end decoder ;
library IEEE;
use IEEE.STD_LOGIC_1164.all,
entity ENCODER8 is
end ENCODER8;
begin
process (A)
begin
case A is
end case ;
end process ;
end ARCH;
9. Design of 8 to 1 multiplexer
library ieee;
use ieee.std_logic_1164.all;
entity mux8x1 is
port ( s : in std_logic_vector(2 downto 0);
d : in std_logic_vector(7 downto 0);
en : in std_logic;
y : out std_logic );
end mux8x1;
end binary_to_gray_arc;