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VHDL Programs

The document describes various logic gate designs using VHDL including: 1) Dataflow and behavioral modeling of common logic gates like AND, OR, NAND, etc. 2) Structural modeling of NAND, NOR and XNOR gates using lower level components. 3) Design of a 2 to 4 decoder using a case statement to decode 2-bit inputs to 4-bit outputs. 4) Design of an 8 to 3 encoder to encode 8-bit inputs to 3-bit outputs using a case statement.

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Venkatramana Reddy K
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69 views

VHDL Programs

The document describes various logic gate designs using VHDL including: 1) Dataflow and behavioral modeling of common logic gates like AND, OR, NAND, etc. 2) Structural modeling of NAND, NOR and XNOR gates using lower level components. 3) Design of a 2 to 4 decoder using a case statement to decode 2-bit inputs to 4-bit outputs. 4) Design of an 8 to 3 encoder to encode 8-bit inputs to 3-bit outputs using a case statement.

Uploaded by

Venkatramana Reddy K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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1.

Dataflow modeling:
AND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity and2 is
port (x,y: in std_logic;
z: out std_logic);
end and2;

architecture and2_data of and2 is


begin
z<=x and y;
end and2_ data;
OR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity or2 is
port(x,y: in std_logic;
z: out std_logic);
end or2;

architecture or2_data of or2 is


begin
z<=x or y;
end or2_ data;
NAND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;

architecture nand2_ data of nand2 is


begin
z<=x nand y;
end nand2_ data;
NOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nor2 is
port(x,y: in std_logic;
z: out std_logic);
end nor2;
architecture nor2_ data of nor2 is
begin
z<=x nor y;
end nor2_ data;
XOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xor2 is
port(x,y: in std_logic;
z: out std_logic);
end xor2;

architecture xor2_ data of xor2 is


begin
z<=x xor y;
end xor2_ data;
XNOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xnor2 is
port(x,y: in std_logic;
z: out std_logic);
end xnor2;

architecture xnor2_ data of xnor2 is


begin
z<=x xor y;
end xnor2_ data;
NOT GATE:
library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x:in std_logic;
z:out std_logic);
end not1;

architecture not1_ data of not1 is


begin
z<=not x;
end not1_ data;
2. Behavioral modeling:
AND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity and2 is
port (x,y: in std_logic;
z: out std_logic);
end and2;

architecture and2_behave of and2 is


begin
process(x,y)
begin
z<=x and y;
end process;
end and2_behave;
OR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity or2 is
port(x,y: in std_logic;
z: out std_logic);
end or2;

architecture or2_behave of or2 is


begin
process(x,y)
begin
z<=x or y;
end process;
end or2_behave;
NAND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;

architecture nand2_behave of nand2 is


begin
process(x,y)
begin
z<=x nand y;
end process;
end nand2_behave;
NOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nor2 is
port(x,y: in std_logic;
z: out std_logic);
end nor2;

architecture nor2_behave of nor2 is


begin
process(x,y)
begin
z<=x nor y;
end process;
end nor2_behave;
XOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xor2 is
port(x,y: in std_logic;
z: out std_logic);
end xor2;

architecture xor2_behave of xor2 is


begin
process(x,y)
begin
z<=x xor y;
end process;
end xor2_behave;
XNOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xnor2 is
port(x,y: in std_logic;
z: out std_logic);
end xnor2;

architecture xnor2_behave of xnor2 is


begin
process(x,y)
begin
z<=x xor y;
end process;
end xnor2_behave;
NOT GATE:
library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x:in std_logic;
z:out std_logic);
end not1;

architecture not1_behave of not1 is


begin
Process(x)
begin
z<=not x;
end process;
end not1_behave;
3. NAND LOGIC GATE STRUCTURAL MODELLING
library ieee;
use ieee.std_logic_1164.all;

entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;

architecture nand2_ data of nand2 is


begin
z<=x nand y;
end nand2_ data;

Library ieee;
use ieee.std_logic_1164.all;

entity nand2_1 is
port(a,b:in std_logic;
c:out std_logic);
end nand2_1;

architecture nand2_1_struct of nand2_1 is


component nand2
port(x,y:in std_logic;
z:out std_logic);
end component;
begin
a1:nand2 port map(a,b,c);
end nand2_1_struct;
4. NOR LOGIC GATE STRUCTURAL MODELLING
library ieee;
use ieee.std_logic_1164.all;

entity nor2 is
port (x,y: in std_logic;
z: out std_logic);
end nor2;

architecture nor2_ data of nor2 is


begin
z<=x nor y;
end nor2_ data;

Library ieee;
use ieee.std_logic_1164.all;

entity nor2_1 is
port(a,b:in std_logic;
c:out std_logic);
end nor2_1;

architecture nor2_1_struct of nor2_1 is


component nor2
port(x,y:in std_logic;
z:out std_logic);
end component;
begin
a1:nor2 port map(a,b,c);
end nor2_1_struct;
5. XNOR LOGIC GATE STRUCTURAL MODELLING
library ieee;
use ieee.std_logic_1164.all;

entity xnor2 is
port (x,y: in std_logic;
z: out std_logic);
end xnor2;

architecture xnor2_ data of xnor2 is


begin
z<=x xnor y;
end xnor2_ data;

Library ieee;
use ieee.std_logic_1164.all;

entity xnor2_1 is
port(a,b:in std_logic;
c:out std_logic);
end xnor2_1;

architecture xnor2_1_struct of xnor2_1 is


component xnor2
port(x,y:in std_logic;
z:out std_logic);
end component;
begin
a1:xnor2 port map(a,b,c);
end xnor2_1_struct;
6. Design of 2 to 4 decoder
Library IEEE ;
use IEEE.STD_LOGIC_1164

entity decoder is
port(a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0) );
end decoder ;

Architecture behavioral of decoder is


begin
Process(a)
begin
if (a = “00”)then
b <=”0001” ;
elsif (a= “01”)then
b <=”0010” ;
elsif (a= “10”)then
b <=”0100” ;
else
b <=”1000” ;
end if ;
end process ;
end behavioral ;
7. Design of 8 to 3 encoder

library IEEE;

use IEEE.STD_LOGIC_1164.all,

entity ENCODER8 is

port (A: in std_logic_vector (7 downto 0);

Y: out std_logic_vector (2 downto 0));

end ENCODER8;

architecture ARCH of ENCODER8 is

begin

process (A)

begin

case A is

when "00000001" => Y <= "000";

when "00000010" => Y <= "001";

when "00000100" => Y <= "010";

when "00001000" => Y <= "011";

when "00010000" => Y <= "100";

when "00100000" => Y <= "101";

when "01000000" => Y <= "110";

when "10000000" => Y <= "111";

when others => Y <= "XXX";

end case ;

end process ;

end ARCH;
9. Design of 8 to 1 multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity mux8x1 is
port ( s : in std_logic_vector(2 downto 0);
d : in std_logic_vector(7 downto 0);
en : in std_logic;
y : out std_logic );
end mux8x1;

Architecture mux_8x1 of mux8x1 is


begin
process (s,d,en)
begin
if(en='0') then y<='0';
else
case s is
when "000"=> y<=d(0);
when "001"=> y<=d(1);
when "010"=> y<=d(2);
when "011"=> y<=d(3);
when "100"=> y<=d(4);
when "101"=> y<=d(5);
when "110"=> y<=d(6);
when "111"=> y<=d(7);
when others=> y<='0';
end case;
end if;
end process;
end mux_8x1;
10. Design of 4 bit binary to gray converter
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity binary_to_gray is
port(din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0));
end binary_to_gray;

architecture binary_to_gray_arc of binary_to_gray is


begin
process (din) is
begin
if (din="0000") then
dout <= "0000";
elsif (din="0001") then
dout <= "0001";
elsif (din="0010") then
dout <= "0011";
elsif (din="0011") then
dout <= "0010";
elsif (din="0100") then
dout <= "0110";
elsif (din="0101") then
dout <= "0111";
elsif (din="0110") then
dout <= "0101";
elsif (din="0111") then
dout <= "0100";
elsif (din="1000") then
dout <= "1100";
elsif (din="1001") then
dout <= "1101";
elsif (din="1010") then
dout <= "1111";
elsif (din="1011") then
dout <= "1110";
elsif (din="1100") then
dout <= "1010";
elsif (din="1101") then
dout <= "1011";
elsif (din="1110") then
dout <= "1001";
else dout <= "1000";
end if;
end process;

end binary_to_gray_arc;

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