Random-access memory

Random-access memory (RAM /ræm/) is a form of computer memory that can be read and
changed in any order, typically used to store working data and machine code.[1][2] A random-
access memory device allows data items to be read or written in almost the same amount of time
irrespective of the physical location of data inside the memory. In contrast, with other direct-access
data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum
memory, the time required to read and write data items varies significantly depending on their
physical locations on the recording medium, due to mechanical limitations such as media rotation Example of writable volatile random-
speeds and arm movement. access memory: Synchronous
Dynamic RAM modules, primarily
RAM contains multiplexing and demultiplexing circuitry, to connect the data lines to the addressed used as main memory in personal
storage for reading or writing the entry. Usually more than one bit of storage is accessed by the computers, workstations, and
same address, and RAM devices often have multiple data lines and are said to be "8-bit" or "16- servers.
bit", etc. devices.

In today's technology, random-access memory takes the form of integrated circuit (IC) chips with MOS (metal-oxide-semiconductor) memory cells.
RAM is normally associated with volatile types of memory (such as DRAM modules), where stored information is lost if power is removed,
although non-volatile RAM has also been developed.[3] Other types of non-volatile memories exist that allow random access for read operations,
but either do not allow write operations or have other kinds of limitations on them. These include most types of ROM and a type of flash memory
called NOR-Flash.

The two main types of volatile random-access semiconductor memory are static random-access memory (SRAM) and dynamic random-access
memory (DRAM). Commercial uses of semiconductor RAM date back to 1965, when IBM introduced the SP95 SRAM chip for their System/360
Model 95 computer, and Toshiba used DRAM memory cells for its Toscal BC-1411 electronic calculator, both based on bipolar transistors.
Commercial MOS memory, based on MOS transistors, was developed in the late 1960s, and has since been the basis for all commercial
semiconductor memory. The first commercial DRAM IC chip, the Intel 1103, was introduced in October 1970. Synchronous dynamic random-
access memory (SDRAM) later debuted with the Samsung KM48SL2000 chip in 1992.

Contents
History
MOS RAM
Types
Memory cell
Addressing
Memory hierarchy
Other uses of RAM
Virtual memory
RAM disk
Shadow RAM
Recent developments
Memory wall
Timeline
SRAM
DRAM
SDRAM
SGRAM and HBM
See also
References
External links
History
Early computers used relays, mechanical counters[4] or delay lines for main memory functions.
Ultrasonic delay lines could only reproduce data in the order it was written. Drum memory could
be expanded at relatively low cost but efficient retrieval of memory items required knowledge of
the physical layout of the drum to optimize speed. Latches built out of vacuum tube triodes, and
later, out of discrete transistors, were used for smaller and faster memories such as registers. Such
registers were relatively large and too costly to use for large amounts of data; generally only a few
dozen or few hundred bits of such memory could be provided.

The first practical form of random-access memory was the Williams tube starting in 1947. It stored
data as electrically charged spots on the face of a cathode ray tube. Since the electron beam of the
CRT could read and write the spots on the tube in any order, memory was random access. The
capacity of the Williams tube was a few hundred to around a thousand bits, but it was much
smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at
the University of Manchester in England, the Williams tube provided the medium on which the first
electronically stored program was implemented in the Manchester Baby computer, which first These IBM tabulating machines from
successfully ran a program on 21 June 1948.[5] In fact, rather than the Williams tube memory being the 1930s used mechanical counters
to store information
designed for the Baby, the Baby was a testbed to demonstrate the reliability of the memory.[6][7]

Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It became a
widespread form of random-access memory, relying on an array of magnetized rings. By changing
the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since
every ring had a combination of address wires to select and read or write it, access to any memory
location in any sequence was possible. Magnetic core memory was the standard form of computer
memory system until displaced by solid-state MOS (metal-oxide-silicon) semiconductor memory in
integrated circuits (ICs) during the early 1970s.[8]

Prior to the development of integrated read-only memory (ROM) circuits, permanent (or read-only)
1 Megabit (MB) chip, one of the last
random-access memory was often constructed using diode matrices driven by address decoders, or
models developed by VEB Carl Zeiss
specially wound core rope memory planes. Jena in 1989.

Semiconductor memory began in the 1960s with bipolar memory, which used bipolar transistors.
While it improved performance, it could not compete with the lower price of magnetic core
memory.[9]

MOS RAM
The invention of the MOSFET (metal-oxide-semiconductor field-effect transistor), also known as the MOS transistor, by Mohamed M. Atalla and
Dawon Kahng at Bell Labs in 1959,[10] led to the development of metal-oxide-semiconductor (MOS) memory by John Schmidt at Fairchild
Semiconductor in 1964.[8][11] In addition to higher performance, MOS semiconductor memory was cheaper and consumed less power than
magnetic core memory.[8] The development of silicon-gate MOS integrated circuit (MOS IC) technology by Federico Faggin at Fairchild in 1968
enabled the production of MOS memory chips.[12] MOS memory overtook magnetic core memory as the dominant memory technology in the early
1970s.[8]

An integrated bipolar static random-access memory (SRAM) was invented by Robert H. Norman at Fairchild Semiconductor in 1963.[13] It was
followed by the development of MOS SRAM by John Schmidt at Fairchild in 1964.[8] SRAM became an alternative to magnetic-core memory, but
required six MOS transistors for each bit of data.[14] Commercial use of SRAM began in 1965, when IBM introduced the SP95 memory chip for the
System/360 Model 95.[9]

Dynamic random-access memory (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly
increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor, and had to be periodically refreshed
every few milliseconds before the charge could leak away. Toshiba's Toscal BC-1411 electronic calculator, which was introduced in 1965,[15][16][17]
used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and
capacitors.[16][17] While it offered improved performance over magnetic-core memory, bipolar DRAM could not compete with the lower price of
the then dominant magnetic-core memory.[18]

MOS technology is the basis for modern DRAM. In 1966, Dr. Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on
MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or
no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This
led to his development of a single-transistor DRAM memory cell.[14] In 1967, Dennard filed a patent under IBM for a single-transistor DRAM
memory cell, based on MOS technology.[19] The first commercial DRAM IC chip was the Intel 1103, which was manufactured on an 8 µm MOS
process with a capacity of 1 kb, and was released in 1970.[8][20][21]

Synchronous dynamic random-access memory (SDRAM) was developed by Samsung Electronics. The first commercial SDRAM chip was the
Samsung KM48SL2000, which had a capacity of 16 Mb.[22] It was introduced by Samsung in 1992,[23] and mass-produced in 1993.[22] The first
commercial DDR SDRAM (double data rate SDRAM) memory chip was Samsung's 64 Mb DDR SDRAM chip, released in June 1998.[24] GDDR
(graphics DDR) is a form of DDR SGRAM (synchronous graphics RAM), which was first released by Samsung as a 16 Mb memory chip in
1998.[25]

Types
The two widely used forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a bit of data is stored using the state
of a six-transistor memory cell, typically using six MOSFETs (metal-oxide-semiconductor field-effect transistors). This form of RAM is more
expensive to produce, but is generally faster and requires less dynamic power than DRAM. In modern computers, SRAM is often used as cache
memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair (typically a MOSFET and MOS capacitor, respectively),[26]
which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets
the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static
RAM, it is the predominant form of computer memory used in modern computers.

Both static and dynamic RAM are considered volatile, as their state is lost or reset when power is removed from the system. By contrast, read-only
memory (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writeable variants of
ROM (such as EEPROM and flash memory) share properties of both ROM and RAM, enabling data to persist without power and to be updated
without requiring special equipment. These persistent forms of semiconductor ROM include USB flash drives, memory cards for cameras and
portable devices, and solid-state drives. ECC memory (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct
random faults (memory errors) in the stored data, using parity bits or error correction codes.

In general, the term RAM refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most
computers. In optical storage, the term DVD-RAM is somewhat of a misnomer since, unlike CD-RW or DVD-RW it does not need to be erased
before reuse. Nevertheless, a DVD-RAM behaves much like a hard disc drive if somewhat slower.

Memory cell
The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary
information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored
until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

In SRAM, the memory cell is a type of flip-flop circuit, usually implemented using FETs. This means that SRAM requires very low power when not
being accessed, but it is expensive and has low storage density.

A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a "1" or a "0" in the cell. However, the charge
in this capacitor slowly leaks away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve
greater storage densities and lower unit costs compared to SRAM.
 SRAM Cell (6 Transistors)

DRAM Cell (1 Transistor and one

capacitor)

Addressing
To be useful, memory cells must be readable and writeable. Within the RAM device, multiplexing and demultiplexing circuitry is used to select
memory cells. Typically, a RAM device has a set of address lines A0... An, and for each combination of bits that may be applied to these lines, a set
of memory cells are activated. Due to this addressing, RAM devices virtually always have a memory capacity that is a power of two.

Usually several memory cells share the same address. For example, a 4 bit 'wide' RAM chip has 4 memory cells for each address. Often the width of
the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed.

Often more addresses are needed than can be provided by a device. In that case, external multiplexors to the device are used to activate the correct
device that is being accessed.

Memory hierarchy
One can read and over-write data in RAM. Many computer systems have a memory hierarchy consisting of processor registers, on-die SRAM
caches, external caches, DRAM, paging systems and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to
as "RAM" by many developers, even though the various subsystems can have very different access times, violating the original concept behind the
random access term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave
organization of the components make the access time variable, although not to the extent that access time to rotating storage media or a tape is
variable. The overall goal of using a memory hierarchy is to obtain the highest possible average access performance while minimizing the total cost
of the entire memory system (generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive
at the bottom).

In many modern personal computers, the RAM comes in an easily upgraded form of modules called memory modules or DRAM modules about the
size of a few sticks of chewing gum. These can quickly be replaced should they become damaged or when changing needs demand more storage
capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the CPU and other ICs on the motherboard, as well as
in hard-drives, CD-ROMs, and several other parts of the computer system.

Other uses of RAM

In addition to serving as temporary storage and working space for the operating system and
applications, RAM is used in numerous other ways.

Virtual memory
Most modern operating systems employ a method of extending RAM capacity, known as "virtual
memory". A portion of the computer's hard drive is set aside for a paging file or a scratch partition,
and the combination of physical RAM and the paging file form the system's total memory. (For
A SO-DIMM stick of laptop RAM,
example, if a computer has 2 GB of RAM and a 1 GB page file, the operating system has 3 GB roughly half the size of desktop RAM.
total memory available to it.) When the system runs low on physical memory, it can "swap"
portions of RAM to the paging file to make room for new data, as well as to read previously swapped information back into RAM. Excessive use of
this mechanism results in thrashing and generally hampers overall system performance, mainly because hard drives are far slower than RAM.

RAM disk
Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a RAM disk. A RAM disk loses
the stored data when the computer is shut down, unless memory is arranged to have a standby battery source.

Shadow RAM
Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter access times. The ROM chip is then
disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes
called shadowing, is fairly common in both computers and embedded systems.

As a common example, the BIOS in typical personal computers often has an option called “use shadow BIOS” or similar. When enabled, functions
that rely on data from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections).
Depending on the system, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be
inaccessible to the operating system if shadow RAM is used. On some systems the benefit may be hypothetical because the BIOS is not used after
booting in favor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs.[27]

Recent developments
Several new types of non-volatile RAM, which preserve data while powered down, are under development. The technologies used include carbon
nanotubes and approaches utilizing Tunnel magnetoresistance. Amongst the 1st generation MRAM, a 128 KiB (128 × 210 bytes) chip was
manufactured with 0.18 µm technology in the summer of 2003. In June 2004, Infineon Technologies unveiled a 16 MiB (16 × 220 bytes) prototype
again based on 0.18 µm technology. There are two 2nd generation techniques currently in development: thermal-assisted switching (TAS)[28] which
is being developed by Crocus Technology, and spin-transfer torque (STT) on which Crocus, Hynix, IBM, and several other companies are
working.[29] Nantero built a functioning carbon nanotube memory prototype 10 GiB (10 × 230 bytes) array in 2004. Whether some of these
technologies can eventually take significant market share from either DRAM, SRAM, or flash-memory technology, however, remains to be seen.

Since 2006, "solid-state drives" (based on flash memory) with capacities exceeding 256 gigabytes and performance far exceeding traditional disks
have become available. This development has started to blur the definition between traditional random-access memory and "disks", dramatically
reducing the difference in performance.

Some kinds of random-access memory, such as "EcoRAM", are specifically designed for server farms, where low power consumption is more
important than speed.[30]

Memory wall
The "memory wall" is the growing disparity of speed between CPU and memory outside the CPU chip. An important reason for this disparity is the
limited communication bandwidth beyond chip boundaries, which is also referred to as bandwidth wall. From 1986 to 2000, CPU speed improved at
an annual rate of 55% while memory speed only improved at 10%. Given these trends, it was expected that memory latency would become an
overwhelming bottleneck in computer performance.[31]

CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the
memory wall in some sense. Intel summarized these causes in a 2005 document.[32]

First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power
consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory
access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial
architectures are becoming less efficient as processors get faster (due to the so-called Von Neumann bottleneck), further undercutting
any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance
within solid state devices, resistance-capacitance (RC) delays in signal transmission are growing as feature sizes shrink, imposing an
additional bottleneck that frequency increases don't address.
The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"[33]
which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.

A different concept is the processor-memory performance gap, which can be addressed by 3D integrated circuits that reduce the distance between
the logic and memory aspects that are further apart in a 2D chip.[34] Memory subsystem design requires a focus on the gap, which is widening over
time.[35] The main method of bridging the gap is the use of caches; small amounts of high-speed memory that houses recent operations and
instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently.
Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on
evolving caching techniques.[36] These can prevent the loss of processor performance, as it takes less time to perform the computation it has been
initiated to complete.[37] There can be up to a 53% difference between the growth in speed of processor speeds and the lagging speed of main
memory access.[38]

Solid-state hard drives have continued to increase in speed, from ~400 Mbit/s via SATA3 in 2012 up to ~3 GB/s via NVMe/PCIe in 2018, closing
the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane DDR4 3200 capable of
25 GB/s, and modern GDDR even faster. Fast, cheap, non-volatile solid state drives have replaced some functions formerly performed by RAM,
such as holding certain data for immediate availability in server farms - 1 Terabyte of SSD storage can be had for $200, while 1TB of RAM would
cost thousands of dollars.[39][40]

Timeline

SRAM
 Static random-access memory (SRAM)
Date of Chip Capacity Access
SRAM type Manufacturer(s) Process MOSFET Ref
introduction name (bits) time
Bipolar
March 1963 N/A 1-bit ? Fairchild N/A N/A
(cell) [9]

? 8-bit ? Bipolar IBM ? N/A

1965 SP95 16-bit ? Bipolar IBM ? N/A [41]

? 64-bit ? MOSFET Fairchild ? PMOS [42]

Bipolar [8]
TMC3162 16-bit ? Transitron ? N/A
1966 (TTL)

? ? ? MOSFET NEC ? ? [43]

64-bit ? MOSFET Fairchild ? PMOS

[43]
1968 ? 144-bit ? MOSFET NEC ? NMOS

512-bit ? MOSFET IBM ? NMOS [42]

? 128-bit ? Bipolar IBM ? N/A [9]

1969
12,000 [44][45][46][47]
1101 256-bit 850 ns MOSFET Intel PMOS
nm

1972 2102 1 kb ? MOSFET Intel ? NMOS [44]

5101 1 kb 800 ns MOSFET Intel ? CMOS [44][48]

1974
NMOS [44][49]
2102A 1 kb 350 ns MOSFET Intel ?
(depletion)

1975 2114 4 kb 450 ns MOSFET Intel ? NMOS [44][48]

NMOS [44][45]
2115 1 kb 70 ns MOSFET Intel ?
(HMOS)
1976
NMOS [44][50]
2147 4 kb 55 ns MOSFET Intel ?
(HMOS)

1977 ? 4 kb ? MOSFET Toshiba ? CMOS [45]

CMOS [50]
HM6147 4 kb 55 ns MOSFET Hitachi 3,000 nm
1978 (twin-well)

TMS4016 16 kb ? MOSFET Texas Instruments ? NMOS [45]

16 kb ? MOSFET Hitachi, Toshiba

1980 ? ? CMOS [51]
64 kb ? MOSFET Matsushita

1981 ? 16 kb ? MOSFET Texas Instruments 2,500 nm NMOS [51]

Matsushita, [52]
October 1981 ? 4 kb 18 ns MOSFET 2,000 nm CMOS
Toshiba
NMOS [51]
1982 ? 64 kb ? MOSFET Intel 1,500 nm
(HMOS)

February 1983 ? 64 kb 50 ns MOSFET Mitsubishi ? CMOS [53]

1984 ? 256 kb ? MOSFET Toshiba 1,200 nm CMOS [51][46]

Sony, Hitachi,
1987 ? 1 Mb ? MOSFET Mitsubishi, ? CMOS [51]
Toshiba

December 1987 ? 256 kb 10 ns BiMOS Texas Instruments 800 nm BiCMOS [54]

15–23 NEC, Toshiba,

1990 ? 4 Mb MOSFET ?
ns Hitachi, Mitsubishi
CMOS [51]
12–15
1992 ? 16 Mb MOSFET Fujitsu, NEC 400 nm
ns
CMOS [55]
December 1994 ? 512 kb 2.5 ns MOSFET IBM ?
(SOI)
 1995 ? 4 Mb 6 ns Cache Hitachi 100 nm CMOS [56]
(SyncBurst)

256 Mb ? MOSFET Hyundai ? CMOS [57]

DRAM
 Dynamic random-access memory (DRAM)
Date of Capacity DRAM
Chip name Manufacturer(s) Process MOSFET Area Ref
introduction (bits) type
DRAM [16][17]
1965 N/A 1-bit Toshiba N/A N/A N/A
(cell)
DRAM [19][43]
1967 N/A 1-bit IBM N/A MOS N/A
(cell)
DRAM [8]
1968 ? 256-bit Fairchild ? PMOS ?
(IC)
DRAM [43]
1969 N/A 1-bit Intel N/A PMOS N/A
(cell)
DRAM [43]
1102 1 kb Intel, Honeywell ? PMOS ?
1970 (IC)

1103 1 kb DRAM Intel 8,000 nm PMOS 10 mm² [58][59][20]

μPD403 1 kb DRAM NEC ? NMOS ? [60]

1971
General [61]
? 2 kb DRAM ? PMOS 13 mm²
Instrument

1972 2107 4 kb DRAM Intel ? NMOS ? [44][62]

1973 ? 8 kb DRAM IBM ? PMOS 19 mm² [61]

1975 2116 16 kb DRAM Intel ? NMOS ? [63][8]

1977 ? 64 kb DRAM NTT ? NMOS 35 mm² [61]

MK4816 16 kb PSRAM Mostek ? NMOS ? [64]

1979
? 64 kb DRAM Siemens ? VMOS 25 mm² [61]

1,000–1,500 34– [61]

1980 ? 256 kb DRAM NEC, NTT NMOS
nm 42 mm²

1981 ? 288 kb DRAM IBM ? MOS 25 mm² [65]

64 kb DRAM Intel 1,500 nm CMOS 20 mm²

1983 ? [61]
256 kb DRAM NTT ? CMOS 31 mm²
January 5, [66][67]
? 8 Mb DRAM Hitachi ? MOS ?
1984
74– [61][68]
Hitachi, NEC 1,000 nm NMOS
February 76 mm²
? 1 Mb DRAM
1984
NTT 800 nm CMOS 53 mm² [61][68]

DPRAM Texas [69][70]

1984 TMS4161 64 kb ? NMOS ?
(VRAM) Instruments
January DPRAM [71][72]
μPD41264 258 kb NEC ? NMOS ?
1985 (VRAM)

June 1986 ? 1 Mb PSRAM Toshiba ? CMOS ? [73]

NEC 800 nm NMOS 99 mm²

1986 ? 4 Mb DRAM Texas [61]

100–
Instruments, 1,000 nm CMOS
137 mm²
Toshiba

1987 ? 16 Mb DRAM NTT 700 nm CMOS 148 mm² [61]

October [74]
? 512 kb HSDRAM IBM 1,000 nm CMOS 78 mm²
1988
Matsushita,
1991 ? 64 Mb DRAM Mitsubishi, 400 nm CMOS ?
[51]
Fujitsu, Toshiba
1993 ? 256 Mb DRAM Hitachi, NEC 250 nm CMOS ?
1995 ? 4 Mb DPRAM Hitachi ? CMOS ? [56]
 (VRAM)

January 9, NEC 250 nm CMOS ?

? 1 Gb DRAM [75][56]
1995 Hitachi 160 nm CMOS ?

1996 ? 4 Mb FRAM Samsung ? NMOS ? [76]

1997 ? 4 Gb QLC NEC 150 nm CMOS ? [51]

1998 ? 4 Gb DRAM Hyundai ? CMOS ? [57]

June 2001 TC51W3216XB 32 Mb PSRAM Toshiba ? CMOS ? [77]

February [51][78]
? 4 Gb DRAM Samsung 100 nm CMOS ?
2001

SDRAM
 Synchronous dynamic random-access memory (SDRAM)
Date of Capacity SDRAM
Chip name Manufacturer(s) Process MOSFET Area Ref
introduction (bits) type

1992 KM48SL2000 16 Mb SDR Samsung ? CMOS ? [79][22]

MSM5718C50 18 Mb RDRAM Oki ? CMOS 325 mm² [80]

1996 N64 RDRAM 36 Mb RDRAM NEC ? CMOS ? [81]

? 1 Gb SDR Mitsubishi 150 nm CMOS ? [51]

1997 ? 1 Gb SDR Hyundai ? SOI ? [57]

1998 MD5764802 64 Mb RDRAM Oki ? CMOS 325 mm² [80]

Direct [82]
March 1998 72 Mb RDRAM Rambus ? CMOS ?
RDRAM

June 1998 ? 64 Mb DDR Samsung ? CMOS ? [83][84][85]

64 Mb DDR Hyundai ? CMOS ? [57]

1998 ?
128 Mb SDR Samsung ? CMOS ? [86][84]

128 Mb DDR Samsung ? CMOS ? [84]

1999 ?
1 Gb DDR Samsung 140 nm CMOS ? [51]

2000 GS eDRAM 32 Mb eDRAM Sony, Toshiba 180 nm CMOS 279 mm² [87]

288 Mb RDRAM Hynix ? CMOS ? [88]

2001 ?
? DDR2 Samsung 100 nm CMOS ? [85][51]

2002 ? 256 Mb SDR Hynix ? CMOS ? [88]

EE+GS [87]
32 Mb eDRAM Sony, Toshiba 90 nm CMOS 86 mm²
eDRAM

72 Mb DDR3 Samsung 90 nm CMOS ? [89]

2003 [88]
Hynix ? CMOS ?
? 512 Mb DDR2
Elpida 110 nm CMOS ? [90]

1 Gb DDR2 Hynix ? CMOS ? [88]

2004 ? 2 Gb DDR2 Samsung 80 nm CMOS ? [91]

EE+GS [92]
32 Mb eDRAM Sony, Toshiba 65 nm CMOS 86 mm²
eDRAM

2005 Xenos [93]

80 Mb eDRAM NEC 90 nm CMOS ?
eDRAM

? 512 Mb DDR3 Samsung 80 nm CMOS ? [85][94]

2006 ? 1 Gb DDR2 Hynix 60 nm

CMOS ? [88]
2008 ? ? LPDDR2 Hynix ?
April 2008 ? 8 Gb DDR3 Samsung 50 nm CMOS ?
[95]
2008 ? 16 Gb DDR3 Samsung 50 nm CMOS ?
? DDR3 Hynix 44 nm
2009 ? CMOS ? [88]
2 Gb DDR3 Hynix 40 nm

16 Gb DDR3 Hynix 40 nm CMOS ? [96]

2011 ?
2 Gb DDR4 Hynix 30 nm CMOS ? [96]

2013 ? ? LPDDR4 Samsung 20 nm CMOS ? [96]

2014 ? 8 Gb LPDDR4 Samsung 20 nm CMOS ? [97]

2015 ? 12 Gb LPDDR4 Samsung 20 nm CMOS ? [86]

2018 ? 8 Gb LPDDR5 Samsung 10 nm FinFET ? [98]

 128 Gb DDR4 Samsung 10 nm FinFET ? [99]

SGRAM and HBM

Synchronous graphics random-access memory (SGRAM) and High Bandwidth Memory (HBM)
Date of Capacity SDRAM
Chip name Manufacturer(s) Process MOSFET Area Ref
introduction (bits) type
November SGRAM [100][101]
HM5283206 8 Mb Hitachi 350 nm CMOS 58 mm²
1994 (SDR)
December SGRAM [102][103]
µPD481850 8 Mb NEC ? CMOS 280 mm²
1994 (SDR)
SGRAM [104][105]
1997 µPD4811650 16 Mb NEC 350 nm CMOS 280 mm²
(SDR)
September SGRAM [83]
? 16 Mb Samsung ? CMOS ?
1998 (GDDR)
SGRAM [106]
1999 KM4132G112 32 Mb Samsung ? CMOS ?
(SDR)
SGRAM [107]
2002 ? 128 Mb Samsung ? CMOS ?
(GDDR2)
SGRAM
(GDDR2)
2003 ? 256 Mb Samsung ? CMOS ? [107]
SGRAM
(GDDR3)
SGRAM [108]
March 2005 K4D553238F 256 Mb Samsung ? CMOS 77 mm²
(GDDR)
October SGRAM [109]
? 256 Mb Samsung ? CMOS ?
2005 (GDDR4)
SGRAM
2005 ? 512 Mb Hynix ?
(GDDR4)
SGRAM [88]
2007 ? 1 Gb Hynix 60 nm CMOS ?
(GDDR5)
SGRAM
2009 ? 2 Gb Hynix 40 nm
(GDDR5)
SGRAM [110]
2010 K4W1G1646G 1 Gb Samsung ? CMOS 100 mm²
(GDDR3)
SGRAM
2012 ? 4 Gb
(GDDR3) SK Hynix ? CMOS ? [96]

2013 ? ? HBM
SGRAM [111]
March 2016 MT58K256M32JA 8 Gb Micron 20 nm CMOS 140 mm²
(GDDR5X)

June 2016 ? 32 Gb HBM2 Samsung 20 nm CMOS ? [112][113]

2017 ? 64 Gb HBM2 Samsung 20 nm CMOS ? [112]

January SGRAM [114][115][116]

K4ZAF325BM 16 Gb Samsung 10 nm FinFET ?
2018 (GDDR6)

See also
CAS latency (CL)
Hybrid Memory Cube
Multi-channel memory architecture
Registered/buffered memory
RAM parity
Memory Interconnect/RAM buses
Memory geometry
 Chip creep

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