My First Nios II for

Altera DE2i-150 Board

C7 Technology
1. Hardware Design
1.1. Required Features
The Nios II processor core is a soft-core central processing unit that you could program onto
an Altera field programmable gate array (FPGA). This tutorial illustrates you to the basic flow
covering hardware creation and software building. You are assumed to have the latest Quartus
II and NIOS II EDS software installed and quite familiar with the operation of Windows OS. If
you use a different Quartus II and NIOS II EDS version, there will have some small difference
during the operation. You are also be assumed to possess a DE2i-150 development board
(other kinds of dev. Board based on Altera FPGA chip also supported).
The example NIOS II standard hardware system provides the following necessary components:
Nios II processor core, that’s where the software will be executed
On-chip memory to store and run the software
JTAG link for communication between the host computer and target
hardware (typically using a USB-Blaster cable)
LED peripheral I/O (PIO), be used as indicators

1.2. Creation of Quartus Project

This section describes the flow of how to create a hardware system including SOPC feature.
The hardware to implement will be similar to the one depicted in Figure 1.

Figure 1 - Hardware to be implemented

 1.2.1. Follow the known steps to create a new project in Quartus Prime, by using New
Project Wizard:
Name the project ‘My_First_NiosII’.

Create an empty project.

Do not add any file at this point.
Select the EPC4CE115F29C7 device (FPGA in the DE2-115 board).

Leave the EDA Tools Settings options with their default configuration.
Click Finish.

1.3. Creation of Hardware System – Platform Designer

1.3.1. Open ‘Platform Designer’: Tools -> Platform Designer.

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 1.3.2. Go to ‘File -> Save As’

1.3.3. Save the system to be created as ‘DE2i_150_QSys’. Remember to save it into

the desired working directory.

1.3.4. Close the pop up window created by saving the new system.

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 1.3.5. Right click over the ‘clk_0’, and select ‘Rename’, to change the clock name to
‘clk_50’.

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 1.3.6. In the ‘IP Catalog’ pane select ‘Processors and Peripherals -> Embedded
Processor -> Nios II Processor’.

1.3.7. Double click or just click on the ‘Add’ button. The Nios II Processor configuration
window will come up. Select the ‘Nios II/e’ version. Then click ‘Finish’.

1.3.8. The Nios II processor will then be added to the system.

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 1.3.9. Rename the processor from ‘nios2_gen2_0’ to ‘nios2_qsys’.

1.3.10. Connect the clk, clk_in_reset and clk_reset between the clk_50 and the
nios2_qsys components as shown in the following figure. Connections are done
by clicking the hollow dots on the connection line. The dots become solid
indicating the ports are connected.

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 1.3.11. Now let’s add the JTAG UART module. In the IP Catalog pane, select Interface
Protocols -> Serial -> JTAG UART. Then double click to add it to the system (leave
the configuration values as per defect). Click Finish.

1.3.12. Rename jtag_uart_0 to jtag_uart.

1.3.13. Now, connect the jtag_uart clk to the clk signal, the reset to the clk_reset and
to the clk_in_reset. Likewise, connect avalon_jtag_slave to data_master.

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 1.3.14. Now, let’s add some memory, from the IP Catalog pane, select Basic Functions
-> On Chip Memory -> On Chip Memory (RAM or ROM). Double click to open the
configuration window. Modify the Total Memory Size to 20480 bytes. Click Finish.

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 1.3.15. Rename the memory from onchip_memory2_0 to onchip_memory2.

1.3.16. Connect clk, clk_reset, data_instruction and data_master as shown in the

following figure.

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 1.3.17. Save the system.

1.3.18. Click the nios2_qsys component. Then, on the right pane the configuration
options should come up. Select the Vectors tab. Update Reset Vector and
Exception Vector as shown in the following figure. Then click Finish.

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 1.3.19. From the IP Catalog, select Basic Functions -> Simulation; Debug and
Verification -> Debug and Performance ->System ID Peripheral. Click to open the
wizard of adding System ID.

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 1.3.20. In the configuration window for the System ID, leave the default values. Click
Finish.

1.3.21. Rename the sysid_qsys_0 peripheral to sysid_qsys. Then connect the clk,
clk_reset and data_master as shown in the following figure.

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 1.3.22. From the IP Catalog, select Processors and Peripherals-> Peripherals -> PIO
(Parallel I/O).

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 1.3.23. Click to open the wizard of adding PIO. Leave the default values. Click Finish.

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 1.3.24. Rename pio_0 to led. Then, connect clk, clk_reset and data_master as shown
in the following figure.

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 1.3.25. Click on the ‘external_connection’ connect. Then click on the ‘Double-click to
export’ in the Export column, and name it ‘led’.

1.3.26. Let’s also create an external connection for the reset input. In the clk_in_reset
row, click on the ‘Double-click to export’ in the Export column, and name it
‘reset’.’

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 1.3.27. At this point if we check the Address Map, there will be several errors marked
due to mainly overlapping addresses.

1.3.28. Do System -> Assign Base Addresses.

1.3.29. The tool will reassign the addresses in such a way that there will not be any
overlap. Cambiar figura, debe aparecer LED y no PIO

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 1.3.30. If you check the message log, there will be a warning regarding no interrupt
assigned to the JTAG module.

1.3.31. In the IRQ column, connect the IRQ31 to the JTAG irq, Interrupt Sender.

1.3.32. After assigning the interrupt, there should be not warnings in the message
window.

1.3.33. Save the system.

1.3.34. Go to Generate -> Generate HDL. In the pop up Generation window, select
VHDL as ‘Create HDL design files for Synthesis’. Then click Generate.

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 1.3.35. If there is no error in the generation, the window will show successful as shown
in the following figure.

1.3.36. Click Close. Then exit from the Platform Designer, File->Exit, to return to the
main Quartus window.

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 1.4. Create Hardware Complete Design in Quartus Prime
1.4.1. We are going to need to instantiate the hardware system created in Platform
Designer in a top VHDL file. Let’s first take a look at the VHDL instantiation
template created by Platform Designer. Go to the directory
<project_directory>/lab1/DE2i_150_QSys/ and open the file
DE2i_150_QSys_inst.vhd.

The template should look like the following piece of code.

1.4.2. Leave that template open. Now, create a new VHDL file by doing File -> New,
then select VHDL file.

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 1.4.3. Once the blank page shows up, save it as my_First_NiosII.vhd.

1.4.4. Type in the following piece of code (use the template previously open to write
the component declaration and the component instantiation).

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 1.4.5. Save it.

1.4.6. After saving the .vhd file, you will get an error message similar to the following:

This is to the fact that the component DE2i_150Qsys is not still part of the project.
It is necessary to add it.

1.4.7. To add a file to a project it can be done by selecting Files in the Project
Navigator pane. Then right click over the Files icon and select Add/Remove Files
in Project.

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 The other way is to do Project -> Add/Remove Files in Project.

Add the file DE2i_150_Qsys.qsys.

1.4.8. Click OK.

1.4.9. The two files should be now in the Files option.

1.4.10. Configure the My_First_NioII.vhd file as Top-Level entity, by right click on the
file name and click on the Set as Top-Level Entity option.

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 1.4.11. Now, it’s necessary now to compile the whole project. Do Processing -> Start
Compilation, or click the icon.

1.4.12. Next step, we will assign the I/O pins. Do Assignments -> Pin Planner. Make the
assignments according to the following table (the I/O pins information is detailed
in the DE2-115 User Manual document).

1.4.13. Close Pin Planner.

1.4.14. Recompile.

1.5. Download Hardware into the FPGA

1.5.1. Connect the board to the host computer via the USB download cable.

1.5.2. Apply power to the board.

1.5.3. Use the Quartus Programmer tool, Tools->Programmer, to download the

configuration file, My_First_NiosII.sof, to the FPGA.

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2. NIOS II Software Build Tools (SFT) for Eclipse
The Nios II Software Build Tools (SBT) for Eclipse is an easy-to-use graphical user
interface that automates build and makefile management. The Nios II SBT integrates
a text editor, debugger, a BSP editor, a Nios II flash programmer and a Quartus II
Programmer. It also offers several software application templates to facilitate to get
started quickly. In this part of the lab you will use the Nios II SBT for Eclipse to compile
a simple ‘C’ program to run on the Nios II processor that resides in the FPGA of the
DE2-115 board. You will create a new software project, build it, and run it on the target
hardware. You will also edit the project, re-build it, and set up a debug session.
2.1. Open the NiosII SBT for Eclipse.

2.2. Select a workspace for your software project.

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 2.3. Do File->New->NIOS II Aplications and BSP from Template. The New Project Wizard
window will come up.

2.4. In the New Project wizard, make sure the following configurations:
2.4.1. Under Target hardware information, next to SOPC Information File name,
browse to locate the <design files directory> where the previously created
hardware project resides.

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 Select DE2i_150_QSys.sopcinf and click Open. You will return to the Nios II
Application and BSP from Template wizard showing current information for the
SOPC Information File name and CPU name fields.
2.4.2. Select the Hello World project template.
2.4.3. Give the project a name: My_First_NiosII.

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 2.4.4. Click Next.

2.4.5. Leave the default location and BSP project.

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 2.4.6. Click Finish.

2.5. When getting back to the main window, there are now two new project created
shown in the Project Explorer pane.

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 2.5.1. My_First_NiosII (hello_world_0 is default name) is your C/C++ application
project. This project contains the source and header files for your application.
2.5.2. My_First_NiosII_bsp (hello_world_0_bsp is default name) is a board support
package that encapsulates the details of the Nios II system hardware.

Note: When you build the system library for the first time the NIOS II SBT for
Eclipse automatically generates files useful for software development, including:
 Installed IP device drivers, including SOPC component device drivers for
the NIOS II hardware system.
 Newlib C library, which is a richly featured C library for the NIOS II
processor.
 NIOS software packages which includes NIOS II hardware abstraction
layer, NicheStack TCP/IP Network stack, NIOS II host file system, NIOS II
read-only zip file system and Micrium’s μC/OS-II real time operating
system(RTOS).
 system.h, which is a header file that encapsulates your hardware system.
 alt_sys_init.c, which is an initialization file that initializes the devices in
the system

2.6. Double click on the ‘hello_world.c’ file. To just take a look at the ‘C’ code for the
example.

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 2.7. Once the project has been created the following step is to build the project. Right-
click on the My_First_NiosII, and select Build Project. The project will be compiled.

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 2.8. A Building Project window will come up stating that the project is being built.

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 2.9. When compilation completes, a message will appear on the Console pane.

2.10. Now the whole system just created is ready to be downloaded to the board. At
this point be sure you have already configured the FPGA with the configuration file as
it was explained in 1-5.

If you have not download the configuration file from Quartus Prime environment, you
still can do it from the SBT console by doing Nios II -> Quartus Prime Programmer.

2.11. To download the program to the FPGA and immediately execute it, right-click
the My_First_NiosII project, select Run As, and then select Nios II Hardware.

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 2.12. Then the program, ‘C’ code is executed, and in the Nios II SBT Console tab,
bottom pane, the message “Hello from Nios II !” should appear.

3. Editing and Re-Building the Application

After finishing previous steps, we will perform other tasks inside the SBT environment
such as configuring the system properties, editing and re-building the application, in
order to get familiar with more advanced features.

3.1. Re-write the hello_word.c file with the following ‘C’ code.

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 3.2. Save the modification.

In case you get an error message regarding LED_BASE, it means that the symbolic
name for the LED address base is other than LED_BASE.

Open the system.h file (which functionality is explained in 3.4), and do a search for LED
and find the mnemonic for LED BASE.

3.3. There is no need to build the project again before downloading it to the board, since
that task, re-build the project, is done automatically when we select run the Nios II in
hardware. Hence, do right-click in My_First_NiosII Project, then Run->Run As -> Nios
II Hardware.

If you have power off the board before starting step 3, you should configure the FPGA
again before run the ‘C’ code in hardware

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 3.4. Let’s analyze the ‘C’ code to understand why the LEDs are blinking

3.4.1. Line 2 of the hello_word.c code, include the system.h header file. This file
contains a lot of definitions of the Nios II hardware system just created. Among
them are the mnemonics, memory locations, base addresses, settings for the
hardware components, etc. Let’s open the system.h file, underneath the
My_Fisrt_NiosII_bsp folder, to take a look at it.

3.4.2. If you remember, when we create the hardware system in Platform Designer,
we add to the system a peripheral, pio_0, that we named led, step 1.3.23 and
followings. The Nios II processor controls the PIO ports, in this case LEDs port, by
reading and writing to a specific memory location. The memory locations was set
by Platform Designer, step 1.3.29. Any PIO peripheral has four registers: data,
direction, interrupt mask, and edge capture. To turn the LEDs on and off, we will
write the data register from the ‘C’ code.

3.4.3. On the other hand, line 3 of the ‘C’ code include the header file
altera_avalon_pio_regs.h. This file is located in

G:\intelFPGA_lite\17.1\ip\altera\sopc_builder_ip\altera_avalon_pio\inc

The altera_avalon_pio_regs.h file has several definitions that used along with
read and write functions defined in the io.h file to easily have access to the low
level hardware from the Nios II processor. The most important functions are:

By using these functions it is possible to read and write the PIO data register. In
this exercise we will write this register to turn on (write ‘1’) and off (write ‘0’) the
LEDs associated to this memory registers.

Intel-Altera provides different documents on the functions and resources

available for designs based in Nios II processor. The two most important
documents are:
Nios II Processor Reference guide:
https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf

Nios II Gen2 Software Developer’s Handbook:

https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf

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4. Use of the DEBUG tool
The SDT comes with a debug tool to have access to the most common debug tasks, such
as breakpoints, execute the program step by step, analyze variable’s values, etc..

4.1. To use the debug tool it is necessary to change the perspective of the tool to ‘NiosII
Debug’. Do Run -> Debug to open the Debug perspective.

4.2. To place a breakpoint in a specific statement, just place the cursor on the left side of
the line number, and do a double-click, a light-blue circle should show up.

4.3. The ‘C’ code variables are visible in the ‘Variables’ tab (upper right side).

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 4.4. The breakpoints that have been set can be seen in the Breakpoint tab.

4.5. To debug the ‘C’ code there are multiple options, which are displayed in the following
figures.

5. BSP Editor – Useful modifications

There are some advanced configurations of the way to generate the BSP for the
current project. We will learn in this step how to configure some advanced options
about the target memory for instance, as well as another options.

5.1. Right-click on the My_Fisrt_NiosII_bsp, and the select NiosII->BSP Editor.

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 5.2. In the BSP Editor window, the Main page contains setting related to how the program
interacts with the underlying hardware. The settings have names that correspond to
the targeted Nios II hardware.

5.3. In the Linker Script tab, observe which memory has been assigned for Program
memory (.text), Read-Only data memory (.rodata), Read/Write data memory
(.rwdata), Heap memory, and Stack memory.

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 The setting in this window determine which memory is used to store the compiled
executable program when the project My_Fisrt_NiosII program runs. Here, it is also
possible to specify which interface will be used for stdio, stdin, and sterr.

5.4. You can use the memory options in the Linker Script box to change the memory target
when you have more than one option.

5.5. Click Exit to get out of the BSP Editor and return to the SDT main window.

5.6. Rerun the project.

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