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Delay-Locked Loops: All-Digital DLL and Low-Power DLL

Presentation · April 2016

DOI: 10.13140/RG.2.1.3407.1282

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Delay-Locked Loops
5. All-Digital DLL and
Low-Power DLL
Woorham Bae
[email protected]

Dept. of Electrical Engineering and Computer Science

Seoul National Univ.
 All-Digital DLL

• All components provide digital interface only

• Suitable for deep-submicron technology using low supply

• PVT variation can be mitigated

• Less sensitive to gate leakage

• Fast locking

• Storing locking information during power down mode

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 Digital Phase Detector - 1

• Binary phase detector

• Simple but highly nonlinear Vavg

p
CK A D Q Out -p ΔΦ

CK B

CK A

CK B

Out

A lead B lead
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 Digital Phase Detector - 2

• Linear: Time-to-digital converter (TDC)

• Conventional TDC: delay chain and samplers

• Resolution: Intrinsic gate delay

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 Digital Phase Detector - 3

• Vernier TDC

• Fine resolution but large area, high power consumption

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 Digital Phase Detector - 4

• Interpolative TDC

• Fine resolution using phase interpolation

[Henzler, JSSC’08]

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 Digital Phase Detector - 5

• Ring oscillator-based TDC

• Wide dynamic range, large power consumption by oscillator

[Yu, JSSC’10]
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 Digital Delay Element Examples

• Current-starved inverter

• Multiplexer-based delay

• Lattice delay line

• Synchronous mirror delay

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 Current-Starved Inverter

• Digitally controlled current-starved inverter

• Fine resolution

• Dynamic range and intrinsic delay depend

on clock frequency

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 Multiplexer-Based Delay

• Most straightforward

• Tunable delay range increases by cascading the delay units,

but the intrinsic delay increases as well

in
td MUX out

sel

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 Multiplexer-Based Delay

• Multiplexer-based delay element and current-starved delay

element are combined

[Wang, JSSC’06] 11
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 Lattice Delay Unit

• Intrinsic delay of two NAND delay

• Delay step of two NAND delay

• Dummy NAND for fan-out balancing

[Yang, JSSC’07]

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 Lattice Delay Line

• Intrinsic delay of two NAND delay

• As the operating frequency increases, the number of activated

delay units is reduced and the power remains the same

• Breaking dependency between total delay stages and power

[Yang, JSSC’07]

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 Lattice Delay Line

• Glitch issue

• Switching of S1 results in two different paths that generates an

output glitch

[Caro, TVLSI’13]

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 Modified Lattice Delay Line

• Dual lattice delay line followed by fine phase mixer

[Lee, JSSC’12]
MDCDL

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 Modified Lattice Delay Line

• Dual lattice delay line followed by fine phase mixer

• Seamless operation between coarse and fine delay line

• Power saving by shared delay line

[Lee, JSSC’12]
Fine mixer

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Synchronous Mirror Delay

[Sung,
JSSC’04]

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 Synchronous Mirror Delay

• Forward delay array (FDA) measures timing information of lock

• Backward delay array (BDA) with a mirror control circuit (MCC)

• Clock pulse is propagated backward through BDA as it is

propagated forward through FDA

• Total delay is two clock cycle: clock skew is suppressed in two

clock cycle

• Device mismatch and dynamic noise make the skew between

the clocks

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 DLL Architecture - 1

• Register-controlled DLL

• Only one bit of the shift register is active to select a point of

entry of the delay line

• Wider range achieved by adding more delay stages: large area

[Dehng, JSSC’00] 19
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 DLL Architecture - 2

• Counter-controlled DLL

• Binary-weighted delay line

• 64-bit shift register in a RDLL can be replaced by 6-bit counter

• Long lock time: 32 clock periods for 6-bit counter

[Dehng, JSSC’00] 20
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 DLL Architecture - 3

• SAR-controlled DLL

• 6 clock periods for 6-bit binary-weighted delay line

[Dehng, JSSC’00] 21
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 Low Power with Open-Loop Mode

• Once DLL is locked, the feedback loop is opened by LCU

• If any phase error is detected, PEC block sends a closed-loop

request to LCU

[Mesgarzadeh, JSSC’09] 22 2015

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Phase-Error Compensation Block

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 DLL with Low Supply

• Delay time mismatch due to the threshold voltage mismatch

• Unequal phase spacing

[Chang, JSSC’09]

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 DLL with Low Supply

• Mismatch becomes severe with low supply voltage

• Mismatch calibration circuit required

[Choi, ISSCC’15]

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 Mismatch Calibration Example

• Multiple DLLs

• Area overhead

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 Mismatch Calibration Example

• Code Density Test

• Asynchronous clock required

[Baronti, JSSC’04]

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 References
[1] Henzler, Stephan, et al. "A local passive time interpolation concept for variation-tolerant high-
resolution time-to-digital conversion." IEEE Journal of Solid-State Circuits 43.7 (2008): 1666-1676.
[2] Yu, Jianjun, Fa Foster Dai, and Richard C. Jaeger. "A 12-bit vernier ring time-to-digital converter in
0.13 CMOS technology." IEEE journal of solid-state circuits 45.4 (2010): 830-842.
[3] Wang, You-Jen, Shao-Ku Kao, and Shen-Iuan Liu. "All-digital delay-locked loop/pulsewidth-control
loop with adjustable duty cycles." IEEE Journal of Solid-State Circuits 41.6 (2006): 1262-1274.
[4] Yang, Rong-Jyi, and Shen-Iuan Liu. "A 40–550 MHz harmonic-free all-digital delay-locked loop
using a variable SAR algorithm." IEEE Journal of Solid-State Circuits 42.2 (2007): 361-373.
[5] De Caro, Davide. "Glitch-free NAND-based digitally controlled delay-lines."IEEE Transactions on
Very Large Scale Integration (VLSI) Systems 21.1 (2013): 55-66.
[6] Lee, Hyun-Woo, et al. "A 1.0-ns/1.0-V delay-locked loop with racing mode and countered CAS
latency controller for DRAM interfaces." IEEE Journal of Solid-State Circuits 47.6 (2012): 1436-1447.
[7] Sung, Kihyuk, and Lee-Sup Kim. "A high-resolution synchronous mirror delay using successive
approximation register." IEEE journal of solid-state circuits39.11 (2004): 1997-2004.
[8] Dehng, Guang-Kaai, et al. "Clock-deskew buffer using a SAR-controlled delay-locked loop." IEEE
Journal of Solid-State Circuits 35.8 (2000): 1128-1136.
[9] Mesgarzadeh, Behzad, and Atila Alvandpour. "A low-power digital DLL-based clock generator in
open-loop mode." IEEE Journal of Solid-State Circuits44.7 (2009): 1907-1913.
[10] Choi, Woo-Seok, et al. "3.8 A 0.45-to-0.7 V 1-to-6Gb/S 0.29-to-0.58 pJ/b source-synchronous
transceiver using automatic phase calibration in 65nm CMOS." 2015 IEEE International Solid-State
Circuits Conference-(ISSCC) Digest of Technical Papers. IEEE, 2015.
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