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Synthesis

ASIC VLSI synthesis flow

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madhusudhan n madhu
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37 views24 pages

Synthesis

ASIC VLSI synthesis flow

Uploaded by

madhusudhan n madhu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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SYNTHESIS

What is synthesis ?
 Synthesis is a process of converting one representation of a circuit (source representation) to another functionally
equivalent representation (target representation).
 Normally the target is less abstract (close to device level) than the source – Synthesis done across several levels
 Synthesis done across several levels

Synthesis = Translation + Logic optimization + Gate mapping transformation


WHY DO WE NEED SYNTHESIS ?
 To convert abstract level idea (Idea modeled in terms of coding) into actual electronic logic
gates behavior.

 With the help actual logic gates we can manufacture a chip.


LOGIC SYNTHESIS
TRANSLATION
Converts HDL to functional Boolean equivalent

 HDL syntax/rule checks


 Optimizes HDL
 Arithmetic function mapping
 Sequential function mapping
 Combinational function mapping
MAPPING/OPTIMIZATION
 Maps Boolean functions to technology specific primitive functions

 Modifies mapping to meet design goals

 Design Rules
 Timing
 Area
 Power
WHERE DOES SYNTHESIS FITS IN ASIC FLOW?
SYNTHESIS FLOW
LIBRARIES USED IN SYNTHESIS
There are 5 libraries in the design compiler
 Target library
 Link library
 Symbol library
 Synthetic library
 Design library
OVERVIEW OF LIBRARIES IN THE SYNTHESIS
ENVIRONMENT
Target_library:
Describes the cells you are mapping to(.Db file)
Link_library
Describes cells you have instantiated and any wire load or operating condition models you are
using(.Db file)
Symbol_library
Contains symbols(.Sdb file)for the gui's schematic viewer
Synthetic_library
Contains symbols(.Sldb file) to implement math function
Design_lib
Holds intermediate format descriptions for your HDL code for design reuse
DESIGN WARE (DW) COMPONENTS
 Synthesis tools provide library of highly optimized designs for arithmetic building
blocks
 Design ware library include high speed adder and multipliers
Tools automatically determine which DW components to use
 User can also specify which DW implementation to use for a particular design
WIRELOAD MODEL

Why do you need wire load model ???


WIRE LOAD MODEL
A wire load model is an estimate of a net ‘s parasitics based on the net’s
fanout
 Model is created by your vendor
 Estimates are based on statistics from other designs the vendor has fabricated using
their process
RTL HARDWARE INFERENCE - IF STATEMENTS AND
LATCHES
 Vhdl/verilog language definition requires signals to maintain their old value unless a new
value is assigned

 To infer latches ,use if statement without an else clause

 Latches implement this requirement in hardware


MULTIPLEXER INFERENCE
BASIC LATCHES & FLIPFLOP
BASIC LATCHES & FLIPFLOPS
BASIC LATCHES & FLIPFLOPS
ASSIGNING MULTIPLE THREESTATE
DRIVERS TO A SINGLE VARIABLE
EFFECTS OF CODING STYLE - IFELSE
STATEMENTS

How to recode this example so that multiplexing hardware was before adder?
UNDERSTANDING IF ELSE STATEMENTS
EFFICIENT CODING TIPS RESOURCE
SHARING
Minimum use of operators should be made
Each operator that is used contributes Towards hardware
QUALITY OF RTL
 Coding style impacts the synthesis QoR

 Same functionality coded in two different ways will yield different results

 Synthesis tool can not fix the major coding related issues to meet timing

 “Think Hardware” before you code so that tool provides best results
FALSE PATH EXAMPLE FOR REFERENCE

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