Technology

compuTer
Aided design
Simulation for VLSI MOSFET

Edited by
Chandan Kumar Sarkar
TECHNOLOGY
COMPUTER
AIDED DESIGN
Simulation for VLSI MOSFET
TECHNOLOGY
COMPUTER
AIDED DESIGN
Simulation for VLSI MOSFET

Edited by
Chandan Kumar Sarkar

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To our family members
Contents

Preface.......................................................................................................................ix
The Editor.............................................................................................................. xiii
Contributors............................................................................................................xv

1 Introduction to Technology Computer Aided Design............................. 1

Samar K. Saha

2 Basic Semiconductor and Metal-Oxide-Semiconductor (MOS)

Physics.............................................................................................................. 45
Swapnadip De

3 Review of Numerical Methods for Technology Computer Aided

Design (TCAD)............................................................................................ 145
Kalyan Koley

4 Device Simulation Using ISE-TCAD...................................................... 155

N. Mohankumar

5 Device Simulation Using Silvaco ATLAS Tool..................................... 187

Angsuman Sarkar

6 Study of Deep Sub-Micron VLSI MOSFETs through TCAD............ 237

Srabanti Pandit

7 MOSFET Characterization for VLSI Circuit Simulation.................... 267

Soumya Pandit

8 Process Simulation of a MOSFET Using TSUPREM-4 and Medici..... 363

Atanu Kundu

vii
Preface

In the era of System-on-Chip (SoC) fabricated with ultra-deep sub-micron

complementary metal-oxide-semiconductor (CMOS) technology, the semi-
conductor industry has to keep pace with the increased performance-capacity
demands from consumers. The current sub-90 nm CMOS technology poses
several critical challenges to very large scale integrated (VLSI) circuit and
device designers regarding the characteristic behavior and performance of
MOS transistors. In addition, there is huge pressure on the designers for
reduction of the design time for economic reasons. To cope with issues like
design productivity gap and yield drop and also to ensure correct behav-
ior of each device, there is a need to involve computer aided design (CAD)
methodologies and design automation tools. Technology computer aided
design (TCAD) is an electronic design automation (EDA) tool that models
the semiconductor device operation and fabrication based on fundamental
physics through the computer aided simulations for design and optimiza-
tion of semiconductor processing technologies and devices. Research and
development (R&D) cost and time for electronic product development can be
reduced by taking advantage of TCAD tools, thus making TCAD indispens-
able for modern VLSI devices and process technologies. TCAD simulation
is gaining importance because it is prohibitively expensive for academia as
well as for the several fab-less design industries to use silicon prototype for
design verification.
The motivation for editing this volume on TCAD simulation of VLSI
MOSFET came about when I was looking for student-level reference materi-
als on TCAD simulation tools while teaching courses for postgraduate and
senior undergraduate students. However, I could not find an appropriate
book and was thus compelled to teach the course by consulting various user
guides and manuals supplied with TCAD software and some semiconduc-
tor device textbooks. However, none of these caters to the intended purpose
of introducing the physics of TCAD simulations to the students. Therefore, I
found that there is a need for a book to provide the most up-to-date and com-
prehensive source of TCAD simulation of VLSI MOSFETs with an emphasis
on the fundamental theory and the underlying physics.
This book is intended for senior undergraduate and postgraduate students
of electrical and electronics engineering disciplines and for researchers and
professionals working in the area of electronic devices. The purpose of the
present edited volume is to rapidly disseminate to them the fundamental con-
cepts and underlying physics of TCAD simulation of MOSFETs. The objec-
tives of this book are to introduce the advantages of TCAD simulations for
device and process technology characterization, to introduce the fundamen-
tal physics and mathematics involved with TCAD tools, to expose readers

ix
x Preface

to two of the most popular commercial TCAD simulation tools, Silvaco and
Sentaurus, to characterize performances of VLSI MOSFETs through TCAD
tools, and to familiarize readers with compact modeling for VLSI circuit sim-
ulation. This volume provides the reader with comprehensive information
and a systematic approach to the design, characterization, fabrication, and
computation of VLSI MOS transistors through TCAD tools.
The chapters contain different levels of difficulty. Several example pro-
grams are supplied for illustration of the software tools and related physics.
The book therefore provides a desirable balance between the basic concepts,
equations, physics, and recent technologies of MOS transistors through
TCAD simulation. The book is organized into eight chapters that encompass
the field of TCAD simulation for VLSI MOSFET.
Chapter 1 provides an overview of the role, need, and advantages of
TCAD tools in design, characterization, and fabrication of VLSI MOS tran-
sistors. The evolution of modern TCAD and its challenges are also provided.
Chapter 2 reviews and analyzes the basic concepts and physics involved with
nanoscale MOS transistors. The physical approach to the tools is described
by basics of band theory, Poisson’s equation, continuity equation, drift dif-
fusion (DD), and hydrodynamic models. The physics of the scattering
mechanisms and different mobility models used in TCAD simulations are
discussed. Chapter 3 describes the basics and importance of numerical solu-
tion techniques applicable to TCAD. The numerical solution of the DD equa-
tions coupled with Poisson’s equation and its application to semiconductor
device modeling is described. Chapter 4 provides a detailed overview of the
two-dimensional/three-dimensional (2D/3D) device simulator Synopsys
Sentaurus TCAD. The various tools involved are introduced in a compre-
hensive manner. The different software-related aspects of this tool for device
simulations are described. Complete design examples explaining step by
step the construction, simulation, and performance extraction of MOS tran-
sistors are provided. Chapter 5 attempts to present the MOSFET simulation
using Silvaco TCAD tools. From basic syntax to choice of a complex model
is presented in this chapter with emphasis on the usage of the SILVACO
simulation software. An overview of the software developed by Silvaco to
meet simulation needs of researching conventional and advanced MOSFET
structures is also presented. The discussion is presented with examples to
perform simulations of different types of MOSFETs. Chapter 6 discusses
in detail the physics of nanoscale MOS transistors through TCAD simula-
tions. The various short channel effects involved with nanoscale MOS tran-
sistors are demonstrated through actual TCAD simulation results. Different
technology aspects and engineering techniques for future MOSFETs are
also introduced. Chapter 7 presents a comprehensive overview of compact
modeling of MOS transistors for use in VLSI circuit simulation. The math-
ematical models for characterizing various ultra-deep sub-micron effects of
sub-65 nm MOS transistors are introduced. The effects are demonstrated
through actual simulation program with integrated circuit emphasis (SPICE)
Preface xi

simulation results using industry standard compact models. The various cir-
cuit performances of MOS transistors are discussed. Chapter 8 addresses
process simulation of MOSFET using TSUPREM-4. The chapter is devoted to
bringing the key fabrication issues and their implementation in TCAD pro-
cess simulation tool TSUPREM-4. It also considers how the output of process
simulator TSUPREM-4 can be linked to device simulator MEDICI in order to
analyze the performance of the fabricated device. An extensive list of refer-
ences is provided at the end of each chapter for more elaborate discussion of
the issues and to motivate readers to engage in further research.
I wish to congratulate all contributors and their peers. Their convictions
and efforts were key to the success of this enterprise. The compilation of
this book would not have been possible without the dedication and efforts
of all the contributing authors. Special thanks go to Gagandeep Singh and
Laurie Schlags and staff members of CRC Press for their responsiveness
and immense patience demonstrated throughout the publishing process of
this book.

C.K. Sarkar
The Editor

Chandan Kumar Sarkar is Professor of Electronics and Telecommunication

at Jadavpur University, Calcutta, India. He received B.Sc. (Hons.) and
M.Sc. degrees in Physics from Aligarh Muslim University, Aligarh, India,
in 1975, was awarded a Ph.D. degree in Radio Physics from Calcutta
University in 1979, and was awarded the D.Phil. degree from Oxford
University, Oxford, United Kingdom, in 1984. He has been teaching for
over 22 years.
In 1980, Sarkar received the British Royal Commission Fellowship to work
at Oxford University. He worked as a visiting scientist at the Max Planck
Laboratory in Stuttgart, Germany, as well as at Linko Pink University in
Sweden. Sarkar also taught in the Department of Physics at Oxford University,
and was a distinguished lecturer of the IEEE EDS.
Sarkar has served as a senior member of IEEE and was chair of the IEEE EDS
chapter, Calcutta Section, India. He served as Fellow of IETE, Fellow of IE,
Fellow of WBAST, and member of the Institute of Physics, United Kingdom.
His research interests include semiconductor materials and devices, VLSI
devices, and nanotechnology. Sarkar has published and presented more
than 300 research papers in international journals and conferences and also
mentored 21 Ph.D.s.

xiii
Contributors

Swapnadip De Soumya Pandit

Electronics and Communication Institute of Radio Physics and
Engineering Department Electronics
Meghnad Saha Institute of University College of Science and
Technology Technology
Kolkata, India University of Calcutta
Kolkata, India

Kalyan Koley Srabanti Pandit

Electronics and Telecommunication Electronics and Telecommunication
Engineering Department Engineering Department
Jadavpur University Jadavpur University
Kolkata, India Kolkata, India
Samar K. Saha
Compact Modeling
Atanu Kundu
SuVolta, Inc.
Electronics and Communication
Los Gatos, California
Engineering Department
and
Heritage Institute of Technology
Electrical Engineering Department
Kolkata, India
Santa Clara University
Santa Clara, California

N. Mohankumar Angsuman Sarkar

Electronics and Communication Electronics and Communication
Engineering Department Engineering Department
SKP Engineering College Kalyani Government Engineering
Tiruvannamalai, Tamil Nadu, College
India Kalyani, India

xv
1
Introduction to Technology
Computer Aided Design

Samar K. Saha

CONTENTS
1.1 Technology Computer Aided Design (TCAD)........................................... 1
1.1.1 Process CAD........................................................................................3
1.1.2 Device CAD.........................................................................................4
1.2 A Brief History of TCAD............................................................................... 5
1.2.1 History of Device CAD......................................................................5
1.2.2 History of Process CAD.....................................................................9
1.3 Motivation for TCAD................................................................................... 10
1.3.1 Motivation for Device CAD............................................................. 10
1.3.2 Motivation for Process CAD........................................................... 12
1.4 TCAD Flow for IC Process and Device Simulation................................. 15
1.4.1 Generation of Simulation Structure............................................... 15
1.4.2 Verification of the Robustness of Simulation Structure.............. 16
1.4.3 Calibration of Physical Models....................................................... 18
1.4.4 Coupled Process and Device Simulation Flow.............................22
1.5 TCAD Application........................................................................................ 23
1.5.1 TCAD in Device Research............................................................... 23
1.5.1.1 Double-Halo MOSFET Devices........................................ 24
1.5.1.2 Sub-90 nm Split-Gate Flash Memory Cells.................... 27
1.5.2 TCAD in Fabrication Technology Development (TD)................. 32
1.6 Benefit of TCAD in TD Projects.................................................................. 35
1.7 Summary........................................................................................................ 36
References................................................................................................................ 37

1.1  Technology Computer Aided Design (TCAD)

Technology computer aided design (CAD), commonly known as technology
CAD or TCAD, is the electronic design automation that models integrated
circuit (IC) fabrication and device operation. TCAD is the art of abstract-
ing IC electrical behavior by critical analysis and detailed understanding

1
2 Technology Computer Aided Design: Simulation for VLSI MOSFET

of process, device, and circuit simulation data. In general, TCAD includes

lithography modeling to simulate the imaging of the mask by the lithography
equipment, photoresist characteristics, and processing; front end process mod-
eling for simulating the physical effects of manufacturing steps used to build
transistors up to metallization; device modeling using hierarchy of physically
based models for the operational description of active devices; compact mod-
eling for active, passive, and parasitic circuit components; interconnect model-
ing to analyze the operational response of back-end architectures; reliability
modeling for simulating the reliability and related effects on process, device,
and circuit levels; equipment modeling for simulating the local influence of the
equipment on each point of the wafer, especially in deposition, etching, and
chemical-mechanical polishing (CMP) processes; package simulation for elec-
trical, mechanical, and thermal modeling of chip packages; materials model-
ing to predict the physical and electrical properties of materials; modeling for
design robustness, manufacturing, and yield to simulate the impact of process
variability and dopant fluctuations on IC performance and determine design
specifications for manufacturability and yield of ICs; and numerical techniques
including grid generators, surface-advancement techniques, solvers for sys-
tems of partial differential equations (PDEs), and optimization routines [1,2].
TCAD offers capabilities to analyze how structural factors such as the
geometry and processes conditions influence the electrical behavior of
devices and circuits. Simulation data help in quantifying the details of the
behavioral models for ICs at the transistor and circuit levels and show physi-
cal limitations at the processing and manufacturing levels [3,4]. By reverse
modeling, the extended TCAD tools can be used to develop IC fabrication
technology from product concept (i.e., from the product specification to IC
fabrication technology as shown in Figure 1.1) [1]. The extended TCAD tools
can also be used to assess the manufacturability of IC fabrication processes
as shown in Figure 1.2 [1,5].

Generate Generate Generate

Process Recipes Process Profiles Device Models
3 2 1

Process Process Device Device Circuit

Simulation Profiles Simulation Models Simulation

Process Product
Specifications Specifications

FIGURE 1.1
Extended TCAD use to generate product-specific IC process recipe by reverse modeling; in
this approach, the sequential steps 1, 2, and 3 represent use of circuit, device, and process
CAD, respectively. (From S.K. Saha, Managing technology CAD for competitive advantage: An
efficient approach for integrated circuit fabrication technology development, IEEE Trans. Eng.
Manage., vol. 46, no. 2, pp. 221–229, May 1999. With permission.)
Introduction to Technology Computer Aided Design 3

Optimized
Process

No. of Simulation Experiment

Process Control Distribution

Create
Process Flow Parameter Selection
using Monte Carlo, or Response
Surface, or Neural Network Method

Model Process Simulation

Calibration
Database Device/Interconnect Simulation

Compact Model Parameter Extraction

Reliability/Circuit Simulation
Optimization

Manufacturability:
Process

No
Performance Check ?
Objectives
Yes
Manufacturing

FIGURE 1.2
Flowchart showing the use of extended TCAD to evaluate the manufacturability of IC fabrica-
tion technology with respect to the target specifications. (From S.K. Saha, Managing technol-
ogy CAD for competitive advantage: An efficient approach for integrated circuit fabrication
technology development, IEEE Trans. Eng. Manage., vol. 46, no. 2, pp. 221–229, May 1999. With
permission.)

In the microelectronics industry, TCAD is widely referred to as front-end

process modeling or process CAD and device modeling or device CAD. Therefore,
unless otherwise specified, hereafter in this chapter TCAD refers to IC front-
end process CAD and device CAD only.

1.1.1  Process CAD

Process CAD refers to front-end process modeling that includes the numeri-
cal simulation of the physical effects of IC processing steps used to fabri-
cate transistors up to metallization. The process CAD is used to simulate the
semiconductor processing steps such as oxidation and diffusion, deposition
4 Technology Computer Aided Design: Simulation for VLSI MOSFET

Structure: Mask. Physical change: Oxide, Epitaxy, Gate.

Process steps: Input Output Chemical/electrical change:
Implant – Species, Dose, Energy. Process CAD Doping profiles;
Diffusion/Oxidation – Temperature, Time, Junctions;
Rate, Pressure, Ambient (oxidation source). Process Sheet resistance.
Simulation

FIGURE 1.3
IC fabrication process simulation using process CAD to generate input file for device simu-
lation; the “physical change” refers to the structural change of the device such as the oxide
growth, whereas the “chemical change” refers to impurity diffusion; process CAD includes
physical process models to perform numerical process simulation.

and etching, ion implantation, and annealing, and generate input data files
for the device simulator as realistically as possible based on the microscopic
information as shown in Figure 1.3 [1–5]. In the area of process simulation,
physical models for process technology were rather limited in the 1960s and
1970s, and the sophisticated process simulators with multidimensional mod-
els were not necessary for the large device geometry used during that time.
In recent years, the physical understanding of IC processes has advanced sig-
nificantly. Moreover, the current evolution of IC devices into the nanoscale
regime necessitates accurate multidimensional process models.

1.1.2  Device CAD

Device CAD refers to numerical simulation of IC device operation as shown
in Figure 1.4. In general, the device CAD includes a suite of physical models
describing carrier transport in materials. Device models range from the sim-
ple drift diffusion, which solves Poisson and continuity equations, to more
complex and computationally challenging models such as the energy balance,
which solves some higher moment simplification of the Boltzmann trans-
port equation (BTE). In addition, the complex physics of today’s nanoscale
devices mandates the use of Monte Carlo (MC) codes, which stochastically
solves BTE, and the use of Schrödinger solvers that account for quantum

Structure: Electrical Characteristics:

Physical: Gate, Oxide, Substrate Input Output Current versus Voltage;
Device CAD Capacitance versus Voltage;
Electrical: Doping profiles,
Junction depth. Transient.
Device
Simulation

FIGURE 1.4
IC device simulation using device CAD to generate electrical characteristics of IC devices for
circuit analysis; device CAD includes physical device models to perform numerical device
simulation.
Introduction to Technology Computer Aided Design 5

Process Compact Model Circuit IC

Process CAD Device CAD
Flow Extraction CAD Design
Process Device
Simulation Simulation

FIGURE 1.5
Process and device CAD are synergistically linked to predict the influence of various IC pro-
cessing steps on device and circuit performance; here circuit CAD represents a modeling tool
to analyze circuit performance.

mechanical (QM) effects in metal-oxide-semiconductor field-effect transis-

tor (MOSFET) devices. The choice of the appropriate model depends on the
problem and the level of detail required. Despite the significant advances
of both numerics and physics, continuous development is required to meet
the increasingly challenging industry needs for device exploration, scaling,
and optimization. Therefore, the ability of device CAD to accurately model
today’s device performance and predict tomorrow’s device limitations is of
utmost importance [3,4].
Though the process CAD and device CAD refer to numerical simulation of
different areas of computational electronics, they are synergistically linked.
An understanding of the various IC processing steps is crucial to predicting
device and circuit performance as shown in Figure 1.5.

1.2  A Brief History of TCAD

During the last four decades, technology CAD has evolved from one-dimen-
sional (1D) Direct current (DC) or steady-state simulation only during the
1970s to full two-dimensional (2D) and three-dimensional (3D) simulation of
today’s complex very large scale integrated (VLSI) circuit fabrication processes
and devices. This evolution of process and device CAD has been possible due
to advancements in the computer technology and mathematical models, thus
providing cost-effective and efficient multidimensional numerical analysis
of IC fabrication processes and devices. A large number of researchers have
contributed to the evolution of TCAD. In this section, we present only a brief
history of the major development in the device and process CAD leading to
commercial TCAD tools.

1.2.1  History of Device CAD

The seminal work of Gummel in 1964 led to the foundation of device CAD.
For the first time, Gummel reported 1D simulation results of bipolar junction
transistors (BJTs) by sequentially solving the three PDEs in the drift-diffusion
6 Technology Computer Aided Design: Simulation for VLSI MOSFET

system using an iterative method [6]. Gummel’s numerical approach was

further developed and applied to simulate p-n junction by De Mari in 1968
[7,8] and Read diode oscillator by Scharfetter and Gummel [9] in 1969. In the
1969 publication, Scharfetter and Gummel reported a methodology for sta-
ble upwind discretization of the transport equations [9]. This method is still
almost universally used and is responsible for making device simulation a
computationally feasible design activity.
In 1968, the first 2D numerical solution of Poisson’s equation for a MOSFET
was reported by Loeb et al. [10] and, in parallel, by Schroeder and Muller [11].
In 1969, the 2D simulation results on planar devices were published by Barron
on MOSFETs [12] and Kennedy and O’Brien on junction field-effect transistors
(JFETs) [13] by solving the Poisson equation and one continuity equation. In the
same year, Slotboom reported the 2D simulation results on BJTs using the full
two-carrier system [14], and in 1971 Reiser reported the first 2D transient simu-
lation results of metal-semiconductor field-effect transistors (MESFETs) [15].
During the 1970s, the major numerical techniques for 2D device simulation
[16,17], including the first finite element analysis of the semiconductor equa-
tions [18,19], were reported. The finite element method can be considered a
precursor to the development of the more general-purpose tools commonly
used in the 1980s. In the late 1970s, some of the first publicly available device
CAD tools were released including the first version of the CADDETH pro-
grams from Hitachi [20] to simulate single carrier field-effect transistor (FET)
structures, the SEDAN program from Stanford University [21] to simulate
1D bipolar device phenomena, and a special-purpose MOSFETs simulation
program MINIMOS from Vienna [22].
Though the work on a general-purpose, non-planar multidimensional
device CAD program began in the mid-1970s, the first device simulation pro-
gram successfully used for bipolar device analysis was FIELDAY [23] from
IBM. Besides FIELDAY, the other first generation non-planar codes include
the GEMINI program in 1980 [24] which solved only Poisson’s equation and
PISCES-I in 1982 [25] which solved Poisson and a single continuity equation
in the steady-state, both from Stanford University.
The real impact of a general-purpose device CAD tool came in the
mid-1980s with the development of programs like PISCES-II at Stanford
University [26,27], DEVICE at AT&T Bell Laboratories [28,29], BAMBI at
Vienna [30], and HFIELDS [31] at the University of Bologna. Each of these
programs worked for two carriers, allowed arbitrary device non-planarities,
and included a more comprehensive set of materials, physical models, and
simulation capabilities than the prior state-of-the-art. However, the primary
advantages of these tools were improved computational methods such as
the discretization and grid generation, non-linear and linear solution tech-
niques that made device simulation practical for device designers. It is worth
noting that PISCES-II has been commercialized by Technology Modeling
Associates (TMA), now Synopsys [32], and Silvaco [33] and is the source of
widely used device simulators MEDICI and ATLAS, respectively.
Introduction to Technology Computer Aided Design 7

Major advances in the numerical solution of BTE [34] also began in the late
1970s. In 1979, the initial 2D MC device simulation results were reported by
Warriner [35]; in 1982, the PDE for energy transport was first treated numeri-
cally in 2D by Cook and Frey [36]; in 1984, Fukuma and Uebbing used the
energy balance model to predict velocity overshoot in silicon MOSFETs [37]
and the hot carrier post-processors with lucky electron based approach were
first implemented by Siemens [38]; in 1985, the first realistic 2D simulations of
hetero-structure devices were reported from the University of Illinois [39]; in
1986, Laux and Warren reported the coupled 2D Schrödinger-Poisson solver
and directly introduced quantum mechanics in device CAD [40]; in 1988, an
MC post-processor for silicon MOSFETs was developed at Bologna [41]; and
the first general-purpose code incorporating hydrodynamic solutions was
implemented in HFIELDS [42].
With the increasing complexities of IC devices due to continuous downscal-
ing of feature size, the 3D numerical analysis became critical. The first paper
using 3D device simulation of MOSFET narrow channel effects was pub-
lished in 1980 [43]. The FIELDAY was the first of many programs extended
into 3D in 1981 [44] by extending the grid uniformly in the depth plane.
Also, in 1981 and 1982, the 3D device simulation results of narrow channel
effects were published using the simulator WATMOS [45,46] which used a
finite difference scheme numerical solution of Poisson’s equation. Following
the approach of FIELDAY, almost every 2D simulation program has been
extended to 3D by extending the grid uniformly in the depth plane [47–52].
The FIELDAY program solved Poisson’s equation and both carrier continuity
equations. The program was later enhanced to include the hydrodynamic
energy-balance equations, Fermi-Dirac carrier statistics, lattice energy equa-
tion, and incomplete ionization [53]. Thus, both drift diffusion and hydrody-
namic simulations were possible using FIELDAY.
In 1985, Hitachi announced CADDETH as a 3D device simulator designed
to run on a supercomputer [49]. CADETH solves both Poisson’s equation and
two current continuity equations using conjugate gradient-based methods
for non-symmetric linear systems; distinguishes between three different
materials, namely semiconductors, insulators, and metals; and implemented
advanced physical models [49]. Another 3D simulator was developed by
Toshiba in 1985, called TOPMOST [54,55]. TOPMOST was designed to ana-
lyze MOS structures and solve the semiconductor equations for the drift-dif-
fusion case. Both 1D and 2D simulations could be performed by pseudo-1D
and pseudo-2D device models by reducing the number of points in the omit-
ted directions. TOPMOST was used to study the effect of the gate structure
on the output characteristics [54] and subthreshold swing in 3D MOSFETs
[55].
In 1987 Vienna announced 3D device simulator, MINIMOS Version 5 [56].
MINIMOS-5 is one of the first 3D device simulators [56–59] for MOSFET
structures, SOI transistors, and gallium arsenide MESFETs. MINIMOS-6,
released in 1994 [60], supports transient analysis and MC modeling to replace
8 Technology Computer Aided Design: Simulation for VLSI MOSFET

the drift diffusion approximation in critical device areas. The fundamental

semiconductor equations, consisting of Poisson’s equation and two carrier
continuity equations, are solved numerically in 2D or 3D space. MINIMOS
is able to simulate planar and non-planar device structures along with AC
small signal analysis and transient simulations.
The reported 3D device CAD tools from the industry include SMART
[61] from Matsushita in 1987, PADRE [62] from Bell Laboratories, SITAR [63]
from Siemens in 1988, MAGENTA [64] from Microelectronics and Computer
Technology Corporation in 1989, and SIERRA [51] from Texas Instruments in
1989. SIERRA solves Poisson’s equation and the carrier continuity equations
for static, AC small signal, and transient cases. Based on SIERRA, TMA devel-
oped their first 3D device simulator known as DAVINCI in 1991 [32]. DAVINCI
has been used to investigate the effects of radiation on DRAM cells and nar-
row channel effects in MOS structures. In January 1998, TMA merged with
Avant!, and in 2001 Avant! merged with Synopsys, and DAVINCI has been the
starting basis of the TAURUS 3D DEVICE program from Synopsys [32].
Some of the other reported 3D device CAD tools include HFIELDS-3D
[65–67] from the University of Bologna in 1989, SECOND [68–70] from ETH
Zürich and STRIDE [71] from Stanford University in 1991, FLOODS [72] from
the University of Florida in 1994, and DESSIS [73] in 1996. The development of
DESSIS began in 1992 in collaboration with Bologna, ETH Zürich, Bosch, and
ST Microelectronics [73]. DESSIS is created by merging the device simulators
HFIELDS from Bologna and SIMUL from ETH and circuit simulator BONSIM
from Bosch to enable efficient mixed-mode IC circuit/device analysis [73]. In
1993, Integrated Systems Engineering (ISE) was founded and took over the
simulator. In 2004 ISE merged with Synopsys which took over DESSIS and is
the basis of commercial Sentaurus device simulator from Synopsys [32].
With the evolution of IC technology and devices, TCAD is continuously
evolving. Another notable device CAD tool includes MINIMOS-NT [74]
reported in 1997. MINIMOS-NT is a generic 2D device simulator that allows
the modeling of high electron mobility transistors. A new method is used
which divides the device region into several sub-domains, referred to as seg-
ments, each segment with its specific physical models. The segmentation of
device region allows appropriate physical models to be used where required,
such as a hydrodynamic model in the channel region and drift diffusion
solution for the non-critical region of the device. This increases the over-
all efficiency of device simulation with the desired accuracy. Also, with the
ongoing reduction of feature sizes, atomistic simulations become reasonable
to study the effects of random discrete doping in the channel region [75–77].
The device CAD tools are continuously evolving, and mathematical mod-
els describing the performance of advanced devices are continuously imple-
mented, especially in the commercial TCAD tools to model today’s complex
IC devices.
Introduction to Technology Computer Aided Design 9

1.2.2  History of Process CAD

After the invention of ICs in 1958, the IC industry was dominated by BJT tech-
nology through the 1960s. However, in the 1970s MOSFET technology began
to overtake BJT technology in terms of the functional complexity and level of
integration. Since the 1980s, complementary MOS (CMOS) technology with
its cost-effective technology solution has become the pervasive technology
for ICs. With aggressive scaling of MOSFETs in the mid-1970s, transistor
dimensions soon reached the point at which first-order assumptions about
the physical effects and dopant distributions began to break down. For the
MOSFETs, the intrinsic device problem such as output conductance, velocity
saturation, and subthreshold behavior all received substantial interest and
effort. TCAD became critical to understand the many interrelated process
and device effects in MOSFETs.
By the mid-1970s, the critical role of processing technology in establishing
device characteristics was evident. Many important interrelated process and
device effects were identified by means of computer coupled analysis tools.
Industry leaders such as IBM and Texas Instruments had aggressive efforts
to model process physics and relate these models to device characteristics
and circuit statistics. A unified process and device simulator, the SITCAP
program was developed at Katholieke University, Leuven, Belgium [78]. This
program inputs process specifications such as processing times and temper-
atures along with simple mask geometries to output I–V and C–V curves,
along with selected SPICE model parameters. And, a process analysis pro-
gram CASPER was jointly developed at Lehigh University (Bethlehem,
Pennsylvania) and AT&T Bell Laboratories (Allentown, Pennsylvania) [79].
In 1977, the first version of 1D process simulator, SUPREM, was developed
and released by Stanford [80]. Since then, the process models in SUPREM
have developed substantially and evolved due to ongoing efforts at Stanford
and at industrial and other research laboratories worldwide. Versions II
and III of SUPREM were released in 1978 and 1983, respectively [81,82]. The
release of a process simulator had a tremendous impact on the accuracy to
which device simulations could be performed. Process simulation has con-
tinued to improve dramatically since the release of SUPREM. And the nota-
ble events in the evolution of process CAD include the development of the
full 2D simulators such as SUPRA from Stanford [83] in 1982 and BICEPS
from AT&T Bell Laboratories [84] in 1983. In 1986, the most advanced 2D
process simulation program SUPREM-IV was developed at Stanford [85].
The SUPREM-IV included more physically based models including point
defect calculations and stress dependent oxidation required for modeling
ultra-small device structures. A 2D SUPREM-IV process simulation program
has been commercialized by Crosslight [86], Sillvaco [33], and TMA [32] as
CSUPREM, ATHENA, and TSUPREM4, respectively.
10 Technology Computer Aided Design: Simulation for VLSI MOSFET

In 1992, ISE (now Synopsys [32]) developed 1D and 2D process simulators

TESIM and DIOS, respectively. DIOS was a widely accepted tool prior to the
introduction of the Sentaurus process by Synopsys in 2005.
The development of 3D process CAD tools began in the mid-1980s for
accurate modeling of ultra-small geometry device technology [87,88]. In
1993, FLOOPS was released from the University of Florida [89] and became
the source of Synopsys 3D process simulator, Sentaurus process that was
released in 2005 [32]. Other 3D process simulators include PROPHET from
AT&T Bell Laboratories [90] released in 1994 and Taurus 3D process from
TMA released by Avant! in 1998 [32].
The history of commercial TCAD began with the foundation of TMA in
1979. TMA was the first commercial supplier of TCAD software that was
the result of the TCAD research program at Stanford University under the
supervision of Professor Dutton and Professor Plummer. Currently, the
major sources of commercial TCAD tools are Silvaco [33] and Synopsys [32].
Synopsys TCAD tools include Taurus process/device TSUPREM4/MEDICI
for 2D TCAD and Sentaurus process/device for both 2D and 3D TCAD.
Silvaco TCAD tools include ATHENA for 2D process simulation, ATLAS for
2D device simulation, and Victory process/device for 3D simulation.

1.3  Motivation for TCAD

The major motivation for the use of TCAD in the semiconductor industry
is the cost-effective and efficient development of IC fabrication technology
using device CAD to analyze device performance and process CAD to input
realistic structural information from process flow to device CAD [1,5].

1.3.1  Motivation for Device CAD

The motivation for the use of device CAD in IC device analysis is the opti-
mization of device performance for specific applications. This optimization
is a complex task due to the complexities of the equations describing semi-
conductor device performance. For semiconductor devices, particle conser-
vation is modeled by several cross-coupled non-linear PDEs: the interaction
of charged particles due to electric fields is modeled by Poisson’s equation,
and the particle concentrations relating to particle fluxes and generation and
recombination are modeled by continuity equations. Also, electron and hole
concentrations are exponentially related to potentials through Boltzmann,
Fermi-Dirac, or other exponentially determined probability distribution
functions. These equations are difficult to solve by hand, making computer
aided analysis a desirable alternative. Again, by the introduction of the SPICE
program from Berkeley in 1975, the circuit simulator became a useful design
Introduction to Technology Computer Aided Design 11

tool, essentially replacing the bread-boarding of prototypes [91]. However,

for accurate circuit analysis, compact device models, commonly known as
SPICE models, are required. For the generation of SPICE models the device
CAD became a necessity. Thus, the widespread use of circuit simulation also
motivated the development and use of device CAD for IC device analysis.
Figure 1.5 illustrates the use of device CAD to generate compact models
for circuit analysis. Compact models such as BSIM4 [92] provide an excel-
lent framework to analyze different modes of MOSFET circuit behavior.
However, in order for the BSIM4 model to be useful in practice, reliable val-
ues for the model parameters must be generated. Device CAD tools are use-
ful for linking fabrication conditions to BSIM4 parameters. For example, the
device simulator uses inputs such as device geometry, doping profiles, and
bias conditions to generate data files for device characteristics such as capaci-
tance (C) and current (I) versus voltage. The simulated data files are then
used to extract BSIM4 model parameters for circuit analysis.
Another major motivation for using device CAD is to study the feasibil-
ity of realizing concept devices in manufacturing. As the MOSFET devices
are scaled down, device performance is severely degraded by short channel
effect (SCE), drain-induced barrier lowering (DIBL), quantum-mechanical
(QM) effects, and so on. The use of device CAD is critical to minimize
these physical effects and improve the device performance by optimizing
the device structure. Figure 1.6 shows a nanoscale “double-halo” MOSFET
device structure designed to suppress SCE, reduce DIBL and QM effects, and
improve device performance [93–97].
The double-halo MOSFET structure as shown in Figure 1.6 includes a poly-
silicon gate, a gate oxide (TOX), vertically and laterally non-uniform channel
doping profiles, shallow source-drain extensions (SDEs), deep source-drain
(DSD) regions, and two halo profiles: first around SDE and the second around
DSD regions to control DIBL from SDE and DSD junctions, respectively. A

Lg
cer
Lext Poly-Si gate (G) Spa TOX

Xj SDE
Xjd DSD
Double Double
Halo Leff Halo

Body (B)

FIGURE 1.6
An idealized double-halo MOSFET device structure showing the basic technology elements: Lg
and Leff are the drawn and effective channel lengths, respectively, TOX is the gate oxide thick-
ness, Lext is the spacer width, and Xj and Xjd are the junction depths of the source-drain exten-
sion (SDE) and deep source-drain (DSD) regions, respectively.
12 Technology Computer Aided Design: Simulation for VLSI MOSFET

super-steep retrograde (SSR) or “low-high” channel doping profile with a low

impurity concentration at the silicon/silicon-dioxide (Si/SiO2) interface and a
higher peak concentration at a finite depth below the interface is used to pro-
vide the non-uniform vertical channel profile [98]. The SSR profile is optimized
to achieve the target threshold voltage (Vth) for the long and wide devices.
The SSR profile also provides superior Vth control. The halo doping profiles
are optimized to achieve the target leakage current for the nominal devices.
In reality, the low-high channel doping profiles are achieved using multiple
buried layers under an undoped epitaxial layer of appropriate thickness [99].
Because, in reality, the ion-implanted profiles are non-linear, more sophisti-
cated 2D/3D device analysis tools are required for device optimization. Thus,
the device CAD use is critical to optimize the halo doping profiles in conjunc-
tion with other key technology parameters such as TOx and SDE junction depth
(XJ) to realize the nanoscale double-halo MOSFETs in manufacturing.
In optimizing the double-halo device performance, it is critical to analyze
the effect of scaling key technology parameters such as Xj and TOx on device
performance. Figure  1.7 shows 2D device simulation results of drain cur-
rent (Ids) versus source-drain voltage (Vds) with a given gate-to-source voltage
(Vgs). Two similar technologies are compared: one optimized for TOx = 1.5 nm,
and the other with TOx = 1.0 nm. For both cases, the devices are optimized to
achieve the same off-state leakage current, I off ≅ 10 nA/µm . From Figure 1.7,
we find that for small values of Vds, the curves show almost identical val-
ues of Ids. At higher Vds, the device with the lower TOx shows substantially
more current handling capability. Thus, both the technologist and the cir-
cuit designers are anxious to understand and control the dependencies of
key technology parameters to realize the optimum circuit performance of
double-halo CMOS technology. Therefore, the motivation to use device CAD
is to understand the dependence of key building blocks of device structure
on device and circuit performance.

1.3.2  Motivation for Process CAD

In the previous section, we have established the motivation for device CAD
in determining circuit design parameters with reference to MOSFET devices.
Now, let us discuss certain critical parameters in MOSFETs that depend
directly on the quantitative features of the doping profiles within the device.
Because doping profiles are determined by process variables such as ion
implantation energy, total implanted dose, and drive-in time/temperature
cycles, the dependence of device parameters on process variables provides
motivation for process simulation.
For MOSFET devices, Vth and other device parameters are directly related
to the distribution of the channel doping profile within the device struc-
ture. In order to produce accurate compact model para­meters such as V TH0,
Introduction to Technology Computer Aided Design 13

7.E–04
|V(Gate)| = 1.0 V
NMOS
|V(Gate)| = 0.8 V
6.E–04
|V(Gate)| = 0.6 V
|V(Gate)| = 0.4 V
5.E–04
TOX(eff ) = 1 nm; Lg = 40 nm
|I(Drain)| (A/µm)

~ 14 nm; L = 25 nm
Xj =
4.E–04 eff
V(Source) = 0 = V(Body)

3.E–04

2.E–04 PMOS

1.E–04

1.E–09
–1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0
V(Drain) (V)
(a)
7.E–04
|V(Gate)| = 1.0 V NMOS
|V(Gate)| = 0.8 V
6.E–04
|V(Gate)| = 0.6 V
|V(Gate)| = 0.4 V
5.E–04
TOX(eff ) = 1.5 nm; Lg = 40 nm
|I(Drain)| (A/µm)

~ 14 nm; L = 25 nm
Xj =
4.E–04 eff
V(Source) = 0 = V(Body)

3.E–04

PMOS
2.E–04

1.E–04

1.E–09
–1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0
V(Drain) (V)
(b)
FIGURE 1.7
I–V characteristics of double-halo MOSFETs for (a) TOX (eff) = 1 nm and (b) TOX (eff) = 1.5 nm; the
simulation data are obtained for 40 nm devices with Leff = 25 nm and optimized for |I off|= 10 nA/µm
at |V(Drain)| = 1 V; V(Gate) = V(Source) = V(Body) = 0). (From S. Saha, Scaling considerations for
high performance 25 nm metal-oxide-semiconductor field-effect transistors, J. Vac. Sci. Tech. B, vol.
19, no. 6, pp. 2240–2246, November 2001. With permission.)

modeling Vth for large devices, K1 and K2 describing body effect, U0 describ-
ing inversion layer carrier mobility, PDIBL1 and PDIBL2 describing DIBL,
and so on, the device simulator must have an exact description of the chan-
nel doping profile in all dimensions. This accurate description of channel
doping profile can be generated using process CAD.
14 Technology Computer Aided Design: Simulation for VLSI MOSFET

Lg
S G D

1.4e18
P-type
Linear
5.31e+18
4.6e+18
4.2e18 4.2e+18
5.31e18 5.31e18 3.8e+18
3.4e+18
3e+18
2.6e+18
2.2e+18
1.8e+18
1.4e+18
1e18 1e+18

FIGURE 1.8
Simulated 2D-doping contours of a typical double-halo nMOSFET device with laterally and
vertically non-uniform p-type channel doping generated using device CAD MEDICI; 2D
cross-section shows S, G, and D are the source, gate, and drain terminals, respectively, and
the outline of SDE and DSD junctions. (From S. Saha, Device characteristics of sub-20-nm
silicon nanotransistors, in Proc. SPIE Conf. on Design and Process Integration for Microelectronic
Manufacturing, vol. 5042, pp. 172–179, July 2003. With permission.)

Figure 1.8 shows the 2D doping profile of the 25 nm double-halo MOSFET

structure shown in Figure  1.6. A number of details of the technology are
apparent from the cross sections shown. First, the 2D halo doping contours
from the source and drain regions approach a peak at a certain depth from
the Si/SiO2 interface under the gate. The halo diffusion from the source and
the drain regions has enhanced the p-type doping concentration at the center
of the device under the gate region. With scaling TOX, the doping distribution
within the device changes both laterally and vertically. Calibrated process,
especially, diffusion models are essential for accurate generation of a 2D dop-
ing profile within the active region of the simulation structure. Therefore,
process simulation is critical to reproduce the doping distributions within
the structure for accurate device simulation and compact model parameter
extraction for circuit analysis.
Thus, the motivation to use process CAD is to couple the relevant fabrica-
tion information into the device CAD. The process CAD captures the critical
aspects of the target fabrication process to accurately determine device mod-
els for circuit analysis and predict the limitations in device performance. For
most device parameters, the exact description of doping profile is needed to
obtain agreement between the simulated and measured data.
Introduction to Technology Computer Aided Design 15

1.4  TCAD Flow for IC Process and Device Simulation

TCAD flow for IC process and device analysis includes the (1) generation of
simulation structure to numerically solve the PDEs that model IC processing
and device performance, (2) verification of the robustness of the simulation
structure and sensitivity of simulation results on grid space, (3) calibration of
physical models for accuracy and predictability, and (4) coupled process and
device simulation.

1.4.1  Generation of Simulation Structure

The first step in the numerical approach is the discretization of the simula-
tion domain in time and space. In this step, the device cross section is parti-
tioned into sub-domains or small cells, each of which is evaluated at discrete
time intervals. Then in each of these cells, the PDEs are approximated by
algebraic equations that include only the values of the continuous dependent
variables at discrete points in the domain and the knowledge of the struc-
ture of the functions approximating the dependent variables within each
cell. In case of process modeling, the time and space must be partitioned in
such a way so that the concentrations of the various impurities present are
constant over each individual cell during each time increment along with the
diffusivity and other physical parameters. Finally, the solution is computed
at each discrete point, known as the mesh or grid, within the domain. The
grid spacing must be sufficiently dense so that all the relevant features of
the doping profile are accurately represented. The increments of time must
be short enough to model important physical effects. On the other hand, it
is important not to use excessively small intervals to avoid time-consuming
and expensive numerical solutions. The detailed discretization technique is
discussed in the literature [100].
The layout of a mesh or grid in a simulation structure is a very important
aspect of the numerical solution of PDEs, as it directly determines how well
the discrete model represents the actual problem. There are a number of con-
siderations regarding grid selection. First, the points must be allocated to
accurately approximate any physical quantities of interest including poten-
tials, concentrations, fields, and currents, as well as any irregularities in
the geometry of the domain. Second, because the overall computation time
depends on the total number of grid points, grid points must be optimized
for computational efficiency. Finally, the finer grid must be allocated in the
active regions of device operation under the biasing conditions [3,101].
Solution variables such as potentials, doping, charge, and recombina-
tion appear in the PDEs. Therefore, high grid densities must be allocated
in regions where any of these quantities undergo rapid changes (e.g., p-n
junctions). Conversely, the spacing between points could be relaxed in areas
where values remain relatively constant without adding any significant
16 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.00

1.00
Distance (Microns)

2.00

3.00
0.00 1.00 2.00 3.00 4.00
Distance (Microns)

FIGURE 1.9
A typical optimized mesh of an LDD MOSFET simulation structure; grid is denser in the gate
oxide and channel region as well as at the source-drain junction. (From S. Saha, MOSFET test
structures for two-dimensional device simulation, Solid-State Electron., vol. 38, no. 1, pp. 69–73,
January 1995. With permission.)

contribution to the overall error (e.g., quasi-neutral regions deep inside the
device). In addition, the simulation structure must be robust so that the sim-
ulated device performance is independent of grid density, and the robust-
ness of the simulation domain; that is, sensitivity of simulation results on
grid must be checked [101] after the structure generation. Figure 1.9 shows a
typical robust mesh of a MOSFET simulation structure.

1.4.2  Verification of the Robustness of Simulation Structure

In the previous subsection we discussed that an appropriate simulation
domain is required to emulate the impurity distribution within the device
as accurately as possible. Inaccurate mesh may cause fluctuation in the simu-
lation results. Therefore, it is critical to check the robustness of the simulation
structure by varying the grid space to generate grid-independent simulation
results [101].
Figure 1.10 shows the sensitivity of simulated I–V characteristics of nMOS-
FETs on grid allocation. Figure 1.10(a) shows the sensitivity of I–V data on
vertical grid space, Y.GRID in the channel at the SiO2/Si interface. It is seen
from Figure  1.10(a) that for Y.GRID ≤ 200 Å, the magnitude of Ids attains a
maximum value and the electrical characteristics become insensitive to the
Introduction to Technology Computer Aided Design 17

0.020
Measurement
Y.GRID = 12 A
Y.GRID = 35 A
Drain Current (A) 0.015 Y.GRID = 100 A
Y.GRID = 140 A
Y.GRID = 200 A
Y.GRID = 250 A
0.010
Y.GRID = 300 A

0.005

0.000
0 1 2 3 4 5
Gate Voltage (V)
(a)
0.020
Measurement
X.GRID = 200 A
X.GRID = 250 A
0.015 X.GRID = 300 A
Drain Current (A)

X.GRID = 350 A
X.GRID = 400 A
X.GRID = 450 A
0.010 X.GRID = 500 A

0.005

0.000
0 1 2 3 4 5
Gate Voltage (V)
(b)

FIGURE 1.10
Sensitivity of grid density on MOSFET device performance; (a) sensitivity of vertical grid,
Y.GRID on Ids and (b) sensitivity of lateral grid, X.GRID on Ids; here Lg = 0.8 μm, W = 40 μm, and
TOX = 15 nm; all data are obtained at V(Drain) = 5 V and V(Body) = 0 = V(Source). (From S. Saha,
MOSFET test structures for two-dimensional device simulation, Solid-State Electron., vol. 38, no. 1,
pp. 69–73, January 1995. With permission.)

values of Y.GRID at the surface. Figure  1.10(a) also shows that the magni-
tudes of the measured and simulated data are closer for Y.GRID ≤ 200 Å.
Thus, Y.GRID = 12 Å at the surface near the Si/SiO2 interface generates robust
test structures for device simulation and accurately models critical physical
effects such as inversion layer quantization in the MOSFET channel [98].
Figure 1.10(b) shows the sensitivity of I–V data on the lateral grid space,
X.GRID in the channel region. It is also seen from Figure  1.10(b) that for
18 Technology Computer Aided Design: Simulation for VLSI MOSFET

X.GRID ≤ 300 Å, the magnitude of Ids attains a maximum value, and the device
characteristics are independent of X.GRID. It is obvious from Figure 1.10(b)
that the simulated and measured data are in close agreement for X.GRID ≤
300 Å. Thus, X.GRID ≤ 200 Å can be used to reduce the uncertainty in the
simulated electrical characteristics due to incorrect grid allocations and gen-
erate robust test structures for device simulation.
For simulation accuracy and computational efficiency, fine grid is allocated
only in the regions of most physical importance as shown in Figure 1.9. The
procedure to verify the robustness of the generated mesh by studying the
electrical behavior as a function of grid space minimizes the probable errors
in the simulation data due to incorrect grid allocation and therefore pro-
vides accurate calibration of the fundamental material parameters for device
simulation.

1.4.3  Calibration of Physical Models

The accuracy of simulation results relates to the underlying physics, numer-
ical discretization issues, and the proper characterization of the models
implemented in the process and device CAD tools. Over the years, the
capabilities of TCAD point tools have significantly improved. However, due
to the deficiencies in physical models, the simulation results are not 100%
predictable and reliable. Although the development and implementation
of advanced physical models have been moving ahead with a steady-state
growth pattern, the characterization of the existing models is critical to
make TCAD accurate. Therefore, the predictability issue must be addressed
by proper calibration of the process and device models implemented in
TCAD point tools. The calibration is a complex and time-consuming task.
In the following section, a brief overview of physical model calibration is
presented.
The physical process models implemented in the process CAD tool must
be calibrated for the target technology under development. The calibration
methodology includes designing short loop wafer fabrication experiments to
calibrate all critical as-implanted as well as final doping profiles of all rele-
vant impurities in the simulation structures. For a typical CMOS technology
this includes 1D doping profiles for (1) channel, (2) SDE, and (3) DSD regions
along the cutlines shown in Figure 1.11.
In order to calibrate the physical device models implemented in device
CAD tools, a set of appropriate device characteristics are measured from the
fabricated wafers of the target technology. For a typical CMOS technology
this includes Ids versus Vgs, Ids versus Vds, substrate current, Isub versus Vgs, and
so on to characterize the physical device models [102,103]. Figures 1.12(a) and
1.12(b) show a basic flow for process and device model calibration of a typical
CMOS technology. As shown in Figure  1.12(a) coupled process and device
CAD is used to calibrate 2D doping profiles.
Introduction to Technology Computer Aided Design 19

n+ n+ p+ p+
STI

p-well n-well

NMOS PMOS
p-substrate

A B C F E D
2D-CMOS cross-section to obtain 1D doping profiles along the cut lines:
A/D NMOS / PMOS channel;
B/E NMOS / PMOS SDE;
C/F NMOS / PMOS DSD.

FIGURE 1.11
A typical 2D-CMOS cross-section showing the cutlines along the depth of the simulation
structure to obtain 1D doping profiles for process model calibration. (STI represents the shal-
low trench isolation.)

For greater accuracy and predictability of simulation results, two levels of

calibration are performed, namely (1) local calibration and (2) global calibra-
tion [1]. A brief outline of the calibration levels is presented below:

Local calibration: The physical models implemented in the process and

device CAD tools can be characterized with the measured data of the
target technology for predictive process and device simulation. During
the IC fabrication process development cycle, a large number of mea-
sured data are generated. This experimental database of the target
technology can be used to calibrate the process and device models and
correlate simulation data with the measured data of the target technol-
ogy. The calibrated TCAD models and simulation files are transferred
to manufacturing at the end of the technology development (TD) cycle.
These models can be used with a higher degree of accuracy (1) to evalu-
ate the effects of process control variables on device and product perfor-
mance and (2) for manufacturing process control [104–107]. Therefore,
the calibrated TCAD models of a particular process technology can be
used for the predictive simulation of that technology.
Global calibration: In order to develop a new IC fabrication technology,
the TCAD point tools must be accurate and must accurately predict
new physical phenomena, as may emerge during the development
phase. Unfortunately, due to the lack of accurate physical models,
effective calibration methodologies must be developed for the suc-
cessful application of TCAD in designing a new technology. For the
20 Technology Computer Aided Design: Simulation for VLSI MOSFET

Process Model Calibration

Calibration Targets

Match SIMS profiles

One-dimensional Calibration

Adjust for dose loss

Implant moments/table;
Oxidant-Enhanced Diffusion (OED);
Segregation (set by channel profile);
Diffusivity (in oxide for dose loss);
TOX (QM, Poly-depletion corrections).

Two-dimensional Calibration

Match Vth
Drain-Induced-Barrier Lowering (DIBL);
Surface recombination;

SCE
Damage by source-drain implant.

Check SIMS
One-dimensional Calibration
Diffusivity of dopant-defect pair;

profiles
Diffusivity of defects;

(a)
Device Device Model
Characteristics Calibration

Ids vs. Vgs (Vth) Work function

@ Vbs = 0, Vds = 50 mV QM model
Low field mobility

Ids vs. Vgs (Ids vs. Vds)

High field mobility
@ Vbs = 0, Vds = Vdd

Ids vs. Vds Band to band

@ Vbs = 0, Vgs = 0 Tunneling (BTBT)

Isub vs. VGS

Impact Ionization
@ Vbs = 0, Vds ≥ Vdd

(b)

FIGURE 1.12
A simplified process and device model calibration flow for a typical CMOS technology: (a)
process model calibration using coupled process and device CAD; (b) device model calibration
using device CAD with measured device characteristics. In (a), SIMS represents secondary ion
mass spectrometry.
Introduction to Technology Computer Aided Design 21

predictive application of TCAD, the numerical models must be ini-

tially characterized with a known previous generation of technology.
These models can be applied to several similar technologies with
the available experimental database. An iterative method of model
updates to correlate the simulation and the measurement data must
be continued up to an acceptable limit of tolerance of the simulation
data with respect to the measurement data. This iterative method
of model characterization with different known technologies and
constant updating of the models provides a global calibration of
the numerical models, which can be applied for next-generation
IC fabrication process development with a higher degree of confi-
dence. In addition, the calibration database must include the data
from a wider range of anticipated process conditions for the next-
generation process technology and device characteristics. Finally, a
limited number of wafers of the target new technology should be
processed concurrently for a local update of the globally calibrated
models. These calibrated physical models and the model parameters
will provide a higher degree of accuracy for simulation results and
can be applied successfully in developing next-generation IC fabrica-
tion technology.
Calibration database: The calibration database used in simulation must
include the measured doping profiles and device characteristics. The
doping profiles must be obtained under a wide range of processing
conditions covering the anticipated process variations of the target
technology. The device characteristics must be obtained under vari-
ous biasing conditions of circuit operations. The database must also
be updated to include any new physical phenomena observed in the
fabrication facility. In order to develop the next-generation IC fabri-
cation technology, the database must also include the measured data
of the anticipated doping materials under the anticipated processing
conditions of the target technology. In reality, the individual process
module for a new technology is developed prior to the start of the
cycle for TD. Therefore, working with the unit process or the mod-
ule development group, the calibration database can be prepared to
include the data for the development of a target technology. In addi-
tion, the measurement data for an advanced technology with respect
to the newer fabrication equipment can be obtained in collaboration
with the equipment vendors. Thus, the calibration database must
have experimental data for all the possible effects of the existing and
the target next-generation technology.
22 Technology Computer Aided Design: Simulation for VLSI MOSFET

1.4.4  Coupled Process and Device Simulation

Process CAD is used for unit process development such as time and temper-
ature required for growing the MOSFET gate oxide, shallow trench isolation
(STI) module for CMOS technology, and so on. Similarly, the device CAD is
used to analyze the effect of process variables on device operation. However,
the coupled process and device simulation allows IC designers to directly
investigate the effect of process specifications on electrical variations in
devices and circuits. The key task of process CAD is to capture the features
that accurately reflect the performance limitations of a given fabrication
technology.
Figure 1.13 presents an overview of the simulation flow that is used to link
process specifications to circuit performance. For the most part, the user input
is simply a description of how the actual fabrication sequence progresses.
The process simulation generates a set of data with the structural informa-
tion like device geometry, doping distribution, and so on. The output of pro-
cess simulation is then used as the input of device CAD to perform device
simulation to obtain I–V, C–V data. These simulation data are used to gener-
ate SPICE models by well-established parameter extraction techniques, and

Process Flow

Calibrated Process CAD

Process Models Process Simulation

Calibrated Device CAD

Device Models Device Simulation

Check Robustness of
Simulation Mesh

Simulate I – V data Simulate C – V data

Generate Compact Models

Circuit CAD
Circuit Simulation

FIGURE 1.13
Link IC process flow to circuit performance using coupled process and device CAD.
Introduction to Technology Computer Aided Design 23

the SPICE models are used for circuit simulation. At each step, the emphasis
is on focusing a broad spectrum of inputs into a coherent set of outputs that
will be of maximum utility in the next step. Thus, the coupled process and
device CAD can be considered as a “virtual factory” simulating ICs from the
process flow analogous to wafer fabrication facility manufacturing ICs from
the target process flow as shown in Figure 1.13 [104].
Through well-defined data exchange formats, the various levels of CAD
are linked quite efficiently with or without simulation framework. The link-
age of process to device CAD occurs through the exchange of both topo-
graphic information and arrays of data representing dopant distributions.

1.5  TCAD Application

In the semiconductor industry the major use of TCAD is in advanced device
research to study new device concepts, TD, and technology transfer process
[1,105–107]. In the following subsections we discuss some examples of these
TCAD usages.

1.5.1  TCAD in Device Research

TCAD is used to study the feasibility of new device concepts or exploratory
devices for the next-generation IC fabrication TD. For exploratory devices,
the fabrication process is yet to be determined. Therefore, only device CAD
is used to design and optimize the device structure and device performance.
In this case, the device structure is generated using analytical doping pro-
files. Figure  1.14 shows a typical flow to use device CAD in the feasibility
study of new concept devices.
In Figure 1.14, the basic simulation flow includes device architecture by ana-
lytical doping profile, use of device CAD to simulate device characteristics,
verification of the robustness of the simulation structure, and optimization
of the device structure to achieve the target performance objectives. After
device optimization, perform device simulation to generate I–V and C–V
data, format device simulation data, and generate compact models for circuit
analysis. In Figure 1.14, note that calibrated device models are required for
accurate prediction of device performance. After achieving the target device
performance by iterative device simulation, appropriate fabrication process
is designed for technology optimization using coupled process and device
CAD flow. To illustrate the use of device CAD in device development for the
next-generation fabrication technology, let us discuss the architecture and
performance of nanoscale double-halo MOSFETs and split-gate (SG) flash
memory cells.
24 Technology Computer Aided Design: Simulation for VLSI MOSFET

Device
Specifications

Calibrated Device CAD

Device Models Device Simulation

Check Robustness of
Simulation Mesh

Simulate I – V data Simulate C – V data

Generate Compact Models

Circuit CAD
Circuit Simulation

FIGURE 1.14
A typical device CAD-based simulation flow to study new device concepts and generate elec-
trical device characteristics for circuit analysis.

1.5.1.1  Double-Halo MOSFET Devices

It is well known that the conventional scaling of MOSFET devices in the
nanoscale regime requires a reduction of the gate oxide thickness (TOX) and
an increase in the channel doping concentration (NCH) to control SCE, DIBL,
and leakage. However, the combination of such high NCH and ultra-thin
Tox is likely to cause severe performance degradation due to higher Vth. In
order to suppress SCE and control DIBL, typically, a single halo profile is
used around SDE. However, as the MOSFET devices approach their ulti-
mate dimension near the 10 nm regime, both SDE and DSD regions near
the source-end of the channel contribute to DIBL, resulting in higher Ioff
and degradation in the subthreshold swing. In order to control DIBL from
both SDE and DSD, we can use two halo doping profiles, one around SDE
and other around DSD. Then use device CAD to optimize these halo dop-
ing profiles to control Vth, SCE, DIBL, and Ioff in the nanoscale MOSFETs.
Therefore, our objective is to design high performance nanoscale MOSFETs
with low leakage, fast switching, controlled SCE, and reduced DIBL and QM
effects [93–97]. In order to achieve our objective an ideal structure shown in
Figure 1.6 is used to optimize the device performance.
Introduction to Technology Computer Aided Design 25

In device architecture, the n/p MOS device structure shown in Figure 1.6

includes an n+/p+ polysilicon gate, a gate oxide, vertically and laterally non-
uniform channel doping profile, shallow n+/p+ SDE, deep n+/p+ DSD, and
two halo doping profiles: the first around SDE and the second around DSD
regions. An SSR doping profile with a low impurity concentration at the Si/
SiO2 interface and a higher peak concentration at a finite depth below the
interface is used to provide the non-uniform vertical channel profile [97,
98]. The SSR profile is optimized to achieve a target Vth for the long channel
devices. The SSR profile also provides superior Vth control caused by dopant
fluctuations [108].
The non-uniform analytical lateral channel doping profile is achieved
using two Gaussian halo profiles during drain-profile engineering [109]. The
first halo doping profile is a heavily doped shallow profile defined on both
sides of the gate region aligning at the gate edge. The peak concentration of
the shallow halo profile is defined immediately below the SDE junction (Xj)
to reduce DIBL due to SDE. The second halo profile is a lightly doped deep
profile defined on both sides of the gate region by an offset distance from the
gate edge. The peak concentration of the second halo doping is placed imme-
diately below the DSD junction (Xjd) to control DIBL due to DSD. The detailed
fabrication procedure is described in [95]. After device architecture, device
CAD is used to study the device performance of the double-halo MOSFETs.
A hydrodynamic model for semiconductors with full energy balance solu-
tion along with an analytical QM model [110] is used for device simulation
[111]. The halo profiles along with the SSR channel doping profile are opti-
mized to the target Ioff = 10 nA/μm. The 2D doping distribution of an optimized
double-halo nMOSFET device is shown in Figure  1.8. And, Figures  1.15(a)
and 1.15(b) show the simulated device performance of double-halo nMOS-
FET and pMOSFET devices with effective channel length, Leff = 25 nm.
Device simulation results in Figure  1.15 show excellent device perfor-
mance, thus achieving the target objective of this study. Thus, device CAD
can be used to optimize exploratory devices and assess the feasibility of
these devices for next-generation IC fabrication technology.
After device optimization using device CAD, an initial guess process flow
is created to reproduce the analytical doping profiles used in device simula-
tion. Then the process CAD is used to perform process simulation and opti-
mize the process flow. Figure  1.16 shows only the section of process flow
used to integrate the double-halo MOSFETs in advanced CMOS technology.
The detailed process flow is described in [95].
In Figure 1.16, the shallow halo doping profile is implanted after the gate
definition with peak concentration immediately below Xj. Then about a 2-nm
wide offset spacer is used to implant the deep halo and SDE profiles. Because
the depth of the shallow halo is ~Xj, SDE regions are encroached by about 2
nm with the halo doping near the Si/SiO2 interface within the channel. Thus,
the shallow doping profiles only enhance the channel doping by about 4 nm
of Leff ≅ 25 nm near the Si/SiO2 interface. On the other hand, the deep halo
26 Technology Computer Aided Design: Simulation for VLSI MOSFET

1.E–03
pMOSFET nMOSFET
1.E–04

1.E–05
|I(Drain)| (A/µm)

1.E–06 ~ 80 mV/decade
S= TOX(eff ) = 1 nm
Lg = 50 nm
1.E–07 X =~ 20 nm
j
Leff = 25 nm
1.E–08 |V(Drain)| = 1.00 V V(Source) = 0
V(Body) = 0
|V(Drain)| = 0.05 V
1.E–09
–1.0 –0.5 0.0 0.5 1.0
V(Gate) (V)
(a)
7.E–04
TOX(eff ) = 1 nm; Lg = 50 nm
~ 20 nm; L = 25 nm
Xj =
6.E–04 eff
V(Source) = 0 = V(Body)
5.E–04 |V(Gate)| = 1.0 V
|I(Drain)| (A/µm)

|V(Gate)| = 0.8 V
4.E–04 |V(Gate)| = 0.6 V
|V(Gate)| = 0.4 V nMOSFET
3.E–04

2.E–04
pMOSFET
1.E–04

0.E+00
–1.0 –0.5 0.0 0.5 1.0
V(Drain) (V)
(b)

FIGURE 1.15
Device characteristics of double-halo MOSFETs obtained by device CAD: (a) Ids versus Vgs and
(b) Ids versus Vds; the simulation data are obtained for 50 nm devices with Leff = 25 nm and
optimized for |I off|= 10 nA/µm at |V(Drain)| = 1 V; V(Gate) = V(Source) = V(Body) = 0. (From S.
Saha, Design considerations for 25 nm MOSFET devices, Solid-State Electron., vol. 45, no. 10, pp.
1851–1857, October 2001. With permission.)

doping profiles with depth ~ DSD junction depth diffuse laterally into the
channel region to enhance the channel doping at a finite depth below the
Si/SiO2 interface. Thus, the combination of double-halo profiles provides the
non-uniform lateral channel doping while maintaining a lower channel dop-
ing concentration near the surface due to the SSR channel doping profile. The
halo implant dose and energy are optimized to achieve the target value of Ioff
Introduction to Technology Computer Aided Design 27

TOX Pad oxide

Gate Gate definition
Shallow halo (#1) implant
Halo 1
p(n) well

TOX Offset spacer

Gate Ultra-thin offset spacer formation
SDE Deep halo (#2) implant
SDE implant
Halo 2 p(n) well

TOX DSD spacer DSD spacer formation

Gate
DSD implant
DSD
p(n) well Dopant activation

FIGURE 1.16
Part of the process flow showing the integration of two halo profiles in CMOS technology
to fabricate nanoscale double-halo MOSFET devices. (From S. Saha, Device characteristics
of sub-20-nm silicon nanotransistors, in Proc. SPIE Conf. on Design and Process Integration for
Microelectronic Manufacturing, vol. 5042, pp. 172–179, July 2003. With permission.)

for the nominal devices of the target technology. The source-drain regions are
optimized to achieve an improved device behavior, and the peak impurity
concentrations for SDE and DSD profiles used are 2.5 × 1020 cm–3 and 3.7 × 1020
cm–3, respectively [93,94].

1.5.1.2  Sub-90 nm Split-Gate Flash Memory Cells

Our second example of device CAD use in advanced device research and
development is to study the feasibility of scaling split-gate (SG) NOR-type
flash memory cells below 90 nm. A typical SG cell with top coupling gate
(CG), called SG-TCG cell [112], is shown in Figure 1.17. The structure includes
a select gate or word-line (WL) with gate oxide (Tox), a floating gate (FG) with
tunneling oxide (Tox,tun), a CG with inter-poly oxide (Tox,IPO), an n+ source as the
“Bitline” (BL), and an n+ drain as the “Sourceline” (SL). The FG is completely
isolated within the gate dielectric and acts as a potential well to store charge
by programming the cell using source-side injection (SSI) of hot carriers. The
erase operation is performed by poly to poly Fowler-Nordheim tunneling of
carriers from the FG to WL. The sharp FG-tip near the WL edge in Figure 1.17
improves the erasing efficiency of the programmed cells. Because the cell
structure in Figure 1.17 consists of two MOSFET devices in series, it is difficult
to scale these cells in the sub-90 nm regime due to several constraints [113,114].
28 Technology Computer Aided Design: Simulation for VLSI MOSFET

Tox,IPO

Coupling
Gate
BL SL
Tox Word Line Floating Gate

Gap to create Tox,tun

n+ Source n+ Drain
high lateral
electric field
Bulk

FIGURE 1.17
An idealized SG-TCG flash memory cell structure used for scaling in the sub-90 nm regime:
here, BL = bitline, Tox = WL-transistor gate oxide thickness, Tox,tun = tunneling oxide thickness,
Tox,IPO = inter-poly oxide thickness and SL = Sourceline. (From S.K. Saha, Non-linear coupling
voltage of split-gate flash memory cells with additional top coupling gate, IET Circuits, Devices
& Systems, vol. 6, no. 3, pp. 204–210, May 2012. With permission.)

The major scaling constraints of NOR-type SG-TCG cells are (1) the high
value of SL programming voltage, VSL ≡ Vsp >> 3.2 V required for an effi-
cient hot-electron programming [113] and Vsp > floating gate (FG) transistor
saturation voltage (VSL,sat) required to mitigate the risk of supply voltage fluc-
tuations [112]; (2) excessive program-inhibit leakage current, Ioff(BLI) causing
inhibited cells susceptible to soft-write error [113,114]; (3) high program cell
leakage current, Ir0, causing ineffective sensing of the write and erase states
by the sense amplifiers [113,114]; and (4) degradation of program/erase (P/E)
coupling ratio causing degradation in P/E efficiency [113,114].
Our objective is to design high performance sub-90 nm NOR-type SG-TCG
cells within the above described scaling constraints. First, the requirement
for Vsp >> 3.2 V makes the scaled SG-TCG cells susceptible to punchthrough
at the operating conditions, causing degradation in the cell reliability.
Therefore, in order to improve the punchthrough voltage, the channel dop-
ing concentration must be increased which in turn decreases the SL p-n
junction breakdown voltage, BVj. Thus, we need to optimize the channel
doping profile and use graded SL/BL p-n junctions to improve the overall
cell breakdown voltage (BV) to achieve the target Vsp for the scaled SG-TCG
cells. In this case, three channel doping profiles are used to optimize cell
performance for the target Vsp value.
The next requirements are tolerable leakage currents Ioff(BLI) and Ir0 at the
target SL voltage (VSL) for the sub-90 nm SG-TCG cells. Ioff(BLI) is the off-state
leakage current of WL-MOSFETs, whereas Ir0 is the off-state leakage current
of FG MOSFETs. Thus, Ioff(BLI) can be optimized to the target value required
for the target Vsp using shallow BL-extension (BLE) and optimizing BL-halo
to reduce SCE and DIBL. Similarly, to achieve the target Ir0 shallow SL junc-
tion along with a lightly doped FG-channel profile is used as shown in
Figure 1.17. The target values of leakage currents at the required VSL = Vsp are
Introduction to Technology Computer Aided Design 29

obtained using device CAD. In this case, we can use device CAD to deter-
mine the maximum tolerable parasitic leakage current for BV > Vsp. In this
example, the device simulation data show that Ir0 ~ 200 pA/cell at V(BL) = 0.8 V
and V(FG) = 0 with WL device on and Ioff(BLI) ~ 200 nA/kbit at V(BL) = 1.8 V
and V(WL) = 0 with FG device on are required to maintain Vsp = 6.5 V < BV.
The detailed optimization technique is reported in the references [113,114].
The final requirement to design sub-90 nm SG-TCG cells is to account for
the degradation of the coupling ratio in the scaled devices. The addition of
top CG improves the programming coupling ratio, whereas the shallow BLE
without overlap under the WL transistor improves the erase coupling ratio.
Thus, the use of shallow SL junction will control SCE and DIBL and
improve scalability of SG-TCG cells. In addition, a shallow BL-junction will
control DIBL and improve scalability of the cells. In this example, a shallow
BLE and deep BL regions along with BL-halo are used to optimize the cell to
the desired performance objective [112–114]. The final simulation structure of
the optimized SG-TCG cell is shown in Figure 1.18.
Figure 1.19 shows device simulation results of the optimized SG-TCG cells.
Figure 1.19 shows that Vth(WL) and cell read current (Ir1) as function of WL tran-
sistor channel length. In Figure 1.19(a), Vth(WL) is extracted from the extrapolated
Ids − Vgs plots of WL-devices at Vds = 50 mV with overdrive V(FG) = 2.5 V. And
Ir1 = Icell is obtained at the read condition, V(WL) = 2.5 V, V(BL) = 0.8 V, V(FG) = 1.8 V
= V(CG), and V(SL) = 0. The device simulation data show acceptable read current
Ir1 ≈ 22.2 μA for 65 nm cells optimized for Vsp = 6.5 V. Figure 1.19(b) shows the

Tox,IPO
BL
SL
WL CG
Tox
FG
n+ BLE n+
Tox,tun
n+ BL

P-substrate

FIGURE 1.18
The final sub-90 nm SG-TCG flash memory cells structure generated using device CAD
tool MEDICI: here, BL = bitline, WL = word line, FG = floating gate, CG = coupling gate, Tox
= WL-transistor gate oxide thickness, Tox,tun = tunneling oxide thickness, Tox,IPO = inter-poly
oxide thickness, SL = sourceline, and BLE = shallow BL extension. (From S.K. Saha, Non-linear
coupling voltage of split-gate flash memory cells with additional top coupling gate, IET Circuit,
Devices & Systems, vol. 6, no. 3, pp. 204–210, May 2012.)
30 Technology Computer Aided Design: Simulation for VLSI MOSFET

1.00 40
Vth (WL)
0.95 38
Icell
36
0.90
34
0.85 32
Vth (WL) (V)

Icell (µA)
0.80 30

0.75 28
26
0.70
24
Ioff (BLI) ~
= 193 nA/kbit
0.65 22
~
I = 193 pA
r0
0.60 20
65 70 75 80 85 90 95 100
WL Length (nm)
(a)
5.5
WL = 100 nm
WL = 90 nm
5.0 WL = 80 nm
WL = 70 nm
WL = 65 nm
4.5
V(FG) (V)

4.0

3.5

3.0

2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
V(SL) (V)
(b)
FIGURE 1.19
Simulated device performance of SG-TCG cells: (a) Vth and Icell versus WL-transistor channel
length and (b) programming coupling voltage V(FG) as a function of programming voltage
V(SL) obtained at function of programming voltage V(SL) obtained at V(CG) = 10 V. (From S.K.
Saha, Design considerations for sub-90 nm split-gate Flash memory cells, IEEE Trans. Electron.
Devices, vol. 54, no. 11, pp. 3049–3055, November 2007. With permission.)

simulated V(FG) versus V(SL) plots of the SG-TCG cells at V(CG) = 10 V. Similarly,
Figure 1.20 shows an improvement in both programming coupling ratio due to
CG and the new device architecture with shallow SL and BLE junctions.
The device simulation study clearly shows the feasibility of SG-TCG cell
scaling near the 65-nm regime. After the device optimization, an initial guess
process flow is created as shown in Figure 1.21 for complete technology opti-
mization using coupled process and device CAD as shown in Figure 1.13.
Introduction to Technology Computer Aided Design 31

12.5
Cell2: WL = 90 nm
11.5
Cell5: WL = 65 nm
10.5
9.5
8.5
Vth (V)

7.5
6.5
5.5
4.5
3.5
2.5
1.E–06 1.E–05 1.E–04 1.E–03 1.E–02 1.E–01 1.E+00
Programming Time (sec)
(a)
12
Cell2: WL = 90 nm
10 Cell5: WL = 65 nm

8
Vth (V)

0
1.E–07 1.E–06 1.E–05 1.E–04
Erase Time (sec)
(b)
FIGURE 1.20
Programming/erase characteristics of SG-TCG cells: (a) programming at V(WL) = 1.2 V, V(SL)
= 6.5 V, V(BL) = 0.3 V, and V(CG) = 10 V; and (b) erase; at V(WL) = 10 V and V(SL) = 0 = V(BL);
from simulation data the time to program, T2P ≈ 30 μs and time to erase, T2E ≈ 40 μs. (From S.K.
Saha, Design considerations for sub-90 nm split-gate Flash memory cells, IEEE Trans. Electron.
Devices, vol. 54, no. 11, pp. 3049–3055, November 2007. With permission.)

The device-simulation results show that the sub-90-nm SG-TCG flash-

memory cells can be achieved with tolerable Ir0 < 200 pA, IOFF(BLI) < 200 nA/kb,
acceptable Ir1, and excellent T2P ≈ 30 μs and T2E ≈ 40 μs. Thus, the present
design methodology demonstrates the feasibility of high performance sub-
90-nm split-gate flash-memory cells down to 65 nm with Ir1 ≈ 235 μA/μm
along with efficient P/E characteristics. From the results of device CAD, a
process flow is developed for coupled process and device simulation.
32 Technology Computer Aided Design: Simulation for VLSI MOSFET

P-well 1 implant: peak concentration depth ~ 0.4 µm

P-well 2 implant: peak concentration depth ~ SL-junction depth
P-well 3 implant: defines WL Vth

FG Vth-adjust implant
FG-transistor gate oxide growth: thickness ~ 9 nm
n+ FG-poly definition

Inter-poly (FG – CG) oxide deposition: thickness ~ 12 nm

n+ CG-poly definition

SL-offset spacer deposition

Ultra-shallow SL implant
n+ SL-poly formation

WL-transistor gate oxide growth: thickness ~ 13-nm

n+ WL-poly definition

BL-halo-offset spacer deposition

BL-halo implant
BL-offset spacer deposition: thickness ~ BLE junction depth
Ultra-shallow BLE implant
BL-spacer deposition
Deep BL implant and anneal

Contact formation

FIGURE 1.21
The major technology steps to integrate sub-90 nm split-gate NOR-flash memory cells in a
standard CMOS technology. (From S.K. Saha, Design considerations for sub-90 nm split-gate
Flash memory cells, IEEE Trans. Electron. Devices, vol. 54, no. 11, pp. 3049–3055, November 2007.
With permission.)

1.5.2  TCAD in Fabrication Technology Development (TD)

The coupled process and device CAD flow as shown in Figure 1.13 is used in
IC fabrication TD. Typically, in the semiconductor industry, the next-generation
IC fabrication technology is derived by scaling the current technology. In
this case, the current generation fabrication process flow with appropriate
modifications is used as the initial guess to optimize the process recipe of the
next-generation technology. As shown in Figure 1.13, the initial guess process
recipe is iteratively optimized using coupled process and device CAD to the
target achievable device specifications; then the compact model parameters
are extracted from the simulated device characteristics; and finally, circuit
CAD is used to analyze the circuit performance. Figure 1.13 also shows that
for accurate prediction of device and circuit performance, calibrated physical
models are essential. Also, the calibration database with experimental dop-
ing profiles under various processing conditions and device characteristics
Introduction to Technology Computer Aided Design 33

are essential to validate the simulation results in each step of the optimiza-
tion process.
Besides the conventional TD approach described above, the initial guess
process recipe can be efficiently obtained by “reverse modeling” as shown in
Figure 1.1. As we discussed in Section 1.3, the ultimate motivation for TCAD
is to extract circuit design parameters to enable designers to predict circuit
performance of the target technology. In the TCAD flow in Figure 1.13, the
circuit design parameters are generated by optimizing the initial guess
process recipe of the current generation technology using coupled process
and device CAD. However, for exploratory devices, the current generation
technology does not exist; therefore, the initial process flow and recipe are
obtained by reverse simulation flow (e.g., circuit CAD to process CAD), as
shown in Figure 1.1. Because the ultimate goal of the new technology genera-
tion is to predict circuit performance, circuit/product specific process recipe
will ensure the target circuit performance. The basic simulation flow for the
product-specific IC process design is shown in Figure 1.22. The initial guess
process recipe is generated by reverse engineering from the target product
specifications in three sequential steps: (1) generation of device models using
circuit simulation as shown in Figure 1.22(a); (2) generation of doping profiles

Initial Guess
Device Models Revise
Device
Models
Circuit Simulation

Generate
Product Specifications
Target Product
Specifications

No
Check?

Yes
Optimized Device Models

Doping Profiles
Optimization

(a)

FIGURE 1.22
Flowchart for the generation of initial guess process recipe using three-step approach: (a) optimi-
zation of device models to the target product specifications; (b) optimization of process profiles to
the target device models; (c) optimization of process recipe to the target process profiles. (From S.
Saha, Technology CAD for integrated circuit fabrication technology development and technology
transfer, Proc. SPIE, vol. 5042, pp. 63–74, July 2003. With permission.) (continued)
34 Technology Computer Aided Design: Simulation for VLSI MOSFET

Initial Guess
Doping Profiles
Revise
Initial

Calibration
Database
Guess
Model Device Simulation

Extract
Device Models
Device Models
Optimized

No
Check?

Yes
Optimized Doping Profiles

Generate Process
Recipe

(b)

Initial Guess
Process Recipe
Revise
Initial
Calibration
Database

Guess
Model

Process Simulation

Generate
Doping Profiles
Optimized
Impurities

No
Check?

Yes
Optimized Recipe

Process
Optimization

(c)

FIGURE 1.22
(continued) Flowchart for the generation of initial guess process recipe using three-step
approach: (a) optimization of device models to the target product specifications; (b) optimiza-
tion of process profiles from the target device models; (c) optimization of process recipe to
the target process profiles. (From S. Saha, Technology CAD for integrated circuit fabrication
technology development and technology transfer, Proc. SPIE, vol. 5042, pp. 63–74, July 2003.
With permission.)
Introduction to Technology Computer Aided Design 35

within the device using device CAD as shown in Figure 1.22(b); and (3) gen-
eration of process recipe using process CAD as shown in Figure 1.22(c). This
initial guess product-specific process recipe can then be further optimized
using coupled process and device CAD as shown in Figure 1.13 to generate
the final process flow and device specifications.

1.6  Benefit of TCAD in TD Projects

TCAD is widely used in advanced IC fabrication TD to optimize IC devices
and fabrication processes through critical analysis and detailed understand-
ing of process, device, and circuit simulation data. The TCAD tools that accu-
rately predict the process and device characteristics of the anticipated wafer
fabrication technology have shown great promise in nanoscale device and
advanced IC manufacturing TD. Therefore, TCAD has become indispens-
able to reduce the development cycle time and cost of advance IC fabrication
technology and products [1–5]. TCAD tools offer manufacturing and devel-
opment engineers vast improvements in flexibility, innovation, efficiency,
and customer responsiveness [1].
In Section 1.3, we established the motivation and importance of TCAD in
IC device and process architecture. It is obvious that the knowledge gained
by TCAD is impossible to quantify. However, for industrial applications it
is essential to quantify the benefit of TCAD in reducing TD cycle time and
cost [1,5]. By conducting a survey of TCAD users, International Technology
Roadmap for Semiconductors (ITRS) reported about 32% reduction in devel-
opment time and about 30% in development cost by the appropriate use of
TCAD [2]. Though this demonstrates high relevance and potential for the
industrial use of TCAD, a survey-based benefit assessment is not adequate to
undertake a TCAD-based development project in the industry. Therefore, a
quantitative model to assess the benefit of TCAD use in a development proj-
ect is crucial for project managers.
In 1999, the basic formulations of a quantitative model to compute the
benefit of TCAD use in IC development were reported [1] and the detailed
analytical model to compute the benefit of TCAD was reported in 2010 [5].
In these reports, a set of realistic assumptions is used to derive a set of
mathematical expressions to compute the cycle time and cost benefit of a
TCAD-based project compared to that of the trial-and-error experimentation
or “conventional” approach. The key assumption of this model is that the
TCAD tools accurately predict the process and device characteristics of the
target wafer fabrication technology. In order to develop a realistic analyti-
cal model to compute the benefit of TCAD over the conventional approach,
a typical IC fabrication TD project is divided into three phases (ϕ): phase 1,
generation of initial guess process recipe; phase 2, process optimization to
generate process and device specifications; and phase 3, evaluation of process
36 Technology Computer Aided Design: Simulation for VLSI MOSFET

manufacturability. According to this model, the reduction in the develop-

ment cycle time, Δt, and cost, ΔC, on a project by TCAD use compared to the
conventional approach is described by

t ≅ Ftconv (1.1)

 F 
C ≥ Cwfr  + ( 1 + ROI ) n − Ctcad (1.2)
 1− ρ 

C ≥ Cwfr [ F + (1 + ROI )(1 − ρ)]A ⋅ m ⋅ np − Ctcad (1.3)


where the model parameters in Equations (1.1)–(1.3) are as follows: F is the
development cycle time reduction factor by a TCAD-based project compared
to a conventional poject; tconv is the conventional TD time without using
TCAD; Cwfr is the cost of processing a single wafer-lot in the fab; ρ is the
fraction of the conventional TD wafers used in a TCAD-based project; ROI
is the return on investment from IC sale; Δn is the reduction in the number
of wafer-lots in the fab by using TCAD; Ctcad is the total cost of implementa-
tion of CAD infrastructure; m is the total number of iterations required to
optimize a technology in each phase of a TD project and is assumed to be the
same for both conventional and TCAD-based processes; np is the number of
process-control variables p (e.g., ion implant) and defines the complexity of
an IC fabrication technology; and A = nx ny φ/wn is the model parameter that
depends on the number of project phases ϕ, the split conditions of implants
(e.g., energy nx and dose ny), and the number of wafers in a wafer-lot wn.
By using the appropriate values of the parameters in Equations (1.1) and
(1.2) or (1.1) and (1.3) for the TCAD tools that accurately predict the pro-
cess and device characteristics of the target wafer fabrication technology,
the above analytical model provides a reduction in the TD cycle time of
about 67% with multimillion dollar cost savings compared to the conven-
tional approach [1,5].

1.7 Summary
This chapter presents the mission and scope of extended technology CAD in
IC process modeling and device performance analysis. A brief history of the
evaluation of device and process CAD during the past four decades leading
to the commercialization of TCAD software is described. The motivation for
TCAD use is outlined with a few typical examples. A brief outline of TCAD
flow including generation of robust simulation structure and physical model
calibration for accurate IC process and device simulation is presented. A few
Introduction to Technology Computer Aided Design 37

examples of typical TCAD application, especially, in studying the feasibility

of exploratory devices for the next-generation fabrication technology are dis-
cussed. Finally, an analytical cost model to compute the benefit of TCAD use
in saving IC TD cycle time and cost over the conventional trial-and-error-
experimentation based TD project is discussed.

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2
Basic Semiconductor and Metal-Oxide-
Semiconductor (MOS) Physics

Swapnadip De

CONTENTS
2.1 Introduction................................................................................................... 47
2.2 Band Formation Theory of Semiconductor............................................... 48
2.2.1 Band Formation in Silicon............................................................... 51
2.2.2 Band Structure in Compound Semiconductor............................. 52
2.3 Concept of Effective Mass...........................................................................54
2.4 Basic Semiconductor Equations.................................................................. 55
2.4.1 Gauss’s Law....................................................................................... 56
2.4.2 Poisson’s Equation............................................................................ 56
2.4.3 Boltzmann Transport Equation...................................................... 57
2.5 Carrier Transport.......................................................................................... 58
2.5.1 Carrier Drift....................................................................................... 59
2.5.2 Diffusion Current............................................................................. 61
2.5.3 Total Drift-Diffusion Current..........................................................64
2.5.4 Einstein Relation...............................................................................64
2.6 Carrier Recombination and Generation.................................................... 66
2.7 Continuity Equation and Solution............................................................. 68
2.8 Mobility and Scattering............................................................................... 72
2.9 Different Distribution Laws........................................................................ 74
2.9.1 Fermi-Dirac Distribution................................................................. 74
2.10 Semiconductor Device Modeling...............................................................77
2.10.1 Introduction.......................................................................................77
2.10.2 Shockley-Read-Hall (SRH) Generation/Recombination
Model............................................................................................... 78
2.10.3 Simple Recombination-Generation Model.................................... 82
2.10.4 Impact Ionization Model..................................................................83
2.10.5 Mobility Modeling............................................................................84
2.11 Introduction to MOS Transistor.................................................................. 85
2.12 Structure and Symbol of MOSFET............................................................. 85
2.13 Basic Operation of MOSFET........................................................................ 87
2.13.1 Operation of MOSFET with Zero Gate Voltage............................ 87
2.13.2 Operation of MOSFET with a Positive Gate Voltage.................... 87

45
46 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.13.3 Effect of a Small VDS.......................................................................... 89

2.13.4 Operation of MOSFET as VDS Is Increased.................................... 89
2.14 Threshold Voltage of MOSFET................................................................... 91
2.14.1 Accumulation of Holes..................................................................... 92
2.14.2 Depletion............................................................................................ 93
2.14.3 Inversion............................................................................................. 94
2.14.4 Surface Potential............................................................................... 94
2.15 Flat-Band Voltage: Effect of Real Surfaces................................................. 99
2.15.1 Equalization of the Fermi Levels.................................................... 99
2.15.2 Oxide Charges................................................................................. 100
2.15.3 Interface Traps................................................................................. 101
2.15.4 Flat-Band Voltage............................................................................ 101
2.16 Expression of Threshold Voltage.............................................................. 102
2.17 I–V Characteristics of MOSFET................................................................ 103
2.17.1 Gradual Channel Approximation................................................ 103
2.18 Depletion MOSFET..................................................................................... 112
2.19 Transconductance (gm)............................................................................... 113
2.20 Channel Length Modulation..................................................................... 114
2.21 Substrate Bias Effects.................................................................................. 119
2.22 MOS Transistor as a Switch....................................................................... 120
2.23 MOSFET Capacitance................................................................................. 121
2.23.1 Overlap Capacitance....................................................................... 121
2.23.2 Channel Capacitance...................................................................... 122
2.23.3 Junction Capacitances.................................................................... 124
2.23.4 Different MOS Capacitors Together............................................. 125
2.23.5 Summary of MOS Capacitances................................................... 125
2.23.6 Interconnect Capacitances............................................................. 127
2.24 Moore’s Law................................................................................................. 127
2.25 Introduction to Scaling.............................................................................. 128
2.26 Constant Field Scaling............................................................................... 128
2.27 Constant Voltage Scaling........................................................................... 129
2.28 Why Constant Voltage Scaling Is More Useful than Constant
Field Scaling................................................................................................. 129
2.29 ITRS Roadmap for Semiconductors......................................................... 129
2.30 Different Groups of MOSFETs.................................................................. 130
2.31 Short-Channel Effects of MOSFET........................................................... 132
2.32 Reduction of the Effective Threshold Voltage........................................ 132
2.33 Hot Electron Effects.................................................................................... 135
2.34 Avalanche Breakdown and Parasitic Bipolar Action............................. 136
2.35 DIBL (Drain-Induced Barrier Lowering)................................................. 137
2.36 Velocity Saturation in MOSFET................................................................ 138
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 47

2.37 Mobility Degradation................................................................................. 140

2.37.1 Vertical Electric Field Mobility Degradation.............................. 140
2.37.2 Surface Scattering........................................................................... 140
2.37.3 Horizontal Electric Field Mobility Degradation......................... 141
References.............................................................................................................. 142

2.1 Introduction
The invention of the transistor in 1947 started the exponential growth of an
industry that is now, some decades later, a several hundred billion dollar
industry. The first bipolar transistor was announced in December 1947 by
William Shockley, John Bardeen, and Walter Brattain at Bell Labs. The first
metal-oxide-semiconductor (MOS) transistor and the first integrated circuits
were demonstrated in the early 1960s. From that time on the development in
the field of microelectronics was impressive. The integration density grew
exponentially. Not only has the integration density been steadily growing,
but pressure on the industry to deliver in short time-to-market has also been
increasing, leaving minimal research and development times for new tech-
nology nodes. This has led to intense efforts in the field of numerical simula-
tion of the semiconductor manufacturing process and the resulting device
structure, called technology computer aided design (TCAD). TCAD can
reduce the number of test cycles with real semiconductor devices and drasti-
cally increase the possibilities to vary process parameters as doping concen-
trations, device geometries, materials, and their composition to a minimum.
Here, TCAD gives the opportunity to analyze the effect of process variation
within hours instead of weeks for real processing.
The fundamentals of semiconductors are typically found in textbooks dis-
cussing quantum mechanics, electro-magnetics, solid-state physics, and sta-
tistical thermodynamics. The purpose of this chapter is to review the physical
concepts, which are needed to understand the fundamentals of semiconduc-
tor devices. We start from the concepts of energy bands, energy band gaps,
and the density of states in an energy band. We then discuss the impor-
tant concept of effective mass. The analysis of most semiconductor devices
requires some knowledge of Gauss’s law and Poisson’s equation, which are
explained briefly. We then look at transport in semiconductors through the
semi-classical Boltzmann transport equation (BTE). Two carrier transport
mechanisms—the drift of carriers in an electric field and the diffusion of
carriers due to a carrier density gradient—will be discussed. Recombination
mechanisms and the continuity equations are then combined into the diffu-
sion equation. We then present the drift-diffusion model, which combines all
the essential elements discussed in this chapter. The rapid developments in
semiconductor technology over the past 20 years have caused huge interest
48 Technology Computer Aided Design: Simulation for VLSI MOSFET

in device modeling. The need to understand the detailed operation of very

large scale integrated (VLSI) devices and compound semiconductor devices
has meant that device modeling now plays a crucial role in modern tech-
nology. The main focus is on the phonon transition or Shockley-Read-Hall
mechanism. It is of special interest for modeling the carrier generation and
recombination at silicon/dielectric interface traps that are caused by negative
bias temperature instability. Mobility modeling is also discussed in brief.
The operation and types of the MOSFET (metal-oxide-semiconductor field-
effect transistor) or MOS transistor are discussed in detail. The steady down-
scaling of MOS transistor dimensions over the past two decades obeying
Moore’s law is discussed along with the short-channel effects in detail.

2.2  Band Formation Theory of Semiconductor

The concept of electronic energy bands provides the basis for the clas-
sification of solids as good conductors, insulators, or semiconductors.
Quantum physics describes the state of electrons in an atom according
to the four-fold scheme of quantum numbers. The quantum number sys-
tem describes the allowable states the electrons may assume in an atom.
Individual electrons may be described by the combination of quantum
numbers they possess. Electrons may change their status, given the pres-
ence of available spaces for them to fit, and available energy. Because shell
level is closely related to the amount of energy that an electron possesses,
“leaps” between shell (and even subshell) levels require the transfer of
energy. If an electron is to move into a higher-order shell, it requires that
an additional energy be given to the electron from an external source.
Conversely, an electron “leaping” into a lower shell gives up some of its
energy, the expended energy manifesting as heat and sound released
upon impact.
Leaps between different shells require a substantial exchange of energy,
while leaps between subshells or between orbitals require lesser exchanges.
When atoms combine to form substances, the outermost shells, subshells,
and orbitals merge, providing a greater number of available energy levels for
electrons to assume. When large numbers of atoms exist in close proximity
to each other, these available energy levels form a nearly continuous band
wherein electrons may transit.
The width of these bands and their proximity to existing electrons determine
how mobile those electrons will be when exposed to an electric field. In metallic
substances, as in Figure 2.1, empty bands overlap with bands containing elec-
trons, meaning that electrons may move to what would normally be a higher-
level state with little or no additional energy imparted. Thus, the outer electrons
are said to be “free,” and ready to move at the beckoning of an electric field [1].
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 49

Band overlap in metals

Conduction band
Overlap of the two
Valence band bands
Electrons move from
valence to conduction
band freely

FIGURE 2.1
Energy band structure of metal.

Band overlap will not occur in all substances, no matter how many atoms
are in close proximity to each other. In some substances, as in Figure 2.2, a
substantial gap remains between the highest band containing electrons (the
so-called valence band) and the next band, which is empty (the so-called con-
duction band). As a result, valence electrons are “bound” to their constituent
atoms and cannot become mobile within the substance without a significant
amount of imparted energy [2–4]. These substances are electrical insulators.
Materials that fall within the category of semiconductors have a narrow
gap between the valence and the conduction bands, as shown in Figure 2.3.
Thus the amount of energy required to motivate a valence electron into the
conduction band where it becomes mobile is quite low.

Insulator band gap

Conduction band

Large band gap

Valence band
Very high energy
required for electron to
enter conduction band

FIGURE 2.2
Energy band structure in insulator.
50 Technology Computer Aided Design: Simulation for VLSI MOSFET

Semiconductor band gap

Conduction band

Small band gap

small energy required
Valence band for electron to enter
conduction band

FIGURE 2.3
Energy band structure in semiconductor.

At low temperatures, there is little thermal energy available to push valence

electrons across this gap, and the semiconductor material acts as an insula-
tor. At higher temperatures, the ambient thermal energy becomes sufficient
to force electrons across the gap, and the material will conduct electricity.
The free electron model of a metal is used to explain the photoelectric effect.
This model assumes that electrons are free to move within the metal but are
confined to the metal by potential barriers, as illustrated by Figure 2.4. The
minimum energy needed to extract an electron from the metal equals
qΦM = work function. This model is used for analyzing metals but does not
work well for semiconductors because the effect of the periodic potential due
to the atoms in the crystal has been ignored. In semiconductors, the energy
levels are grouped into bands. The behavior of electrons at the top and bot-
tom of such a band is similar to that of a free electron [5]. However, the elec-
trons are affected by the presence of the periodic potential. The combined
effect of the periodic potential is included by adjusting the mass of the elec-
tron to a different value. This mass will be referred to as the effective mass.

Minimum energy
needed to extract an
Work
function electron from metal

Electrons move
freely within metal
L
x

FIGURE 2.4
The free electron model of a metal.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 51

2.2.1  Band Formation in Silicon

A schematic representation of an isolated Silicon (Si) atom is shown in
Figure  2.5(a). In Si crystal each isolated Si atom has an electronic structure
1s22s22p63s23p2. Ten out of fourteen Silicon atom electrons occupy energy
levels close to the nucleus. The four remaining valence electrons are weakly

n = 2 shell has 8 Si
electrons 14 e–

n = 1 shell has 2
electrons

Band Formation in Silicon

(a)

4N states 6N states
Energy of Electron

3p state

Band gap
3s state

4N states 2N states
8N states

Equilibrium Spacing
(b)

FIGURE 2.5
Energy band formation in silicon.
52 Technology Computer Aided Design: Simulation for VLSI MOSFET

bound, and these electrons are involved in chemical reactions [6]. They deter-
mine the chemical and electrical properties of Silicon (i.e., 14 electrons can
be distributed in 18 states—two 1s, two 2s, six 2p, two 3s, and six 3p states). If
we consider N atoms, there will be 2N, 2N, 6N, 2N, and 6N states of type 1s,
2s, 2p, 3s, and 3p, respectively. Figure 2.5(b) shows the band splitting of the
silicon. Because the first two shells are completely filled and tightly bound to
the nucleus, we have to consider n = 3 level for valence electron. The 3s states
corresponding to n = 3 and l = 0 contain two quantum states per atom. This
state will contain two electrons at T = 0 K. The 3p states corresponding to n =
3 and l = 1 contain six quantum states per atom. This state will contain two
remaining electrons of the individual Si atom (i.e., the band of ‘3s-3p’ levels
contain 8N available states). When the inter-atomic spacing decreases, these
energy levels split into bands, beginning with the outer (n = 3) shell. The 3s and
3p bands merge into a single band composed of a mixture of energy levels.
At the equilibrium inter-atomic distance, the bands again split, having four
quantum states in the lower band and four quantum states in the upper band.
At T = 0 K electrons will reside at the lowest energy state, thus the lower band
(valence band will be full) and the energy states in the upper band (conduc-
tion band) will be empty. The band-gap energy Eg is the width of the energy
between the top of the valance band and the bottom of the conduction band.
In other words, for inter-atomic spacing, this band splits into two bands
separated by an energy gap Eg. The upper band (the conduction band) con-
tains 4N states, as does the lower band (the valence band). The energy gap
contains no allowed energy levels for electrons to occupy, thus it is called
forbidden band, Eg. The lower bands (1s, 2s, 2p) are fully occupied. But 4N elec-
trons originally in n = 3 shells (2N in 3s and 2N in 3p states) must occupy
states in the valence band or the conduction band in the crystal. At 0 K the
electrons will occupy the lowest energy states available to them. In the case
of Si crystal, there are exactly 4N states in the valence band available to the
4N electrons. Thus at 0 K every state in the valence band is totally filled,
while the conduction band is empty.

2.2.2  Band Structure in Compound Semiconductor

A particularly interesting and useful feature of the III–IV compounds is the
ability to vary the mixture of elements. For example, in the ternary com-
pound AlGaAs, it is possible to vary the composition of the ternary alloy
by choosing the fraction of Al or Ga atoms. It is common to represent the
composition by assigning subscripts to the various elements. For example
AlxGa1–xAs refers to a ternary alloy in which a fraction of X of Al atoms and
(1 – X) of Ga atoms are present. X can vary from 0 to 1, thus varying the
optical and electronic properties. The composition Al0.3Ga0.7As has 30% of
aluminum and 70% Ga atoms [7]. GaAs is a direct band-gap semiconductor
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 53

X
L

1.43 eV

k
GaAs
Direct Band Gap Material

L
X

2.36 eV

k
AlAs
Indirect Band Gap Material

FIGURE 2.6
Energy band diagram in GaAs and AlAs.

material with a band gap of 1.43 eV. The direct (k = 0) conduction band mini-
mum is denoted as λ. The lowest-lying indirect minimum is denoted as
L and the other as X. In GaAs, as shown in Figure 2.6 (top), there are two
higher-lying indirect minima, but these are sufficiently far above λ and few
electrons reside there.
In AlAs shown in Figure  2.6 (bottom), the direct transition minimum is
much higher than the indirect minimum and so this material is an exam-
ple of indirect band-gap semiconductor with a band gap of 2.16 eV at room
temperature. In the ternary compounds, all of these conduction band min-
ima move up relative to the valence band, as the composition X varies from
0(GaAs) to 1(AlAs). However, the indirect minimum moves up less than the
others when the compositions are above 38 percent Al. Also here this indirect
minimum is actually the lowest-lying conduction band. AlGaAs is a direct
band-gap semiconductor when X = 0 to X = 0.38 and is an indirect semicon-
ductor for higher Al mole fractions. GaAs1–xPx is generally similar to AlGaAs,
which is also a direct band-gap semiconductor up to X = 0.45. This material is
54 Technology Computer Aided Design: Simulation for VLSI MOSFET

often used in light-emitting diode (LED) fabrication. Light emission is most

efficient for direct materials, in which the electron can drop to the valence
bands without changing k and therefore the momentum. By changing X, we
can change the color of the light by changing the band gap [8].

2.3  Concept of Effective Mass

The effective mass of a semiconductor is obtained by fitting the actual E-k dia-
gram around the conduction band minimum or the valence band maximum
by a paraboloid shown in Figure 2.7. While this concept is simple enough,
the issue turns out to be substantially more complex due to the occasional
anisotropy of the minima and the maxima. A single electron is assumed to
travel through a perfectly periodic lattice. The parameter m* called the effec-
tive mass takes into account all the internal forces in the lattice. Electrons
are considered as classical particles whose motions are governed by classical
mechanics when all the internal forces are taken care of through the concept
of the effective mass.
Now classical laws like F = m* a are applied, where a is now directly related
to external force. We know the electron momentum is p = mv = ℏk, where the
symbols have their usual significances. Thus,

1 1 p2 1 2 2
E= mv 2 = = k (2.1)
2 2 m 2 m

FIGURE 2.7
Example of an E-K diagram.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 55

The electron energy is parabolic with wave vector k.

dE  2 k p
= =
dk m m
(2.2)
1 dE p
= =v
 dk m

where v is the velocity of particle. dE

dk
is related to the velocity of the particle.
2
The electron mass is inversely related to ddkE2 . So

d 2E  2
=
dk 2 m
(2.3)
1 d 2E 1
=
 2 dk 2 m

For a free electron the mass is a constant, so d 2E is a constant. Also
dk 2

2 mE
k=


For a free electron total energy E is equal to the kinetic energy. So,

1 
2 m  mv 2 
2 mE 2  p
= = =k
2  2
 (2.4)

p2 k 2 2
E= =
2m 2m
The E-k relationship is parabolic. The effective mass is a parameter that
relates the quantum mechanical results to the classical force equations.

2.4  Basic Semiconductor Equations

The analyses of most semiconductor devices include the calculation of the
electrostatic potential within the device as a function of the charge distri-
bution [9]. Electromagnetic and electrostatic theories are used to obtain the
potential. Short descriptions of the necessary tools, namely Gauss’s law,
Poisson’s equation, and the Boltzmann transport equation, are given below.
56 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.4.1  Gauss’s Law

Gauss’s law gives a relationship between the charge density, ρ(x), and the
electric field, E(x). Considering no time-dependent magnetic fields, the one-
dimensional equation is given by

dE( x) ρ( x)
= (2.5)
dx ε

Integrating the above equation, the electric field for 1D charge distribution
is given as

x2
ρ( x)
E( x2 ) − E( x1 ) =
∫ ε
dx (2.6)
x1

In three dimensions, application of Gauss’s law gives the divergence of the
electric field:

ρ( x , y , z)
E( x , y , z) = (2.7)
ε

2.4.2  Poisson’s Equation

The electric field is defined as the negative gradient of the electrostatic potential,
Ψ(x), or in one dimension, as the negative derivative of the electrostatic potential:

dΨ( x)
= −E( x) (2.8)
dx
The electric field starts from a higher-potential region and points toward a
lower-potential region.
Integration of the electric field gives the expression of potential as

x2

∫
Ψ( x2 ) − Ψ( x1 ) = − E( x) dx (2.9)
x1

Putting the expression of the electric field from Equation (2.8) into Equation
(2.5), the relation between the charge density and the potential is obtained as

d 2 Ψ( x ) ρ( x)
2
=− (2.10)
dx ε

This equation is referred to as Poisson’s equation.

Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 57

In three dimensions, the potential gradient is given by

∇Ψ(x,y,z) = −E(x,y,z) (2.11)

Combining Equations (2.11) and (2.7), the general form of Poisson’s equation
is given by

2 ρ( x , y , z)
Ψ ( x , y , z) = − (2.12)
ε

2.4.3  Boltzmann Transport Equation

The Boltzmann transport equation (BTE) is a semi-classical approach to car-
rier transport. It describes the evolution of the trajectory of a particle by using
a combination of Newtonian mechanics and quantum probabilistic scatter-
ing rates. The former account for the classical motion of the particle, and
the latter for dissipative processes from one energy state to another. Unlike
quantum transport, the energy eigen-states are not determined during the
solution but are pre-computed by an independent method. The BTE can be
derived from the Liouville-von Neumann transport equation under simpli-
fying assumptions and ignoring all phase coherence [10,11]. A good intro-
duction to the BTE, its physical parameters, and its application for device
simulation can be found in [10].
For deriving the BTE a phase space is considered about the points (x, y, z, px, py,
pz) as in [12], where (px, py, pz) are the angular components of p-type orbitals. The
particles entering the considered phase space in time dt are equal to the number of
particles in ( x − vx dt , y − vy dt , z − vz dt , px − Fx dt , py − Fy dt , pz − Fz dt) at some earlier
dt time, where F is the external force on a particle and (Fx, Fy, Fz) are the respective
directional components of the force. Let the number of particles per unit volume in
the phase space be represented by f(x, y, z, px, py, pz). The change in this distribution
function in time dt as a result of the external force and the movement of particles is
given from [12] as df = f ( x − vx dt , y − vy dt , z − vz dt , px − Fx dt , py − Fy dt , pz − Fz dt)
− f ( x , y , z, px , py , pz ).
The time derivative of this function from Taylor series is given by
df
dt = −( F p f + v r f ). However, if the scattering or collision of particles in the
phase space due to particles from outside is considered, the time derivative
takes the form

df ∂f
= −( F p f +v r f ) + s(r , p , t) + (2.13)
dt ∂t collision

∂f
where ∂t collision is the rate of change of distribution function due to collisions
from other particles outside the phase space; s(r,p,t) is the term accounting
for the generation-recombination processes; s(r,p,t) stands for the probability
58 Technology Computer Aided Design: Simulation for VLSI MOSFET

of having generation-recombination at a position r at time t having particle

momentum p. If particle momentum is replaced by crystal momentum the
time derivative of f is given by

∂ f (r , k , t) 1 1 ∂f
+ F k f (r , k , t) + k E( k ) r f (r , k , t) = s(r , k , t) + (2.14)
∂t   ∂t
collision
This equation is the Boltzmann transport equation or continuity equation in
6D-phase space.
Because the BTE does not include phase information, it is simpler to
solve than quantum transport. There are several methods of solution of
BTE. Among the earlier approaches was the Legendre polynomial expan-
sion [13]. Such methods did not achieve much success because the drastic
approximations used to simplify the problem and to obtain analytical solu-
tions were valid only in the simplest cases and not for any practical devices.
Other earlier methods were based on an iterative integration technique that
worked well only for low-field transport [14]. In the 1960s, a method based
on the Monte Carlo technique was suggested as a means to solve the BTE.
It has achieved the most success among all other methods so far, due to its
ease of programming, ease of including a variety of physical effects in the
same framework, simple numerical algorithms, and low memory require-
ments (review in [15]). The Monte Carlo technique can simulate transport
in complicated device geometries with complicated band structures [16,17].
However, the Monte Carlo technique suffers from several fundamental dis-
advantages (i.e., statistical noise in low-bias near-equilibrium conditions).
These conditions involve events that occur at exponentially decreasing
probabilities and cannot be detected by a stochastic method that has a well-
known convergence only for nearly uniform distributions. Some methods
have been suggested to “enhance” the exponential tails of distribution
functions so that they can be detected and that has provided some respite
[18]. However, a stochastic method inherently has lesser accuracy than a
direct numerical method with controlled discretization error. Among other
significant methods to solve the BTE, the Cellular Automata methods, the
Scattering matrix method, and the Spherical Harmonic method must be
mentioned.

2.5  Carrier Transport

Current in a semiconductor is defined as the rate of flow of charge carriers.
The flow of charge carriers called carrier drift is due to an externally applied
electric field. The carriers move from a higher carrier density region to a
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 59

lower density region. This movement of carriers called diffusion is due to the
thermal energy. The total current in a semiconductor is equal to the sum of
the drift and the diffusion currents.
When an electric field is applied to a semiconductor, the electrostatic
force causes the carriers to first accelerate due to the electrostatic field. Then
due to collisions with impurities a constant average velocity, v, is reached.
Mobility is defined as the average drift velocity per applied electric field.
Saturation velocity is reached at high electric fields. Carriers along the
semiconductor surface are subjected to surface scattering as a result of
which the mobility degrades. Due to variation in doping density, a density
gradient is created in the semiconductor due to which diffusion of carriers
takes place.
Both drift and diffusion mechanisms are related because the same parti-
cles and scattering mechanisms are involved. This leads to the Einstein rela-
tion which is a relationship between the mobility and the diffusion constant.

2.5.1  Carrier Drift

The drifting of a carrier in a semiconductor on application of an externally
applied electric field, E, is shown in Figure 2.8. Due to the applied bias the
carriers move with an average velocity, v [1].
The current flowing through the semiconductor can be expressed as the
total charge divided by the time taken to travel from one electrode to the
other—that is,

Q
I = Q/tr = (2.15)
L/v

v
E

FIGURE 2.8
Drift of a carrier due to an applied electric field.
60 Technology Computer Aided Design: Simulation for VLSI MOSFET

where tr is the transit time of carrier, moving with velocity, v, covering the
distance L. The current density, J, can be expressed in terms of the charge
density ρ as

Q
J = I/A = v = vρ (2.16)
AL
Considering negatively charged electrons, the current density is given by

J = −qnv (2.17)
Considering positively charged holes, it is given by

J = qpv (2.18)
where n and p are the semiconductor electron and hole density.
Due to scattering, the carriers move around the semiconductor randomly
with a constantly changing path instead of a straight-line path along the
electric field. This occurs when no electric field is applied externally and is
due to the thermal carriers. Electrons in a non-degenerate electron gas have
a thermal energy of kT/2 per particle per degree of freedom [1,19]. The typical
thermal velocity is around 107 cm/s at room temperature, which is greater
than the drift velocity in semiconductors. The movement of carriers in the
semiconductor in the presence and absence of an electric field is shown in
Figure 2.9.
When no external field is applied, the carriers move randomly with rapidly
changing directions. On application of an external electric field, the holes
move in the direction of the applied field, while the electrons move in the
opposite direction.
The force on a carrier can be obtained from Newton’s law.

d〈v〉
F = ma = m (2.19)
dt

E≠0

E=0

FIGURE 2.9
Random motion of carriers in a semiconductor with and without an applied electric field.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 61

The force equals the difference between the electrostatic force and the scat-
tering force. The scattering force equals the ratio of the momentum of the
carriers to the average time between collisions, τ—that is,

〈v〉
F = qE − m (2.20)
τ

where q is the charge of a carrier particle.

Equating Equations (2.19) and (2.20):

d〈v〉 〈v〉
qE = m +m (2.21)
dt τ

The average particle velocity can be obtained from Equation (2.21). In steady
state, the carrier particles after acceleration reach a constant velocity. In
such a condition, the velocity of the particle is proportional to the externally
applied electric field. The mobility is defined as the average velocity per
applied field.

〈 v 〉 qτ
µ= = (2.22)
E m

Mobility of a semiconductor particle is small when the mass is large and the
time between collisions is small. In terms of mobility, the drift current den-
sity for electrons may be expressed as

J n = qnµ nE (2.23)

Similarly, the drift current density for holes may be expressed as

J p = qpµ pE (2.24)

considering the mass, m, of the semiconductor particle. But the effective
mass, m*, rather than the free particle mass, m, must be considered for taking
into account the effect of the periodic potential of the atoms:

qτ
µ= (2.25)
m*

2.5.2  Diffusion Current

Semiconductor devices fall into two broad categories: majority carrier
devices and minority carrier devices. In the majority carrier devices, cur-
rent flow is dominated by electric field driven current. In minority carrier
devices, the current flow is dominated by the diffusion effects. Whenever
62 Technology Computer Aided Design: Simulation for VLSI MOSFET

there is a gradient in the concentration of mobile particles, the particles dif-

fuse from the regions of high concentration to the regions of low concentra-
tion. In addition to drift, this is the alternate mechanism that can lead to
current flow. Suppose a drop of ink falls into a glass of water. Introducing a
high local concentration of ink molecules, the drop begins to “diffuse”—that
is, the ink molecules tend to flow from a region of high concentration to
regions of low concentration. This mechanism is called diffusion. A similar
phenomenon occurs if charge carriers are dropped into a semiconductor so
as to create a non-uniform density. In the absence of an electric field, the car-
riers move toward regions of low concentration, thereby carrying an electric
current so long as the non-uniformity is sustained. Diffusion is therefore
distinctly different from drift.
The derivation is based on the idea that carriers at non-zero temperature
(Kelvin) have an additional thermal energy equal to kT/2 per degree of free-
dom. Thermal energy drives the diffusion process. At T = 0 K there is no
diffusion. Because thermal energy is random, the average value needs to be
considered for deriving the diffusion current for a one-dimensional semi-
conductor [1].
Let the average values of the thermal velocity be vth, the collision time τ,
and the mean free path l. The thermal velocity is the average velocity of the
semiconductor carriers in the positive or the negative direction. The collision
time is the time taken by the carriers to move with the same velocity before
a collision occurs with another carrier. The mean free path is the average
length a carrier moves between collisions. From this basic concept the ther-
mal velocity is given by

vth = l/τ (2.26)

In order to find an expression for diffusion current density, a variable car-
rier density n(x) is considered in Figure  2.10. The carrier densities of two

n(–l)
n(+l)

–l 0 +l x

FIGURE 2.10
Carrier density profile used to derive the diffusion current expression.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 63

points x = –l and x = l are considered as in [1], which are one mean free path
away from x = 0. The flux due to the semiconductor carriers at x = 0 due to
carriers moving from x = –l is given by

1
ηleft−right = vth n(−l) (2.27)
2

The “1/2” term is because only half of the carriers move to the left while the
other half moves to the right. The flux due to the semiconductor carriers at
x = 0 due to carriers moving from x = +l is given by

1
ηright−left = vth n(+l) (2.28)
2

The total flux of carriers at x = 0 may be obtained by subtracting the flux due
to carriers moving from right to left from the flux of carriers moving from
left to right:

1
η = ηleft−right − ηright−left = vth {n(−l) − n(+l)} (2.29)
2

Considering small mean free path, the carrier density derivative may be
obtained as

n(+l) − n(−l) dn
η = −lvth = − vthl (2.30)
2l dx

The diffusion current density for electrons may be obtained by multiplying

the flux with the charge of an electron:

dn
J n = − qη = qvthl (2.31)
dx

Let the diffusion constant, Dn , be equal to the product of thermal velocity, vth,
and the mean free path, l:

dn
J n = qDn (2.32)
dx

For holes the diffusion current density is given as

dp
J p = − qDp (2.33)
dx
64 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.5.3  Total Drift-Diffusion Current

Based on the concepts derived in the previous sections, we can now establish
the drift-diffusion equations [3,20]. The total hole current density in a semi-
conductor is composed of the sum of the drift and the diffusion components
of current. Similarly, the total electron current density in a semiconductor is
composed of the sum of the drift and the diffusion components of current.
For electrons the total current density is given as

dn
J n = qDn + qnµ nE (2.34)
dx
Similarly for holes,

dp
J p = − qDp + qpµ pE (2.35)
dx
The total current is the sum of the electron and hole current densities multi-
plied by the area, A, perpendicular to the current direction:

Itot = A( J p + J n ) (2.36)

2.5.4  Einstein Relation

In a non-uniformly doped semiconductor the doping concentration decreases
with increase in x. As a result, diffusion of majority carriers takes place from
a high concentration to a low concentration region along the +x direction.
The flow of electrons leaves behind positively charged donor ions. The sepa-
ration of positive and negative charges creates an electric field in the direc-
tion opposite to the diffusion process. At equilibrium the induced electric
field prevents further diffusion.
When taking the electric field along the x direction, the energy bands are
as shown in Figure 2.11. The potential energy increases in the direction of the
electric field. The electrostatic potential, which varies in the opposite direc-
tion as it is defined in terms of positive charges, is given by

E( x)
V ( x) = − (2.37)
q

From the definition of electric field

dV ( x)
E( x) = −
dx
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 65

Electric field

Conduction band

Ei

Valence band

FIGURE 2.11
Energy band diagram of a semiconductor in the presence of an electric field E(x).

Considering Ei as a convenient reference, the electron potential energy may

be related to E(x) as

dV ( x) d  E  1 dEi
E( x) = − =−  i = (2.38)
dx dx  (− q)  q dx

Since the band diagram indicates electron energies, we know that the
slope of this band must be such that electrons drift downhill in the field.
Therefore E points uphill in the band diagram. At equilibrium no current
flows. Putting

dp
J p = qpµ pΕ − qDp =0 (2.39)
dx
we get

Dp 1 dp ( x)
Ε ( x) = (2.40)
µ p p( x) dx

Also,

p0 = ni e(Ei −EF )/kT

so

Dp 1  dEi dEF 
Ε ( x) =  −  (2.41)
µ p KT  dx dx 

66 Technology Computer Aided Design: Simulation for VLSI MOSFET

The equilibrium Fermi level does not vary with x. So

dEF
=0
dx

and

dEi
= qE( x)
dx

Thus the equation takes the form Dµ = kTq . The relationship between drift
parameter (μ) and diffusion parameter (D) is given by the Einstein relationship.

2.6  Carrier Recombination and Generation

Recombination is a process by which the electrons occupy the empty states
associated with holes. The carriers as a result disappear. The energy released
is the difference between the initial state energy and the final state energy
of the electrons. The energy is emitted in the form of a photon for radia-
tive recombination. For non-radiative recombination, it is transmitted to one
or more phonons, and for Auger recombination it is transferred as kinetic
energy to another electron [1,2,21]. The different processes are shown in
Figure 2.12.

Ec

Et

Ev

Trap Aided Band-to-band Auger

Recombination Recombination Recombination

FIGURE 2.12
Carrier recombination mechanisms in semiconductors.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 67

In band-to-band recombination an electron moves from the conduction

band into the valence band state associated with the hole. In case of direct
band-gap semiconductors, it is a case of radiative transition. In trap-assisted
recombination, the electrons fall into the band gaps caused by some defects
or some foreign atoms. The electrons occupying those band gaps move into
an empty valence band state, thus completing the recombination process. So
this is a two-step transition of an electron from the conduction to the valence
band called Shockley-Read-Hall (SRH) recombination. Auger recombination
is a process of recombination of an electron and a hole with the resultant
energy given to another electron or hole. Auger recombination is different
from band-to-band recombination due to this third electron or hole. All the
recombination processes when reversed cause carrier generation instead of
recombination. A single expression can be used to describe both generation
and recombination processes. Generation of carriers by light absorption is a
process that does not have recombination associated with it. This process is
referred to as ionization. Impact ionization also belongs to this category. The
different generation mechanisms are shown in Figure 2.13.
If the photon energy is large, an electron from the valence band may move
into the conduction band generating an electron-hole pair as a result. This
photon energy must be larger than the band-gap energy for electron-hole
pair generation. Kinetic energy (Eph – Eg) is added to the electron and the hole
due to absorption of the photon.
Carrier generation due to high-energy charged particles is similar except
that the available energy may be far greater than the band-gap energy caus-
ing multiple electron-hole pairs generation. The high-energy particle gradu-
ally loses its energy and eventually stops [5,22].
Impact ionization is the counterpart of Auger recombination. It is caused
by an electron/hole with energy, much greater/smaller than the conduction/
valence band edge. The process is shown in Figure 2.14.
The excess energy is transmitted to generate an electron-hole pair in band
transition [23]. Avalanche multiplication is caused in semiconductor diodes

Conduction
band

Eph > Eg
Eg

Valence
band
Generation by Absorption Charged
of Light Particle
Ionization

FIGURE 2.13
Carrier generation due to light absorption and ionization due to high-energy particles.
68 Technology Computer Aided Design: Simulation for VLSI MOSFET

Electric field E

Conduction band

Valence band

FIGURE 2.14
Impact ionization and avalanche multiplication of electrons and holes in the presence of a large
electric field.

under high reverse bias as a result of this generation process. The accelerated
carriers gain kinetic energy that is given off to an electron in the valence
band, causing an electron-hole pair. The two electrons created in the process
can create two more electrons causing an avalanche multiplication effect.
Both electrons as well as holes take part in avalanche multiplication.

2.7  Continuity Equation and Solution

The continuity equation describes a basic concept, namely that a change in
carrier density over time is due to the difference between the incoming and
outgoing flux of carriers plus the generation and minus the recombination.
If a volume of space is considered in which charge transport and recombina-
tion are taking place, we have the simple equality as in Figure 2.15(a). As a
result of consideration of particle current, Net rate of particle flow = Particle
flow rate due to current − Particle loss rate due to recombination + Particle
gain due to generation.
Thus a continuity equation is based on the conservation of mobile charges [24]:

∂n 1 ∂ J n
= − Rn + Gn
∂t q ∂ x
(2.42)
∂p 1 ∂Jp
=− − R p + Gp
∂t q ∂x

where Gn and Gp are the electron and hole generation rates, Rn and Rp are the
electron and the hole recombination rates, and ∂∂Jxn and ∂∂Jxp are the net flux of
mobile charges in and out of x.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 69

Current is conserved

Incoming Outgoing
current current

Small volume in which generation and

recombination occurs
(a)

Jn(x + ∆x)
Jn(x)

Area of the
face, A
x ∆x

(b)

FIGURE 2.15
(a) A conceptual description of the continuity equation. (b) Geometry used to develop the cur-
rent continuity equation.

A solution to these equations can be obtained by substituting the expres-

sion for the electron and hole current. This then yields two partial differential
equations as a function of the electron density, the hole density, and the elec-
tric field. The electric field is obtained from Gauss’s law as in Figure 2.15(b).
Let us now collect the various terms in this continuity equation. If δn is the
excess carrier density in the region, the recombination rate R in the volume
A⋅Δx may be written approximately as

δn
R= ⋅A⋅ x (2.43)
τn
where τn is the electron recombination time per excess particle due to both the
radiative and the non-radiative components. The particle flow rate into the
same volume due to the current density J n ( x) is given by the difference of par-
ticle current coming into the region and the particle current leaving the region:

 J n ( x) J n ( x + x)  1 ∂ J n ( x)
 (− e ) − 
(− e ) 
A≅
e ∂x
x⋅A

70 Technology Computer Aided Design: Simulation for VLSI MOSFET

If G is the generation rate per unit volume, the generation rate in the volume
A · Δx is GAΔx. δn/τn is the net recombination rate of electrons and U =
G − R—that is, Rate of electron buildup (U) = Increase in electron concentra-
tion in ΔxA per unit time (G) – recombination rate (R). The rates of electron
buildup in volume A · Δx is then

 ∂n( x , t) ∂δn 1 ∂ J n ( x) δn 
A⋅ x ≡ = − 
 ∂t ∂t e ∂x τn 

As Δx approaches zero, we can write equations in the derivative form for

electrons and holes as
∂δn 1 ∂ J n ( x) δn
= −
∂t e ∂x τn
(2.44)
∂δp 1 ∂ J p ( x) δp
=− −
∂t e ∂x τp

Using these expressions, the diffusion currents are

∂δn
J n (diff ) = eDn
∂x
(2.45)
∂δp
J p (diff ) = − eDp
∂x

The time-dependent continuity equation for electrons and holes, valid separately:

∂δn ∂2 δn δn
= Dn −
∂t ∂x2 τn
(2.46)
∂δp ∂2 δp δp
= Dp −
∂t ∂x2 τ p

These equations are used to study the steady-state charge profile in p-n
diodes and bipolar transistors. In steady state,

∂2 δn δn δn
2
= = 2
∂x Dnτ n Ln
(2.47)
∂2 δp δp δp
= =
∂x2 Dp τ p L2p

Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 71

Here is the diffusion length for electrons, and Lp is the diffusion length for
holes. Considering the case where an excess electron density δn(0) is main-
tained at x = 0, at point L in the semiconductor, the excess carrier density is
maintained at δ(L). The general solution of the above second-order differen-
tial equation is

x −xL
δn( x) = A1e Ln
+ A2 e n (2.48)

When L >> Ln and δ n (L) = 0 , the semiconductor is much longer than Ln , for
example in the case of the long p-n diode. A1 and A2 can be found from the
boundary conditions. For a large value of x, δ n = 0 at x = ∞ and so A1 = 0.
Similarly δ n = 0 = δ n (0) at x = 0 giving A2 = δ n (0) . The solution of the equa-
tion is given by

−xL
δnp ( x) = δnp (0)e n
(2.49)

It is seen from the above equation that the carrier density decays exponen-
tially in the semiconductor.
However, when L << Ln , the carrier density is linear from one boundary
value to the other because over a short distance exponential can be approxi-
mated as linear. When excess carriers are injected into a thick semiconduc-
tor sample, both diffusion and recombination take place. Ln represents the
distance over which the injected carrier density falls to 1/e of its original
value. It also represents the average distance an electron diffuses before
recombination.
The probability that an electron survives up to a distance x without recom-
bination is given by

δnp ( x) −x
= e Ln
δnp (0)

The steady-state distribution of excess holes causes diffusion and a hole cur-
rent in the direction of decreasing concentration.

δp D
J p ( x) = − qDp = q P δp( x) (2.50)
δx Lp

It will be useful for the current calculation of the p-n junction where the
injection of minority carriers across a junction will lead to exponential
distribution.
72 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.8  Mobility and Scattering

The relationship between the velocity of electrons and the applied elec-
tric field is complex. When the electric field is low, the relationship is in a
simple form. The distance versus time trajectory of an electron is shown in
Figure  2.16. Considering d as the distance traveled in time t, the electron
motion is described by

d = vt
v = μE
The velocity of electron v is proportional to the electric field applied, and μ
is the mobility. For a large electric field the relation between the velocity and
the applied field is not so simple [2–4] and will be discussed later.
When no electric field is applied externally, the occupation of a state with
momentum +ħk is the same as that with momentum −ħk. So no current flows
in this case as the momentum gets canceled out. Figure 2.17(a) shows the
distribution function in momentum space. When an electric field is applied,
the electron distribution shifts, as shown schematically in Figure  2.17(a),
and there is a net momentum of the electrons. Current flows as a result.
For perfect and rigid crystal, no scattering of the electron takes place. On
application of an external electric field E, the electron behaves as a “free”
electron in the absence of scattering. However, there are always imperfec-
tions due to which electrons scatter. The process is shown in Figure 2.17(b).
The average behavior of the electrons represents the transport properties of
the electrons.

Electric field E

Movement of
electron in a
crystal
Distance Travelled by

d = vt
Electron

Also, v = µE

Time Taken

FIGURE 2.16
A typical electron trajectory in a sample, and the distance versus time plot.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 73

No electric
field Σf (k) = 0

–k +k

Electric field E

Σf (k) ≠ 0

–k +k
(a)

Electric field E

Free electron
transport

Collisions or scattering in
electron path
(b)

FIGURE 2.17
(a) Schematic of the electron momentum distribution function in the presence and absence
of an electric field. (b) Schematic view of an electron moving under an electric field in a
semiconductor.

In the absence of scattering, the electron transport is very simple although

scattering dominates transport in semiconductor devices. Due to scattering,
electrons in a semiconductor do not achieve constant acceleration. However,
they can be considered as classical particles moving at a constant average
drift velocity.
The electron suffers a scattering as it moves. In between scattering, the
electron moves according to the “free” electron equation of motion. The
scattering of carriers is mainly due to lattice vibrations caused by thermal
energy. Carriers scatter from various imperfections in crystal, alloy disorder,
and interface imperfections.
74 Technology Computer Aided Design: Simulation for VLSI MOSFET

On application of an electric field E, drift current flows in a semiconduc-

tor. The force experienced by an electron is given by F = − qE = me dv dt
. The
velocity of electrons will saturate at a constant value in steady state. In fact,
F = me dv
dt + me τ , where the latter term represents the impeded force due to
v

scattering which describes collision caused by lattice vibrations and crystal

imperfections. At steady state (dv/dt = 0), the drift velocity is

Fτ − qEτ
Vd = = = −µE (2.51)
me me
where

qτ
µ= (2.52)
me

is the mobility of the electron (or hole), and τ is the mean free time between
collisions.

2.9  Different Distribution Laws

There are three distribution laws that govern the particle distribution among
available energy states.

1.
Maxwell-Boltzmann probability function: Particles are distinguishable
with no limit to the number of particles in each energy state.
2.
Bose-Einstein function: Particles are indistinguishable and no limit to
the number of particles in each energy state.
3.
Fermi-Dirac probability function: Particles are indistinguishable and
only one particle is permitted in each quantum state.

The Fermi factor that expresses the probability that a state at a given energy
level is occupied by an electron has a value between 0 and 1. A probability
of 0 means that the state is unoccupied and a probability of 1 means that the
state is occupied. A probability of ½ means that the chance of the state being
occupied is 50%.

2.9.1  Fermi-Dirac Distribution

The Fermi-Dirac distribution function, also called the Fermi function, gives
the probability of occupancy of energy levels by Fermions. Fermions are half-
integer spin particles obeying the Pauli exclusion principle. As the Fermions
are added to an energy band, they will fill the available states in an energy
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 75

band. The states with the lowest energy are filled first, followed by the next
higher ones. At absolute zero temperature (T = 0 K), the energy levels are all
filled up to a maximum energy called the Fermi level. No states above the
Fermi level are filled. At higher temperature, the transition between com-
pletely filled and completely empty states is gradual. The Fermi function
provides the probability that energy level at energy, E, in thermal equilib-
rium with a large system, is occupied by an electron. The system is character-
ized by its temperature, T, and its Fermi energy, EF.
The Fermi-Dirac distribution function f(E) gives the probability that an
electron has an energy E at a temperature T [25]. This is given by

1
f (E) =
1 + exp[(E − EF )/KT ] (2.53)

where k is the Boltzmann constant, T is the temperature in Kelvin, and EF is

the Fermi level.
It is seen that at T = 0 K if E = EF, f(E) = 1/2. Similarly at T = 0 K if E > EF
f(E) = 1/1 + exp(∞) = 1/1 + ∞ = 0. Also at T = 0 K if E < EF f(E) = 1/1 + exp(–∞) =
1/1 + 0 = 1. The condition E < EF, f(E) = 1 shows that below the Fermi level all
the states are occupied and the probability of finding an electron on a level
with energy greater than Fermi energy is zero. It is therefore the energy of
the highest filled level. At other temperatures E = EF and f(E) = 1/2. So the
Fermi level is that energy at which the probability of a state being occupied
is ½. At T = 0oK, no covalent bonds are broken and all the lower energy
states up to E = EF are completely occupied. At any other temperature cova-
lent bonds are continuously broken, which generates electron-hole pairs.
The recombination of electrons and holes also takes place at the same time.
Due to this, the probability of the states being occupied below the Fermi
level is slightly less than one, and there is a small probability that a few
states are occupied just above the Fermi level. As shown in Figure  2.18,
as the energy E = EF, the probability of occupancy of a state by an elec-
tron decreases exponentially as E increases in accordance with the above
equation. f(E) gives the probability that a state at a given energy level is
occupied by an electron. Then probability that a state is not occupied by
an electron, or equivalently, the probability that there exists a hole in the
valence band will be given by

1 1
f p (E) = 1 − f (E) = 1 − = (2.54)
1 + exp[(E − EF )/KT ] 1 + exp[(EF − E)/KT ]

In general the position of EF is dependent on temperature. The occupation

probability is at 0.5 at the Fermi energy. We may write f(E) = N(E)/g(E),
where N(E) is the number of carriers per unit volume per unit energy, and
g(E) is the number of quantum states per unit volume per unit energy.
76 Technology Computer Aided Design: Simulation for VLSI MOSFET

T = 0° K
Probability of Occupancy

1 T1

T2 > T1

T2

EF E

FIGURE 2.18
The Fermi function for electrons.

Therefore, f(E) gives us the probability that a quantum state of energy E

may be occupied.
The probability of energy above EF being occupied increases as tempera-
ture increases, and the probability of a state below EF being empty increases
as temperature increases. We may note that the probability of a state being
occupied above EF is the same as the probability of a state below EF being
empty. The curve is symmetrical.
The Bose-Einstein distribution function is applicable to particles with inte-
ger spin called Bosons and includes photons, phonons, and a large number of
atoms. Bosons do not obey the Pauli Exclusion Principle so that any number
can occupy a single energy level. The Bose-Einstein distribution function is
given by

1
fbe (E) = (2.55)
exp[(E − EF )/KT ] − 1

This distribution function is only defined for E > EF.
The Maxwell-Boltzmann distribution function applies to non-interacting
distinguishable particles [9]. This function is also called the classical distri-
bution function because it provides the probability of occupancy for non-
interacting particles at low densities. The Maxwell-Boltzmann distribution
function is given by

1
fmb (E) = (2.56)
exp[(E − EF )/KT ]

All three functions are almost equal for large energies. The Fermi-Dirac dis-
tribution reaches a maximum of 100% for energies, which are a few kT below
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 77

the Fermi energy, while the Bose-Einstein distribution diverges at the Fermi
energy and has no validity for energies below the Fermi energy.

2.10  Semiconductor Device Modeling

2.10.1 Introduction
Rapid developments in semiconductor technology over the past 20 years
have caused huge interest in device modeling. The need to understand the
detailed operation of very large scale integrated (VLSI) devices and com-
pound semiconductor devices has meant that device modeling now plays a
crucial role in modern technology.
As the size of the semiconductor decreases and the complexity of the phys-
ical structure increases, the nature of the device characteristics depart from
those obtained from many of the classically held modeling concepts. The
difficulty encountered in performing measurements on these devices means
that greater emphasis must be put on theoretical results. Modeling also allows
new device structures to be rigorously investigated prior to fabrication.
Semiconductor device models can be classified into two categories:
physical device models and equivalent circuit models. Physical device
models account for the physics of device operation, and equivalent cir-
cuit models are based on electrical circuit analogies representing electri-
cal behavior. The latter approach is generally limited in its applicability
because of the frequency dependence and the non-linear behavior of most
devices with respect to signal level. The advantage of this technique is that
it is easy to implement. In contrast, physical device models can provide
greater insight into the detailed operation of semiconductor devices but
usually require lengthy analysis. The analysis requirements for physical
models are typically satisfied using numerical techniques implemented
on computers. With the advent of fast and powerful computing resources,
this makes physical modeling techniques a very attractive proposition for
the physicist.
Physical device models are solved using either bulk carrier transport
equations, solutions to the Boltzmann transport equation, or quantum
transport concepts. Historically, bulk transport solutions have satisfied
most device models, while Boltzmann and quantum transport solutions
have provided strong insight into the detailed device physics. However, the
trend toward very small geometry devices, operating in the hot electron
range, means that non-equilibrium transport conditions must be accounted
for. The understanding of physical boundary conditions and device-circuit
interaction is steadily improving, allowing more intricate models to be
developed.
78 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.10.2  Shockley-Read-Hall (SRH) Generation/Recombination Model

The generation/recombination process by phonon emission is shown in
Figure 2.13. A lattice defect energy Et, as in Figure 2.12, is used in this trap-
assisted mechanism. Energy is transmitted/received by phonon during the
recombination/generation process. This effect is known as Shockley-Read-
Hall (SRH) generation/recombination effect. The four sub-processes are
described below as in [1,9]:

1.
Capture of electron: A conduction band electron is captured by a
vacant trap in the semiconductor band gap. (Ec − Et) is the energy
released to the crystal lattice in the form of phonon emission.
2.
Capture of hole: The electron in the trap now neutralizes a hole in the
valence band. Because the direction of motion of the hole is opposite
to that of the electron, the hole is captured by the trap in the semi-
conductor lattice band gap and energy of (Et − Ev) is generated in the
form of a phonon.
3.
Emission of hole: A valence band electron moves to the trap in the lat-
tice band gap, thereby leaving a hole in the valence band. So it can be
said that a hole moves from the trap to the valence band, as a result
of which generating (Et − Ev) energy in the form of phonon.
4.
Emission of electron: Here an electron moves from the trap level to the
conduction band as a result of which requiring (Ec − Et) amount of
energy.

It is seen that both the generation and the recombination processes are
two-step processes. Sub-processes 1 and 2 lead to recombination of
electron-hole pairs, the excess energy equal to band-gap energy is trans-
ferred to the crystal lattice in the form of phonons. Sub-processes 3 and 4
lead to generation of electron-hole pairs where energy needs to be supplied
by the lattice.
For finding an expression of the total recombination rate Rtot, rates for the
four sub-processes need to be determined. In this case traps are assumed
to be of the acceptor type, which are neutral when empty and negatively
charged when occupied by an electron. Similarly, the derivation for donor
traps (neutral when occupied by electron and positive when empty) can be
done.
Let the capture rate of an electron be ve ,capture, proportional to the electron
concentration in the conduction band n, the empty traps concentration nt0 ,
and a proportionality constant ke ,capture. With the energy-dependent distribu-
tion function for electrons fe (E) and the density-of-states g e (E) we get

dve ,capture = ke ,capture (E)nt0 g e (E) fe (E)dE (2.57)

Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 79

The total conduction band electrons is given by

n=
∫ g (E) f (E) dE
e e (2.58)
Ec

Let the hole capture rate be vh ,capture , hole concentration in the valence band p,
the filled traps concentration ntfill , with proportionality constant k h ,capture . We
get

dvh , capture = k h , capture (E)ntfill f h (E) g h (E) dE (2.59)

f h (E) is the distribution function for holes, and g h (E) is the hole density of state.
Total holes in the valence band is

p=
∫ g (E) f (E) dE
h h (2.60)
Ev

The hole emission rate is vh ,emission , and the proportionality constant is k h ,emission :

dvh , emission = nt0 k h , emission (E){1 − f h (E)} g h (E) dE

(2.61)
Electron emission rate ve ,emission is proportional to the concentration of filled
traps and the proportionality constant ke ,emission :

dve , emission = ntfill ke , emission (E){1 − fe (E)} g e (E) dE (2.62)

The total trap concentration nt is

nt = ntfill + nt0 (2.63)

and the fraction of occupied traps foccupied is given by [9,26]

ntfill
foccupied =
nt
(2.64)
nt0
1 − foccupied =
nt

The net recombination rate for electrons becomes

dRe.tot = [ ke , capture (E)nt0 fe (E) − ke , emission (E)ntfill {1 − fe (E)}] g e (E) dE (2.65)

80 Technology Computer Aided Design: Simulation for VLSI MOSFET

In thermal equilibrium np = n0 p0 = ni2, which means that the respective cap-

ture and emission rates for electrons and holes are equal:

ve ,emission = ve ,capture , vh ,emission = vh ,capture (2.66)

so

ke ,emission (E) 1 − foccupied fe (E)

= (2.67)
ke ,capture (E) foccupied 1 − fe (E)

In thermal equilibrium, foccupied is given by Fermi-Dirac statistics [9]:

1
foccupied (E) =  E−EF  (2.68)
 
kT 
1+ e
Hence,

 Et −EF   E−EF   Et −E 
ke ,emission (E)   −   
(2.69)
= e kT   kT 
e = e kT 

ke ,capture (E)
The net recombination rate is modified as

ke , emission (E) fill

dRe ,tot = [nt0 fe (E) − nt {1 − fe (E)}]ke , capture (E) g e (E) dE (2.70)
ke , capture (E)

 k (E)  foccupied   1 − fe (E)  

= 1 − e , emission    (1 − foccupied ) fe (E)ke , capture (E) ge (E)nt dE

 ke , capture (E)  1 − foccupied   fe (E)  

(2.71)


 EFt − EF  
 
= 1 − e  kT   (1 − foccupied ) fe (E)ke , capture (E) g e (E)nt dE (2.72)
 

with the trap’s quasi Fermi energy EFt .

The total electron recombination rate is given by

 EFt − EF  ∞

∫
 
kT 
Re ,tot = [{1 − e }(1 − foccupied )nt ] fe (E)ke , capture (E) g e (E) dE (2.73)
Ec

Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 81

Let a capture cross section α e (E) be introduced to rewrite ke ,capture as

ke ,capture (E) = α e (E)vthermal

e
(2.74)

with the thermal velocity for electrons

3 kT
e
vthermal = (2.75)
m

For non-degenerate semiconductors near equilibrium the electron recombi-

nation is

 −  c F   Ft F  
 E −E   E −E 
Re , tot =  n − N c , effective e  kT  e  kT   (1 − foccupied )K e , capture (2.76)

where N c ,effective is the effective density of states for electrons and

K e ,capture = nt vthermal
e
<< α e (E) >>

Considering
 E −E 
− c t 
 kT 
n1 = N c , effective e (2.77)

and
 Ev −Et 
 
p1 = N v ,effective e  kT 

we get
Re ,tot = {n(1 − foccupied ) − n1 foccupied } K e ,capture

In the stationary case the recombination rates for electrons and holes are equal,

Re ,tot = Rh ,tot = Rtot (2.78)

Therefore, we can calculate foccupied as

ke ,capture n + k h ,capture p1
foccupied = (2.79)
ke ,capture (n + n1 ) + k h ,capture ( p + p1 )

Using this expression the total recombination rate is obtained as [3,9]

np − n1 p1
Rtot = ke ,capture k h ,capture nt (2.80)
ke ,capture (n + n1 ) + k h ,capture ( p + p1 )

82 Technology Computer Aided Design: Simulation for VLSI MOSFET

It is common to introduce carrier lifetimes for electrons and holes Τ electron

and Τ hole as
1
Τ electron =
ke ,capture nt

and

1
Τ hole =
k h ,capture nt

By using the capture cross sections for electrons and holes, α e (E) and α h (E),
e h
and the thermal velocities vthermal and vthermal ,

1
Τ electron =

e
nt vthermal α e (E)

1
Τ hole =

h
nt vthermal α h (E)

We come to the final formulation of the Shockley-Read-Hall model for the

carrier generation-recombination model:

np − ni2
Rtot = nt (2.81)
Τ hole (n + n1 ) + Τ electron ( p + p1 )

2.10.3  Simple Recombination-Generation Model

In this model the recombination-generation rate is proportional to the excess
carrier density. If the carrier density equals the thermal equilibrium value
no net recombination takes place. The expression for the recombination of
electrons in a p-type semiconductor is given by

np − np0
U n = Rn − Gn = (2.82)
τ
The expression for the recombination of holes in an n-type semiconductor is
given by

pn − pn0
U p = R p − Gp = (2.83)
τ
where τ is the average time of recombination of excess minority carrier.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 83

The above expressions are valid only for minority carriers in a “quasi-
neutral” semiconductor. In steady state the recombination rates of the major-
ity and minority carriers are equal because recombination involves an equal
number of holes and electrons. Majority carrier recombination depends on
the excess minority carriers.

2.10.4  Impact Ionization Model

Impact ionization is a pure generation process similar to the Auger genera-
tion process. When a carrier moves into the conduction or valence band, the
energy released is used to move an electron from valence to conduction band
causing an electron-hole pair.
The two sub-processes in this case are the electron emission and the hole
emission. While in the former a highly energetic electron in conduction
band transfers energy to an electron in valence band, in the latter case, a
hole in a valence band transfers energy to an electron in the valence band.
As a result, the electron from valence band moves to the conduction band.
The effect of impact ionization and avalanche multiplication is shown in
Figure 2.14.
The current densities for electrons and holes are given as J e and J h . The
generation rates are modeled proportional to these current densities as [9]

ie J e ih J h
ge = and gh = (2.84)
q q

where ie and ih are the ionization rates for electrons and holes, respectively.
The ionization rates are exponentially dependent on the electric field along
critical critical
the current flow direction. Let Eelectron and Ehole be the critical electric fields
∞ ∞
for electrons and holes. Let ie and ih be the ionization rates at infinite field
for electrons and holes, respectively. The ionization rates for electrons and
holes are given by
jelectron
∞  E critical 
ie = i exp−  electron 
e (2.85)
 E 
and
jhole
 E critical 
ih = ih∞ exp−  hole  (2.86)
 E 

where jelectron and jhole are model parameters with values close to 1.
84 Technology Computer Aided Design: Simulation for VLSI MOSFET

The total impact ionization rate is now found as

i J i J 
Rtotal , IIR = −( g e + g h ) = −  e e + h h  (2.87)
 q q 

This rate is independent of the electric field but depends on the carrier
temperature.

2.10.5  Mobility Modeling

Mobility modeling is divided into four categories: low field mobility, high
field mobility, bulk semiconductor mobility, and inversion layer mobility.
In low field mobility the carriers are in equilibrium with the lattice and
the mobility is very low. This mobility is inversely related to the impurity
scattering. The low field mobility models for bulk materials include con-
stant mobility model, Caughey and Thomas model [27], Dorkel-Leturg
model [28], Arora model [29], and Klaassen low-field mobility model
[30]. The low field mobility is mainly affected by Coulomb scattering. In
the high field case the mobility decreases with electric field as the high
energy carriers take part in scattering and the mean drift velocity rises
slowly with increasing electric field. Finally the drift velocity saturates
to a constant value. The bulk mobility model is a three-step process. First
the low field mobility is expressed as a function of lattice temperature
and doping. Then the saturation velocity is expressed in terms of tem-
perature. And finally the low and high field junction region is described.
The mobility models can further be classified into physical based, semi-
empirical, and empirical models. As carriers move under the influence
of an electric field, the velocity saturates and so the effective mobility
reduces because the drift velocity is equal to the product of mobility and
the electric field. The field-dependent mobility expressions of Caughey
and Thomas [27] are

1
−
  µ n 0E  β n  βn
µ n (E) = µ n0 1 +  n   (2.88)
  vsat  

1
−
  µ p 0E  β p  βp
µ p (E) = µ p 0 1 +  p   (2.89)
  vsat  

where µ n0 and µ p0 are the respective low field electron and hole mobility,
and E is the parallel electric field. The saturation velocities are calculated
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 85

from the temperature-dependent model in [31] as

p 24 * 106 (2.90)
vsat = vsat
n
= cm/sec
1 + 0.8exp ( 600
T
)

2.11  Introduction to MOS Transistor

The most important requirement for a field-effect transistor (FET) is zero or
negligible gate leakage current. It is important to isolate the gate from the
channel so that no current flows into the gate. One needs some kind of bar-
rier for the electron (or hole) from the gate to the source, the channel, and the
drain. In MOSFET, an insulator provides the barrier. It is possible to grow a
high-quality and reliable insulator using Silicon (Si). SiO2 is stable and makes
a firm bonding with Silicon. This oxide makes selective diffusion and easy
pattern transfer. This has led to the well-established silicon MOSFET technol-
ogy to become dominant. In MOSFET application of a large gate bias inverts
the bands and induces the electrons (or holes) in a channel without the gate
leakage. Over the last few years steady progress has been made on using the
MOSFET concept with other semiconductors, notably (Gallium Arsenide)
GaAs. GaAs n-MOSFETs have channel mobilities much higher than those in
n-MOSFET based on the silicon as in [32]. However, GaAs technology does
not provide a high-quality oxide. Thus, the widespread use of such devices
is still not prevalent because of lack of good-quality oxide.
The Si technology is unique in the sense that a high-quality oxide SiO2 can
be formed on the silicon wafer. The Si-SiO2 interface perfection is required
for a field-effect device. Their higher areal density, better switching charac-
teristics, and lower power dissipation have made them the dominant device
in electronic systems.
There are two basic types of MOS transistors: the n-channel and the
p-channel. A circuit containing only n-channel devices is produced by an
nMOS process. Similarly, a pMOS process fabricates circuits that contain
only p-channel transistors.

2.12  Structure and Symbol of MOSFET

The structure of an n-channel MOS transistor is shown in Figure 2.19(a), con-
sisting of two n-type regions embedded in a p-type substrate, connected via
metal or polysilicon to external conductors called the source and the drain.
86 Technology Computer Aided Design: Simulation for VLSI MOSFET

Source Gate Drain

Conductor
plate
hW

D
dt
Wi

B
G

S
n+ source n+ Drain (b)
Oxide
thickess tOX p type substrate

Insulator oxide
SiO2 Length L
(a)

FIGURE 2.19
(a) An n-type NMOS device structure. (b) Symbol of MOSFET.

The symbol of MOSFET is shown in Figure 2.19(b). An n-channel MOS tran-

sistor is fabricated in a p-type semiconductor substrate, usually silicon [33].
Two n-type regions are made in the substrate and the current flows between
these two regions. The region with the lowest applied potential is called the
source and that with the highest potential is called the drain. On the surface,
a thin silicon dioxide (SiO2) layer is formed and on top of this a conducting
polysilicon material called a gate is deposited. An electron-rich layer called a
channel can be created between the source and the drain underneath the gate
when a positive gate bias is applied. When appropriate voltages are applied
at the source and the drain, electrons can flow from the source into the drain.
If the substrate material is n-type and the diffused regions are p-type, a simi-
lar structure will represent a p-channel MOS transistor. The gate plate must
act as a good conductor and was in fact realized by metals like aluminum
in the early generations of the MOS technology. However, it was discovered
that the non-crystalline polysilicon exhibits better fabrication and physical
properties. The bonding between the silicon substrate and polysilicon gate
is better than that between the metal gate and the silicon substrate. Thus the
metal M is replaced by a heavily doped polysilicon.
Here L and W denote the length and width of the channel, respectively. In
the most common mode of operation of the transistor, the source and the sub-
strate are grounded and the drain is connected to a supply voltage VDD through
a load resistor, which is positive for an n-channel transistor and negative for a
p-channel transistor. In a MOSFET the channel charge is induced electrostati-
cally by the gate by using it as a capacitor without the need for doping.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 87

2.13  Basic Operation of MOSFET

2.13.1  Operation of MOSFET with Zero Gate Voltage
Let us consider the gate voltage equal to zero while the p-type substrate
and the source are grounded (VSub = VS = 0) [34]. The drain is connected to
a positive voltage source. Because the source and the substrate are at the
same potential, no current flows in the source-substrate junction. The drain-
substrate junction is reverse biased, and except for a small reverse leakage
current, no current flows in that junction. These back-to-back diodes prevent
current conduction from the source to the drain, as in Figure  2.20(a). The
depletion formation is shown in Figure 2.20(b). The MOSFET has a very high
resistance between the source and the drain. It is operating in the “cut off”
as there is no conducting channel between the source and the drain. Small
current flows due to the second-order effect under the weak inversion, called
subthreshold current.

2.13.2  Operation of MOSFET with a Positive Gate Voltage

In this case a constant positive bias is applied to the gate as in Figure 2.21(a).
There is no gate current because the metal electrode is insulated from the
silicon. However, the positively biased gate electrode attracts electrons
from the semiconductor, and an electron-rich layer forms underneath the
gate insulator. In effect, negative charges are induced in the underlying Si
by the formation of a depletion region and a thin surface region containing
mobile electrons.

Source Gate Drain Source Gate Drain

n+ n+ n+ n+

p-type bulk si p-type bulk si

Depletion layer
(a) nMOS (b) Depletion layer formation
Operating in cut off mode as VGS < Vth

FIGURE 2.20
(a) Two reverse biased p-n diodes representing a MOSFET working in cutoff regime. (b)
MOSFET operating in the “cut-off” mode.
88 Technology Computer Aided Design: Simulation for VLSI MOSFET

+ –

Source VG Drain

+ –

VG
n+ n+

p-type
substrate

(a)

Source + – Drain Source +– Drain

VG VG

n+ n+ n+ n+

p-type p-type
substrate substrate

(b) (c)

FIGURE 2.21
(a) MOSFET with positive gate bias. (b) Formation of depletion region. (c) Formation of channel.

The positive voltage on the gate causes the free holes to be repelled from
the region underneath the gate [35]. The holes are pushed downward into the
substrate, leaving behind a depletion region. The depletion region is popu-
lated by the bound negative charge associated with the acceptor atoms as
in Figure 2.21(b). Also, the positive gate voltage attracts electrons from the
source and the drain regions into the channel. When a large number of elec-
trons accumulates near the surface underneath the gate, an n region is cre-
ated, connecting the source and the drain regions, as in Figure 2.21(c).
The electron-rich layer underneath the gate is called the channel. The
n-type source and the n-type drain are connected by the electron-rich chan-
nel. When a voltage is applied between the drain and the source, current
flows between them. The gate bias creates an electric field that can either
induce or prevent the formation of an electron-rich region at the surface of
the semiconductor. The channel is created by inverting the substrate surface
from p to n type. Hence the induced channel is also called an inversion layer
and is shown in Figure 2.22.
Threshold voltage (VTH) in MOSFET is defined as the minimum gate volt-
age required to induce the channel. For an n-channel device, positive gate
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 89

VGS > Vth

Source Drain

n+ n+

p-substrate

Inversion layer formation

FIGURE 2.22
Inversion layer formation in nMOS for positive gate bias.

voltage greater than VTH is required to induce a conducting channel consist-

ing of electrons. For a p-channel device, a negative gate voltage larger than
V­TH is required to induce a conducting channel consisting of holes.

2.13.3  Effect of a Small VDS

A small positive voltage VDS between the drain and the source induces a
channel. This positive voltage VDS causes electrons to flow from the source
to the drain through the induced channel, causing a flow of current. The
magnitude of this current ID flowing from the drain to the source depends
on the density of the electrons in the channel, which in turn depends on the
magnitude of VGS. For VGS = VTH, the channel is just induced and the current
is small. When VGS exceeds VTH more electrons are attracted to the channel
and the current increases. We observe that the MOSFET is operating as a
linear resistor whose value is controlled by VGS, and the channel is uniform
when a small VDS is applied. Thus the MOSFET is said to operate in the linear
or triode region.

2.13.4  Operation of MOSFET as VDS Is Increased

Let VGS be kept constant at a voltage greater than VTH. As VDS is increased the
voltage drop across the length of the channel increases [36]. As one moves
along the channel from the source to the drain, the voltage increases from 0 to
VDS. So the voltage between the gate and points along the channel decreases
from VGS at the source end to (VGS – VDS) at the drain end. Because the voltage
is not constant, the channel is no longer of uniform depth; rather it will be
90 Technology Computer Aided Design: Simulation for VLSI MOSFET

VGS ≥ Vth
VGS – Vth > VDS VGS VDS

n+ n+
Current flow

p-substrate

FIGURE 2.23
Current flow through the channel for small VDS.

tapered as shown in Figure 2.23. As VDS is increased, the channel becomes

more tapered and its resistance increases correspondingly. Eventually, when
VDS is increased to the value that reduces the voltage between the gate and
the channel at the drain end to VTH—that is, VGD = VTH or VGS – VDS = VTH or
VDS = VGS – VTH—the channel depth at the drain end decreases to almost zero,
and the channel is said to be pinched off as shown in Figure 2.24. Increasing
VDS beyond this has negligible effect on the channel shape, and the current
through the channel remains fixed. The drain current saturates at this value,
and the MOSFET is said to have entered the saturation region of operation.
Because the current is constant in the saturation region, the MOSFET is
said to operate as a constant current source whose value depends upon the
applied gate voltage. The voltage VDS at which saturation occurs is denoted
as VDsat = VGS – VTH. So for every value of VGS, there is a corresponding value

VGS ≥ Vth Drain

VGS – Vth = VDS VGS VDS
Source
Inversion layer is
pinched off near the
Gate drain

n+ n+

p-type
substrate

FIGURE 2.24
Pinched off channel, with deeper depletion layer near the drain side.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 91

of VDsat [37]. When VDS ≥ VDsat, the device operates in the saturation region. The
region of the ID – VDS characteristic for VDS < VDsat is called the triode region.

2.14  Threshold Voltage of MOSFET

Conduction between the source and the drain takes place for MOSFET under
the influence of the source-to-gate voltage. The current flow does not begin
sharply, but it is assumed that if the gate voltage exceeds a given value called
the threshold voltage Vth, conduction starts. The first step is to study the band
diagram. The analytical expression of this important parameter comes from
the study of the MOS structure. To understand the operation of the MOSFET
we first need to examine the MOS capacitor, shown in Figure 2.25. An oxide
layer is grown on top of a p-type semiconductor and a metal contact is placed
on the oxide. In general, the insulator could be large band-gap material.
The MOS capacitor consists of a metal gate, an insulating oxide layer, and a
semiconductor. The thickness of the oxide varies from 5 to 50 nanometers. We
first consider the case of a hypothetical metal whose Fermi level is the same as
that of silicon [38]. When such a structure is fabricated, the Fermi level of the
system is unique, and because the metal has the same Fermi level as the sili-
con, the band structure is that shown in Figure 2.26. Work function is defined
as the energy required for moving an electron from the Fermi level to the
outside. In this idealized case let Φ m = ΦS so that there is no difference in the
work functions. This condition is referred to as flat band for obvious reasons.

Metal

Oxide insulator

Semiconductor

FIGURE 2.25
A MOS capacitor.
92 Technology Computer Aided Design: Simulation for VLSI MOSFET

Oxide
Silicon
EC EC

Metal
Ei Ei
EFM

–qVG > 0
EF EF
EFM
Ev Ev
x x

(a) (b)

EC
EC

Ei
Ei
–qVG < 0

EF
–qVG << 0

EF
Ev
Ev
EFM
EFM
x
x
(c) (d)

FIGURE 2.26
Energy band diagram of MOSFET: (a) flat band, (b) accumulation, (c) depletion, and (d)
inversion.

2.14.1  Accumulation of Holes

When a negative bias is applied between the metal and the semiconductor,
a negative surface charge is deposited on the metal at the metal oxide inter-
face, and the structure behaves as a parallel-plate capacitor whose electrodes
are the silicon and the metal, with oxide as the insulator [39]. In response an
equal net positive charge appears at the surface of the semiconductor at the
silicon-oxide interface. This silicon charge whose thickness is approximately
10 nm can also be considered as a surface charge. This hole-rich thin layer is
called an accumulation layer.
The energy band diagrams are drawn for negative charges, whereas an
electrostatic potential diagram is drawn for positive test charges. In metal,
application of negative bias reduces the electrostatic potential, and as a result
electron energies are raised in the metal relative to the semiconductor. The
Fermi level for the metal rises above its equilibrium position by qV, where V
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 93

Accumulation

p
p0
EC

Carrier Density
Ei
EFM n0
eVG

EF n
+
++ EV

Z
M O S
W

FIGURE 2.27
Energy band diagram for ideal MOS capacitor under the application of applied voltage.

is the applied voltage. The difference between the Fermi level in the metal
and the semiconductor is the applied bias.
Because Φ m and ΦS do not change with applied voltage, but EFm moves
up relative to EFS, causing a tilt in the oxide conduction band, the energy
bands of the semiconductor bend near the interface (the valence bands are
bent to come closer to the Fermi level) accommodating the accumulation of
holes at the interface as in Figure  2.27. The effect of depositing a negative
charge in the gate of a MOS transistor causes hole accumulation.
An increase in surface hole concentration implies an increase in Ei − EF
at the surface. Because the Fermi level within the semiconductor remains
unchanged as no current flows though the MOS structure with increasing
(Ei − EF ), Ei must move up in the energy near the surface. This results in band
bending near the surface. From Figure 2.27 it is clear that near the surface the
Fermi level lies closer to the valence band, creating a larger hole concentra-
tion than that arising from the doping of the p-type semiconductor.

2.14.2 Depletion
When a positive bias is applied to the metal, positive charges are depos-
ited on the metal and a corresponding net negative charge accumulates at
the semiconductor surface. Such a negative charge in the p-type material is
due to depletion of holes from the surface, leaving behind the uncompen-
sated ionized acceptors. Thus the hole concentration decreases, moving Ei
closer to EF , bending the band down near the semiconductor surface as in
Figure 2.28. If the positive voltage is increased, the band bends down more
94 Technology Computer Aided Design: Simulation for VLSI MOSFET

Depletion
Electric field E

Na p0
p
EC

Carrier Density
n
n0
VG > 0 Ei

EF
EV
qVG

EFM Z
W
M O S

FIGURE 2.28
Effect of applied electric field on the interface charge density in the ideal MOS capacitor: posi-
tive gate voltage (VG) creates a depletion region.

strongly, resulting in inversion that occurs for the higher positive applied
positive gate bias [39].

2.14.3 Inversion
If the positive bias on the metal side is increased further, the bands at the semi-
conductor surface bend down more strongly as shown in Figure 2.29. A large
positive voltage can bend Ei below EF . Thus the conduction band at the oxide-
semiconductor region comes close to the Fermi level in the semiconductor. This
reverses the mobile charges from holes to electrons at the interface and the elec-
tron density increases. If the positive bias is increased until EC comes close to
the electron quasi-Fermi level near the interface, the electron density increases
and the semiconductor near the interface has electrical properties of an n-type
semiconductor. This n-type surface layer is formed not by doping, but by inver-
sion of the original p-type semiconductor due to the applied bias. This inverted
layer is separated by the underlying p-type material by a depletion region.

2.14.4 Surface Potential

Figure  2.30 shows the band bending of the semiconductor on the onset of
strong inversion [37–39]. It is described by the quantity Φ ( x) , which mea-
sures the position of the intrinsic Fermi level with respect to the bulk intrin-
sic Fermi level. The band bending at the oxide-semiconductor interface is
described in terms of the potential ΦS as in Figure  2.30. We notice that
ΦS = 0 is the flat band condition for the MOS (Figure 2.26). When ΦS < 0 , the
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 95

Inversion
n(interface) ≥ p0
Electric field E

Na p0

p
EC

Carrier Density
n
VG >> 0 n0
Ei

EF
Ev
qVG

Z
W
EFM

FIGURE 2.29
Band bending with increase of positive bias on the metal side of MOSFET.

At inversion
ΦS = 2ΦF

EC

Ei
qΦF
Surface
potential qΦs EF
EV

eΦF = EF – Ei
Positive for p-substrate
Negative for n-substrate

Oxide Semiconductor

FIGURE 2.30
Band bending of the semiconductor in the inversion mode.
96 Technology Computer Aided Design: Simulation for VLSI MOSFET

bands bend up at the surface and holes accumulate. Similarly when ΦS > 0 ,
depletion takes place, and finally when ΦS > 0 and greater than Φ F , the bands
bend in such a way that Ei lies below EF, resulting in inversion.
The onset of inversion is a gradual process and is a function of gate bias. The
strong inversion occurs when the electron concentration at the interface is equal
to the bulk p-type concentration. Strong inversion means the surface will be as
strongly n-type as p-type. So the intrinsic level Ei is at a position Φ F below the
Fermi level at the interface. The surface band bending is given in (2.91) as

ΦS (inv) = 2 Φ F (2.91)

For an n-MOSFET, the substrate is p-type and Φ F is positive, and a positive
ΦS is required for inversion. For a p-MOSFET the substrate is n-type and Φ F
is negative, causing inversion.
The charge density of the metal Qm is balanced by the channel depletion
charge Qd and the inversion charge Qn. We are interested in calculating the
threshold voltage (i.e., the gate voltage needed to cause inversion in the channel).
The total surface charge density is related to the surface field by Gauss’s
law. This charge QS is the total surface charge density at the semiconductor-
oxide interface region and includes the induced free charge in inversion and
the background ionic charge. The charge QS is zero when the bands are flat.
For a larger positive gate voltage the surface potential increases. The hole
concentration near the surface decreases while the electron concentration
increases, according to the following relationships:

 − qΦS 
p( x=0) = N a exp 
 kT  (2.92)

and

ni2  qΦ 
n( x=0) = exp  S  (2.93)
Na  kT 

since

 E − Ei 
n = ni exp  F (2.94)
 kT 

 E − EFi 
p = ni exp  i (2.95)
 kT 

np = ni2 (2.96)

Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 97

The electron surface concentration is equal to that of hole (n(0) = p(0) = ni),
when Ei coincides with EF at x = 0. This happens when

kT  N a 
ΦS = Φ F = ln  (2.97)
q  ni 

as shown in Figure 2.31.
With further increase in the gate voltage, the electron surface concentra-
tion increases up to a point where n(x = 0) becomes equal to ppo = Na which
is the original hole concentration in the substrate. This is because the band
curvature at the surface (x = 0) places Ei at an energy qΦF below EF. In other
words, the band curvature is equal to 2(Ei – EF) or ΦS = 2 Φ F .
When this condition is met, the semiconductor surface is said to be in
strong inversion.
For ΦF ≤ ΦS ≤ 2ΦF, the electron concentration is larger than the hole concen-
tration, and the surface is in weak inversion, while for ΦS ≥ 2 Φ F it is in strong
inversion as shown in Figure 2.32. The inversion layer is rich in electrons and
hence is a good conductor. The MOS capacitor consists of two conducting
electrodes (the metal gate and the inversion layer at the silicon surface). As
in the case of accumulation, the capacitance of the MOS structure is again
equal to Cox.
When an inversion layer is formed, electrons are the local majority carriers
at the surface. Any subsequent increase in gate voltage increases the electron
concentration in the inversion layer and produces a larger inversion charge
Qinv. However, the thickness of the inversion layer remains very small. Its
actual thickness is similar to that of an accumulation layer.
Concentration in Log Scale

Na
co Ho
nc
en le
tra
tio on
n ctr tion
Ele ntra
e
nc
co

ΦS
ΦF 2ΦF

FIGURE 2.31
Hole and electron concentration as a function of surface potential.
98 Technology Computer Aided Design: Simulation for VLSI MOSFET

EC

Ei
–qΦF
Surface
potential EF
ΦS = 2ΦF qΦF EV

–2qΦF

Metal Oxide Semiconductor Z

FIGURE 2.32
Band bending under strong inversion at the surface.

The electron charge in an inversion layer can be thought of as a surface

charge [40]. As in the case of an accumulation layer, the inversion charge
depends exponentially on the surface potential:

 qΦ 
Qinvα exp  S  (2.98)
 kT 

When the gate voltage is increased beyond inversion, the surface potential ΦS
increases very slightly above 2ΦF and one can assume that ΦS = 2ΦF when an
inversion layer is present. Because the semiconductor is p-type, the electrons
in the inversion layer are produced by a slow process called thermal genera-
tion at room temperature. They can also be produced by external generation
(if a light source is present). If the semiconductor is in the dark and at cryo-
genic temperature, the inversion layer may never form.
In summary the following rules will be used to describe the relationships
between the charge on the metal gate and the charge in the accumulation,
depletion, and inversion layers as shown in Figure 2.33.

−QG = Qacc  (accumulation) (2.99)

−QG = Qd  (depletion) (2.100)

−QG = Qd + Qinv  (inversion) (2.101)

−QG = charge at the back-side contact of the sample (dielectric mode)

Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 99

Oxide
Metal Silicon
Qacc

x x
QG
x=0

(a) (b)

QG QG
Qd Qd
x x

xd xdmax

Qinv
(c) (d)

FIGURE 2.33
Charges in the MOS structure: (a) flat band, (b) accumulation, (c) depletion, and (d) inversion.

2.15  Flat-Band Voltage: Effect of Real Surfaces

2.15.1  Equalization of the Fermi Levels
The Fermi level of the metal gate and the silicon are so far considered equal.
However, in practice this is not the case. In modern devices the gate material
is not actually a metal, but heavily doped polysilicon. The doping concentra-
tion for that material is so high (≈1020 cm–3) that it can be considered as a metal.
Let us first consider the metal and the semiconductor separately. The energy
needed to extract an electron with an energy EFM from the metal is called the
work function qΦ m. The work function in the semiconductor is denoted by qΦ sc .
The potential work function difference is Φ ms = Φ m − Φ s . It is to be noted that
Φ ms is negative for both n+ poly-silicon gate and n-type Si substrate and n+
poly-silicon gate and p-type Si substrate.
When a MOS structure is formed, the Fermi levels align, and the charge
transfer causes a tilt in the oxide conduction band [40,41]. The bands bend
down near the semiconductor surface to accommodate work function differ-
ence as shown in Figures 2.34(a),(b),(c). To go back to a flat-band condition a
voltage must be applied to the gate. This voltage called work function difference
is denoted by Φ ms :

EF − EFM
Φ ms = Φ m − Φ sc = (2.102)
q

100 Technology Computer Aided Design: Simulation for VLSI MOSFET

Vaccum

qΦm qΦsc EC

EC
EFM EFM EF
EV
EF
EV
Gate Gate
Metal Semiconductor Metal Semiconductor
oxide oxide
(a) (b)

EC
EFM
qΦMS
EF
EV

Metal Gate
Semiconductor
oxide
(c)

FIGURE 2.34
Energy band diagram of MOSFET when (a) the metal and the semiconductor are taken sepa-
rately, (b) no bias is applied, and (c) a bias equal to Φms is applied to the gate.

2.15.2 Oxide Charges

Oxides grown on silicon contain positive charges due to the presence of con-
taminating metallic ions or imperfect Si-oxide bonds [40]. These charges can
either be fixed or mobile in the oxide. However, for simplicity only the case
of fixed charges is considered.
Let us consider an elementary real positive charge Q(Coulomb m–2) at a
depth x in the oxide. Let x = 0 be defined at the metal/oxide interface as
shown in Figure 2.35(a). Negative charges will appear in the metal and the
silicon. The sum of these three charges is equal to zero. The charge in the
silicon can be removed when an appropriate negative bias is applied to the
gate as in Figure 2.35(b). If the charge is closer to the semiconductor, a larger
compensation gate bias is required to remove it. In an actual device, charges
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 101

ρ ρ

Q Q

tOX tOX

x x

x x

x=0 x=0

Metal Oxide Semi

Metal Oxide Semiconductor conductor

(a) (b)

FIGURE 2.35
Single charge in an oxide for (a) VG = 0 and (b) an applied gate voltage.

are distributed throughout the oxide. The compensating voltage is obtained

as equal to

QOX
VQ = (2.103)
COX

2.15.3  Interface Traps

A set of charges arise from the interface states at the Si-SiO2 interface.
They are created by the sudden termination of the semiconductor crys-
tal lattice at the oxide interface. In the oxidation process, Si reacts with
oxygen forming a SiO2 layer. When the oxidation process is suddenly
stopped, some ionic Si left near the interface causes perturbation to the
periodic crystal structure of the semiconductor and hence some Si-Si
bonds are unfulfilled or dangling. As a result there are energy states in
the band gap at the silicon surface. These states called interface states or
interface traps can be charged positively or negatively, and depending on
their nature and their energy with respect to the Fermi level will affect
the surface potential.

2.15.4  Flat-Band Voltage

Flat-band voltage is defined as the voltage that must be applied to the gate to
bring the semiconductor energy bands to a flat level. It can also be defined
as the voltage applied to the gate such that there is no band bending in the
102 Technology Computer Aided Design: Simulation for VLSI MOSFET

semiconductor. Flat-band is achieved by applying a gate voltage that com-

pensates for the following:

• The differences in work functions of the semiconductor and the

gate electrode
• The presence of charges in the oxide
• The interface traps

QOX Q
VFB = VQ + Φ ms + Vi = Φ ms − + i (2.104)
COX COX

For simplicity the various oxide and interface charges are included in an
effective positive charge Qit (C/cm2) at the interface. Qit includes both Qi and
QOX. This charge will introduce an effective negative charge in the semicon-
ductor. To compensate for these charges, a bias Vit = CQOXit must be applied to
the gate. Flat band voltage can be given as

Qit
VFB = Vit + Φ ms = Φ ms − (2.105)
COX

2.16  Expression of Threshold Voltage

The threshold voltage of a MOSFET is defined as the voltage that must be
applied to the gate to form an inversion layer. In a MOS transistor, the gate
voltage is equal to the sum of the potential drops in the semiconductor and
the oxide given as

QG
VG = ΦS + (2.106)
COX

where QG is equal to the positive charge on the gate electrode. An equal

amount of negative charge also exists in the semiconductor, composed of
ionized impurities in the depletion region, and the free electrons at the
oxide/silicon interface at the inversion. If the charge due to the free electrons
is assumed to be much smaller than that due to ionized impurities when the
inversion layer starts to form, the above equation can be written as

Qd
VG = 2 Φ F − = VTHO (2.107)
COX
VTH0 is called the ideal threshold voltage, and it is measured with respect to the
source [40].
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 103

The flat-band voltage in Equation (2.105) must be added to the expression

of the threshold voltage in (2.107), in order to accurately describe the actual,
“non-ideal” threshold voltage given as

Qd Q Q
VTH = VFB + 2 Φ F − = Φ ms − it + 2 Φ F − d (2.108)
COX COX COX

For strong inversion the voltage required must be strong enough to first
achieve the flat band condition (first two terms of Equation 2.108), then to
induce an inverted region (2ΦF term of Equation 2.108) and to accommodate
the charge in the depletion region (last term of Equation 2.108).
The threshold voltage may be either positive or negative, depending on the
doping concentration Na, the material used to form the gate electrode, etc. If the
threshold voltage is negative, the n-channel MOSFET is a depletion-mode device.
However, if VTH 0 is positive, the device is an enhancement-mode MOSFET.
Depletion-mode devices have an inversion layer when the gate voltage is
equal to zero. Such devices are sometimes referred to as “normally on.”
Enhancement-mode devices called “normally off” require an applied positive
gate bias to create the inversion layer. The value of the threshold voltage can
be adjusted by applying a controlled amount of doping impurities in the
channel region during device fabrication.

2.17  I–V Characteristics of MOSFET

The derivation of the MOSFET I–V relationship for different conditions
needs several approximations. The analysis of an actual three-dimensional
MOSFET would be a very complex task without these assumptions. Derivation
of closed form I–V equations is not possible without these assumptions. Here
gradual channel approximation (GCA) is used for deriving the I–V relationship,
which will effectively reduce the problem to a one-dimensional current flow
problem. This will allow us to devise simple current equations that are in
agreement with experimental results. However, GCA has limitations, par-
ticularly in the case of short-channel MOSFETs.

2.17.1  Gradual Channel Approximation

A semiconductor bar carrying a current I is considered in Figure 2.36. If Qd
coulombs per meter is the density of charge along the direction of current
and v meters per second is the velocity of the charge, then

I = Qd v (2.109)

The total charge that passes through a cross section of the bar per unit time can
be measured. With a velocity v, the charge enclosed in v meters of the bar must
104 Technology Computer Aided Design: Simulation for VLSI MOSFET

V meters

After one second

FIGURE 2.36
A semiconductor bar carrying current and snaps of the carriers after 1 second.

flow through the cross section in one second. Because the charge density is Qd,
the total charge in ‘v’ meters is given by Qd v .
In Figure 2.37(a) a coordinate system for the MOSFET structure is consid-
ered taking the x-direction parallel to the surface and the y-direction per-
pendicular to the surface. The origin of the x-coordinate is at the source end
of the channel. The channel voltage with respect to the source end is denoted
by V(x). Now let the threshold voltage Vth be constant along the entire chan-
nel region between x = 0 and x = L. However, in reality the threshold voltage
changes along the channel because the channel voltage is not constant. Let
the electric field component Ex along x-coordinate be dominant compared to
electric field component EY along the y-coordinate. This allows us to reduce
the current flow problem in the channel along the x-direction only.
Boundary conditions used are

V( x=0) = VS = 0 (2.110)

V( x=L) = VDS (2.111)

Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 105

+ –

Source VGS Drain

Gate VGS
+ –

n+ n+

x=0 L x
p-type substrate
y

(a) Body

VGS
+ –
VDS
Source Drain + –
Gate VGS
+ –

n+ n+
+ –

VDS
x=0 L x
p-type substrate
y

(b)
Body

FIGURE 2.37
(a) Channel charge with equal source and drain voltages and (b) with only drain voltage.

Let an n-channel MOSFET whose source and drain are connected to ground
be considered. When VGS = VTH, the inversion charge density produced by
the gate oxide capacitance is proportional to VGS – VTH. For VGS ≥ VTH, any
charge placed on the gate must be mirrored by the charge in the channel,
yielding a uniform channel charge density equal to

Qd = COX W (VGS − VTH ) (2.112)

COX is the gate/channel capacitance per unit area, where COX is multi-
plied by W to represent total gate capacitance per unit length. Sometimes
106 Technology Computer Aided Design: Simulation for VLSI MOSFET

expressions are described in terms of another capacitance known as gate/

channel capacitance Cg .

Cg = COX WL (2.113)

Now let the drain voltage taken be greater than zero as shown in Figure 2.37(b).
Because the channel potential varies from zero at the source end to VD at the
drain, the potential difference between the gate and the channel varies from
VG to VG – VD. Thus the charge density at a point x along the channel can be
written as

Qd ( x) = COX W[(VGS − V ( x) − VTH ] (2.114)

where V(x) is the channel potential at x. The drain current is given by

I D = −COX W[(VGS − V ( x) − VTH ]v (2.115)

In this expression the negative sign is inserted because the charge carriers
are negative and v denotes the velocity of the electrons in the channel. For
semiconductors v = μE, where μ is the mobility of charge carriers and E =
–dV/dx is the electric field.
Putting the value of v

dV ( x)
I D = COX W[(VGS − V ( x) − VTH ]µ n (2.116)
dx

The boundary conditions are V(0) = 0 and V(L) = VDS. Although V(x) can eas-
ily be found from this equation, the quantity of interest is I D . Integrating
(2.116) we get

L VDS

∫I D dx =
∫ WC OX µ n [VGS − V ( x) − VTH ] dV (2.117)
x= 0 V =0
The current equation of MOSFET in the triode region is given by

W 1
I D = µ nCOX [(VGS − VTH )VDS − V 2DS ] (2.118)
L 2
where L is the effective channel length.
Figure 2.38 plots the parabolas given by Equation (2.118) for different val-
ues of VGS. Calculating ∂ I D/∂VGS, one can show that the peak of each parabola
occurs at VDS = VGS – VTH, and the peak current is

1 W
I D ,max = µ nCOX (VGS − VTH )2 (2.119)
2 L
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 107

VGS3
Drain Current ID

VGS2

VGS1
VGS1 – Vth
VGS2 – Vth
VGS3 – Vth

Drain Voltage VDS

FIGURE 2.38
Drain current versus drain-source voltage in triode region.

Here, (VGS – VTH) is the overdrive or effective voltage and W/L is the aspect ratio.
If VDS ≤ VGS – VTH, we say the device is operating in the triode or linear region.

kn′ = µ nCOX is known as the process transconductance parameter.

W W
kn = kn′ = µ nCOX is known as the gain factor.
L L

Equations (2.118) and (2.119) serve as the foundation for analog and digital
CMOS VLSI design.
If in (2.118) VDS < 2(VG S – VTH), we have

W
I D ≈ µ nCOX [(VGS − VTH )VDS ] (2.120)
L

The drain current is a linear function of VDS. This is also evident from the
characteristics of Figure 2.38. For small VDS, each parabola can be approxi-
mated by a straight line. The linear relationship implies that the path from
the source to the drain can be approximated by a linear resistor equal to

1
Ron = (2.121)
µ nCOX W
(VGS − VTH )
L
108 Technology Computer Aided Design: Simulation for VLSI MOSFET

VGS3
ID

VGS2

VGS1 Approximate linear

operation in deep
triode region

VDS

FIGURE 2.39
Linear operation in deep triode region.

A MOSFET can therefore operate as a resistor whose value is controlled

by the overdrive voltage (as long as VDS < 2(VGS – VTH)). This is shown in
Figure 2.39. Thus in triode region, MOSFET operates as a voltage controlled
resistor as in Figure 2.40.
However, if in Figure 2.38 the drain-source voltage exceeds VGS – VTH, the
drain current does not follow the parabolic behavior for VDS > VGS – VTH. In
fact, as shown in Figure 2.41, ID becomes relatively constant, and we say that
the device operates in the saturation region as in [38,41].
If the drain voltage remains greater than the source voltage, then the volt-
age at each point along the channel with respect to ground increases as we
move from the source end toward the drain end. From Figure  2.42(a), this
effect arises from the gradual voltage drop along the channel resistance.
Because the gate voltage is constant (as the gate is conductive but carries no
current in any direction) and the potential at the oxide-silicon interface rises
from the source to the drain end, the potential difference between the gate

Gate

Gate Gate

Source Drain Source Drain

Source Drain

FIGURE 2.40
MOSFET as a voltage-dependent resistor.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 109

VDS(sat) = VGS – Vth

VGS = 3.25 V
500 µA

400 µA Saturation region

Triode VGS = 2.75 V

ID 300 µA
region

200 µA VGS = 2.3 V

100 µA
VGS = 0.45 V(Cutoff region)

1 2 3 4 5
VDS in (V)

FIGURE 2.41
Plots showing saturation of drain current.

and the oxide-silicon interface decreases along the x-axis as in Figure 2.42(b).

The density of electrons in the channel follows the same trend, falling to a
minimum value at x = L.
The local density of inversion layer charge is proportional to VGS − V ( x) − VTH .
So if V(x) approaches VGS − VTH, then Qd ( x) drops to zero. In other words, as
in Figure 2.43(a), if VDS is slightly greater than VGS − VTH , then the inversion

VG
– + VD
+ –

n+ n+
X-direction
ID

Potential
= VG <VG = VG – VD
difference

V(x) VG
Gate to body potential
drop

VG – VD
L x L x
(a) (b)

FIGURE 2.42
(a) Channel potential variation. (b) Gate-substrate voltage difference along the channel.
110 Technology Computer Aided Design: Simulation for VLSI MOSFET

VGS
+ –
VDS
S G +1 –

n+ n+

Pinch off
V(L) = VGS – Vth
X-direction
x=0 L
p-type substrate
y

(a)
Body

VGS
+ –
VDS2 > VDS1
S G + –

n+ n+

Pinch off

X-direction
x=0 L1 L
p-type substrate y V(L1) = VGS – Vth

(b)
Body

FIGURE 2.43
(a) Pinch-off condition. (b) Pinch-off point shifts to source end for increasing VDS.

layer stops at x ≤ L, and the channel is pinched off. As VDS increases further,
as in Figure 2.43(b), the point where Qd equals zero gradually moves toward
the source. So at some point along the channel, the local potential difference
between the gate and the oxide-silicon interface is not sufficient to support
an inversion layer.
No channel exists between L1 and L. But the device still conducts, as illus-
trated in Figure 2.44. Once the electrons reach the end of the channel, they
experience the high electric field in the depletion region at the drain junction
and are rapidly swept to the drain terminal.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 111

VG
VS = 0
– +
VD
+ – Drain

ID

n+ n+
n+
E
x
0 L1 L

FIGURE 2.44
Detailed operation in the pinch-off region.

From the above observations, we examine (2.117) for a saturated device.

The integral on the left-hand side of (2.117) must be taken from x = 0 to x =
L1, where L1 is the point at which Qd drops to zero, and that on the right from
V(x) = 0 to V ( x) = VGS − VTH. As a result,

L1 VGS −VTH

∫I
x= 0
D dx =
∫
V =0
WCOX µ n [VGS − V ( x) − VTH ] dV

which gives

1 W
I D ,max = µ nCOX (VGS − VTH )2 (2.122)
2 2 L1
Considering the approximation L ≈ L1, a saturated MOSFET can be used
as a current source connected between the drain and the source. Current
sources draw current from VDD or inject current into ground as shown in
Figure 2.45.

VDD

VDD
I1

I1
VG VG
I2
I2

FIGURE 2.45
MOSFET acting as a current source.
112 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.18  Depletion MOSFET

Some devices have an already fabricated channel even at zero gate voltage.
Negative gate voltage is required to turn them off [41]. Such a normally on
device is known as a depletion-type MOSFET. The MOSFETs that are off at
zero gate bias are termed enhancement-type MOSFET. On application of a gate
voltage the device turns on.
Figure 2.46 shows an n-channel depletion-type MOSFET. A doped n-chan-
nel region exists under the oxide, meaning that an electron inversion layer
already exists with zero applied gate bias. In this type of device, a negative
gate voltage will induce a space charge region underneath the oxide, reduc-
ing the thickness of the n-channel region. The reduced thickness decreases
the channel conductance, which in turn, reduces the drain current. A positive
gate voltage will create an electron accumulation layer, increasing the drain
current. The ID – VDS characteristics and symbol for an n-channel depletion
MOSFET are shown in Figures 2.47(a),(b). Figure 2.48 shows the ID – VGS curve
for depletion mode and enhancement mode MOSFET.

Source Gate Drain

n+ n+
Ion implanted n-type
channel layer
p-type
substrate

B
VB = 0

FIGURE 2.46
Structure of a depletion MOSFET.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 113

Drain
VDS(sat) = VGS – Vth
ID VGS2 > VGS1 ID
VGS1 > 0

VGS = 0
Gate Body

VGS3 < 0

Source

VDS
(a) (b)

FIGURE 2.47
(a) ID versus VDS characteristics for an n-channel deletion mode MOSFET. (b) Symbol of an
n-channel deletion mode MOSFET.

ID

Enhancement mode
Depletion mode

VGS

FIGURE 2.48
ID –VGS characteristics for depletion mode and enhancement mode MOSFETs.

2.19  Transconductance (g m)
Since a MOSFET operating in saturation region produces a current in response
to its gate-source overdrive voltage, we define a figure of merit that indicates
how well a device converts a voltage to a current. In processing signals we deal
with the changes in voltages and currents, so here we define a figure of merit
as the change in the drain current divided by the changes in the gate-source
voltage, called the transconductance, denoted by gm, expressed as

∂ID
gm =
∂VGS VDS = cons tan t

W
g m = µ nCOX (VGS − VTH ) (2.123)
L
114 Technology Computer Aided Design: Simulation for VLSI MOSFET

gm gm gm

ID VGS – Vth W/L VGS – Vth W/L ID

Constant Constant Constant

FIGURE 2.49
Variation of trans-conductance of MOSFET

gm represents the sensitivity of the device. When gm is high, a small change

in VGS results in a larger change in ID ⋅ gm in the saturation region is inverse of
Ron in the deep triode region.
Also,

2 ID
VGS − VTH =
W (2.124)
µ nCOX
L

Putting the value of (2.124) in (2.123), we get

W
g m = 2 I Dµ nCOX (2.125)
L

2 ID
gm = (2.126)
VGS − VTH

gm of a MOS transistor can be increased by increasing its width. However,

this will also increase the input capacitance and the area occupied. Equation
(2.123) suggests that gm increases with the overdrive if W/L is constant,
whereas (2.126) shows that gm decreases with the overdrive if ID is constant.
From (2.125) we see that gm increases in square law with ID if W/L is constant.
These results are illustrated in Figure 2.49.

2.20  Channel Length Modulation

When VDS = VDSSat = VGS − VTh, the inversion layer charge at the drain end
becomes zero. We can say that the channel is pinched off at the drain end
for this bias condition. If the drain-to-source voltage is increased beyond the
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 115

VGS VDS
VGS ≥ Vth
VDS ≥ VGS – Vth

p-substrate

δL

FIGURE 2.50
Reduction of channel length at saturation.

saturation voltage so that VDS > VDSSat, an even larger portion of the chan-
nel becomes pinched off. The effective channel length (i.e., the length of the
inversion layer) is reduced to L − ΔL, where ΔL is the length of the channel
region where inversion charge is equal to zero as in Figure 2.50. The pinch-
off point moves from drain end to the source end caused by increasing drain-
to-source voltage. The electrons traveling from the source toward the drain
traverse the inverted channel section of length L and then are injected into
the depletion region of length L − L′ = ΔL which separates the pinch-off point
from the drain end.
The voltage remains constant at VGS − VTH = VDSsat, and the additional bias
applied to the drain appears as a voltage drop across the narrow depletion
region between the channel end and the drain region. This voltage acceler-
ates the electrons at the drain end of the channel and sweeps them across
the depletion region into the drain. The channel length is reduced from L to
L − ΔL, a phenomenon known as channel-length modulation which is similar to
base-width modulation in BJT. The shortening of the channel causes a larger
current called channel-length modulation.
Channel-length modulation in a MOSFET is caused by the increase of the
depletion layer width at the drain end with increased drain voltage. This
leads to a shorter channel length and an increased drain current. An exam-
ple of this is shown in Figure 2.51(a). The channel-length-modulation effect
increases in small devices with low-doped substrates as in Figure 2.51(b).
116 Technology Computer Aided Design: Simulation for VLSI MOSFET

Drain current
ID

With channel
length modulation

Without channel
length modulation

Drain voltage
(a)

Source Drain
end end

∆L

L
(b)

FIGURE 2.51
(a) Effect of increase in the drain current as a result of channel length modulation. (b) Channel
length modulation.

From (2.122) we get

−1
 L
I D α1/(L − L) = 1/L  1 −  (2.127)
 L 

Neglecting higher-order terms in the series, we get

 L
I D = 1/L  1 +  (2.128)
 L 

Let

L
= λVDS (2.129)
L
where λ is the channel-length modulation parameter.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 117

Again from (2.122),

W
I D = µCOX (VGS − Vt )2 (2.130)
2L
Due to channel-length modulation, the effective channel length becomes L − ΔL.
The drain current in saturation can be written as

W
I D = µCOX (VGS − Vt )2
2(L − L)

W
I D = µCOX (VGS − Vt )2 (1 + λVDS ) (2.131)
2L

The above equation is the modified current equation of a MOSFET consider-

ing channel-length modulation.
The saturation current is not dependent on drain bias if one does not con-
sider channel-length modulation (λ = 0). However, in reality the saturation
mode current increases linearly with drain bias. The slope of this current–
voltage curve in the saturation region is determined by the channel-length
modulation parameter λ. Thus, in the saturation region the graph is not a
straight line, and there is finite slope caused by channel-length modulation
as in Figure 2.51(a).
The I D − VDS characteristics showing the effect of channel-length modula-
tion are shown in Figure 2.52. The observed linear dependence of I D on VDS
in the saturation region is represented in (2.131) by the factor (1 + λVDS). From
Figure 2.52 it is seen that when the straight-line I D − VDS characteristics are
extrapolated, they intercept the VDS axis at the point VDS = −VA , where VA

VGS2

ID
VGS1

VGS2 > VGS1

– 1 Drain Voltage
λ

FIGURE 2.52
Effect of VDS on I D in the saturation region.
118 Technology Computer Aided Design: Simulation for VLSI MOSFET

is a positive voltage. Equation (2.131) indicates that ID = 0 at VDS = –1/λ. It fol-

lows that VA = 1/λ.
Therefore, VA is a process-technology parameter with the dimensions of V.
For a given process, VA is proportional to the channel length L that the designer
selects for a MOSFET. The voltage VA is referred to as the Early voltage.
Equation (2.131) shows that when channel-length modulation is taken into
account, the saturation values of I D depend on VDS . Thus, for a given VGS,
a change VDS causes a corresponding change I D in the drain current I D .
The output resistance of the current source representing I D in saturation is
no longer infinite. The output resistance ro is defined as

−1
 ∂I 
r0 =  D  (2.132)
 ∂VDS VGS = constant
−1
 K/ W  1 V
r0 =  λ n (VGS − Vt )2  = = A (2.133)
 2 L  λI D ID

Thus the output resistance is inversely proportional to the drain current [39,40].
The output conductance gDS can be expressed as

 ∂I 
g DS =  D  = λI D (2.134)
 ∂VDS VGS = constant

λ is proportional to 1/L, and I D is proportional to 1/L:

1
λα (2.135)
L

1
I Dα (2.136)
L

Output conductance g DS is strongly dependent on channel length, and this

strong dependence is expressed by

2
 1
g DSα  
 L

Unlike the Early effect in bipolar devices, the amount of channel-length

modulation is under the circuit designer’s control. Because λ is inversely
proportional to L, for a longer channel, the relative change in L for a given
change in VDS is smaller. We may conclude that channel length modulation
is more prominent in short-channel devices as shown in Figure 2.53.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 119

ID L1 ID L2 > L1

VDS VDS

FIGURE 2.53
Channel length modulation is more prominent for short-channel devices.

2.21  Substrate Bias Effects

The derivation of linear mode and saturation mode current-voltage char-
acteristics is done based on the assumption that the substrate potential is
equal to the source potential (i.e., VSB = 0). The threshold voltage is calcu-
lated without considering the substrate voltage. However, in many digital
applications, the source potential can be larger than the substrate potential
(i.e., VSB > 0). The influence of non-zero VSB must be accounted for by the
threshold voltage VT. So the modified VT must be applied to the current
characteristics. The threshold voltage is a function of the bulk-to-source
voltage VBS through the substrate bias effect or backgate effect. The application
of VBS (a negative voltage to avoid forward biasing the bulk-to source p-n
junction) increases the depletion width, which increases the bulk charge as
shown in Figure 2.54 and, thus, the threshold voltage. A solution to avoid
the backgate effect is to make VBS = 0 by electrically shorting the source to
the bulk as in Figure 2.55.

VG VG
+ – + –
VB = 0 VB < 0
S
B B S

p+ n+ n+ p+ n+ n+
Negative depletion Depletion
p-substrate charge Qd p-substrate charge Qd

FIGURE 2.54
Variation of depletion charge with body effect.
120 Technology Computer Aided Design: Simulation for VLSI MOSFET

Source and bulk terminal shorted

Active contact
for bulk

p+ n+ source n+ drain

p well

n type substrate

FIGURE 2.55
Source and bulk are tied together to reduce backgate effect.

2.22  MOS Transistor as a Switch

When a MOS transistor is in the linear region, the device acts as a linear
resistor under gate voltage control. The transistor can be used as an on–off
switch, as in Figure 2.56, if it operates in linear and cutoff regions. When the
transistor is on, it operates in the linear region. The switch is turned off and
the channel disappears by setting VGS = 0 . Hence, only a small amount of
leakage current flows at the drain end. The switch is turned on by setting
VGS = VDD , and the current path provides a resistance Rch. For a p-channel
MOSFET the switch is turned on if VGS = VDD. If the transistor is connected
in series with a high-impedance circuit, the total current flowing through
the transistor and the voltage drop VDS = I ds Rch across the channel will be
very small. In this context an input voltage source signal, VDS = I ds Rch, which
is either zero or VDD representing logical 0 or 1, respectively, is applied as
shown in Figure 2.57. The output voltage Vo is either held at its previous logic
value (if the switch is open) or its capacitance C is charged up to Vin (if the
gate voltage allows the transistor path to be closed). The transistor used in
this way is called a pass transistor, and the process of transferring the charge
from the input node to the output under the influence of gate voltage is called
charge steering.

0 Switch
open

1
Switch
closed

FIGURE 2.56
MOS transistor as a switch.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 121

C Vout
Vin

FIGURE 2.57
MOSFET as a pass transistor.

2.23  MOSFET Capacitance

The importance of capacitance is that it determines the delay or the speed of
the circuit. In this section some basic facts about capacitance in a MOS device
are presented. The capacitance of a MOS network depends on a number of
factors, such as the physical structure of the MOS devices, the terminal volt-
ages, and the network topology. We discuss these factors briefly.

2.23.1  Overlap Capacitance

The gate of the MOSFET is isolated from the conducting channel by the gate
oxide layer that has a capacitance per unit area equal to COX = εtoxox . From the
basic drain current equation of MOSFET, it is seen that COX must be made
as large as possible (i.e., the oxide thickness tOX must be very thin). The total
value of this capacitance is called the gate capacitance CG, and it can be divided
into two elements, each with a different behavior. One part of CG contributes
to the channel charge and is discussed in a subsequent section. Another part
is solely due to the topological structure of the transistor. Let the transistor
structure of Figure 2.58 be considered.

Polysilicon gate
Top view

Source Drain
W

xd xd

Ld Gate-body
overlap

FIGURE 2.58
Overlap capacitance in MOSFET.
122 Technology Computer Aided Design: Simulation for VLSI MOSFET

Ideally, the source and drain regions should end at the edge of the gate
oxide. In reality, both the source and the drain tend to extend somewhat
below the oxide by an amount xd, called the lateral diffusion length. Hence, the
effective channel of the transistor L becomes shorter than the length Ld (the
length the transistor was originally designed for) by a factor ΔL = 2xd. It also
gives rise to a parasitic capacitance between the gate and the source (drain)
that is called the overlap capacitance. This capacitance is strictly linear and has
a fixed value:
CGSO = CGDO = COXxdW = COW (2.137)

Because xd is a technology-determined parameter, it is customary to com-

bine it with the oxide capacitance to yield the overlap capacitance per unit
transistor width Co .

2.23.2  Channel Capacitance

This is the most important MOS parasitic circuit element, the gate-to-channel
capacitance CGC is divided into CGCS, CGCD, and CGCB (being the gate-to-source,
gate-to-drain, and gate-to-body capacitances, respectively), depending upon
the operation region and terminal voltages. This varying distribution is
best explained with the simple diagrams of Figure 2.59. When the transis-
tor is in cutoff as in Figure 2.59(a), no channel exists, and the total capaci-
tance CGC appears between the gate and the body. In the resistive region
as in Figure 2.59(b), an inversion layer is created, which acts as a conductor
between the source and the drain. Consequently, CGCB = 0 as the body elec-
trode is shielded from the gate by the channel. From symmetry, the capaci-
tance distributes evenly between source and drain. Finally, in the saturation
mode as in Figure 2.59(c), the channel is pinched off. The capacitance between
gate and drain is approximately zero, and so is the gate-body capacitance.
Hence, all the capacitances are between the gate and the source.
The actual value of the total gate-channel capacitance and its distribution
over the three components is best explained with the help of a number of
charts. The plot in Figure 2.60(a) shows the evolution of the capacitance as a

G G G
CGC CGC CGC

S D S D S D

(a) Cut off (b) Resistive (c) Saturation

FIGURE 2.59
The gate-to-channel capacitance and their distribution over the other three terminals depend-
ing upon the operation region.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 123

WLCOX
CGC

CGCB
WLCOX/2
CGCS = CGCD

Vth VGS
(a)

CGC
WLCOX

CGCS
2WLCOX/3
WLCOX/2
CGCB

0 1
VDS/(VGS – Vth)
(b)

FIGURE 2.60
Distribution of the gate-channel capacitance as a function of VGS and VDS. (a) CGC as a function
of VGS when VDS = 0. (b) CGC as a function of degree of saturation.

function of VGS for VDS = 0. For VGS = 0, the transistor is off as no channel is
present, and the total capacitance, equal to WLCox, appears between the gate
and the body. When VGS is increased, a depletion region is formed under the
gate. This causes the thickness of the gate dielectric to increase, which means
a reduction in capacitance. Once the transistor turns on (VGS = Vth), a channel
is formed and CGCB drops off to 0. With VDS = 0, the device operates in the
resistive mode and the capacitance divides equally between the source and
the drain, or CGCS = CGCD = WLCox/2. A designer must avoid operation in this
region.
When the transistor is on, the distribution of its gate capacitance depends
on the degree of saturation, measured by VDS/(VGS – Vth). As in Figure 2.60(b),
CGCD gradually drops to 0 for increasing levels of saturation, while CGCS
increases to 2/3 COXWL. This also means that the total gate capacitance
decreases with an increased level of saturation.
124 Technology Computer Aided Design: Simulation for VLSI MOSFET

Channel stop implant NA+

Source
W ND

Bottom

xj Side wall
Channel
LS
P-type substrate NA

FIGURE 2.61
Schematic view of the source junction.

2.23.3 Junction Capacitances

Another capacitive component is contributed by the reverse-biased source-
body and drain body p-n junctions. The depletion-region capacitance is non-
linear and decreases when the reverse bias is increased. To understand the
components of the junction capacitance (called the diffusion capacitance), we
must look at the source (drain) region and its surroundings. The detailed
picture, shown in Figure  2.61, shows that the junction consists of two
components.
The bottom-plate junction is formed by the source region (with doping ND)
and the substrate with doping NA. The total depletion region capacitance for
this component equals CBottom = CJWLS, with CJ as the junction capacitance
per unit area.
The side-wall junction is formed by the source region with doping ND
and the p+ channel-stop implant with doping level NA+. The doping level
of this stopper is usually greater than that of the substrate, resulting in a
larger capacitance per unit area. Its capacitance value equals C SW = C’JSWxj
(W + 2L S). It is to be noted that no side-wall capacitance is counted for
the fourth side of the source region, as this represents the conductive
channel. Because x J, the junction depth, is a technology parameter, it is
normally combined with C′JSW to give a capacitance per unit perimeter,
CJSW = C′JSW. x J. An expression for the total junction capacitance can then
be derived as

CDiff  = CBottom + CSW = CJ* AREA + CJSW

*  PERIMETER
= CJLSW + CJSW (2LS + W) (2.138)
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 125

Gate

CGD
CGS

Source Drain

CSB
CDB
Bulk

FIGURE 2.62
Different capacitances in MOSFET.

2.23.4  Different MOS Capacitors Together

All the above contributions can be combined in a single capacitive model
for the MOS transistor, shown in Figure 2.62. Its components are identified
based on the preceding discussions.

CGS = CGCS + CGSO; CGD = CGCD + CGDO (2.139)

CGB = CGCB (2.140)
CSB = CSdiff; CDB = CDdiff (2.141)

2.23.5  Summary of MOS Capacitances

The structure of a MOS transistor is that of a parallel-plate capacitor. The
oxide layer acts as an insulator between the two conducting plates: the gate
(in polysilicon or metal) and the substrate. The parallel-plate capacitance per
unit area is given as

ε0ε r
COX = farad/cm2 (2.142)
tox
where εr = 3.9 is the dielectric constant of the oxide, ε0 = 8.85 × 1014 F/cm2 is
the free-space permittivity, and tox is the oxide thickness. The value of COX
remains relatively constant but decreases slightly with increase in substrate
126 Technology Computer Aided Design: Simulation for VLSI MOSFET

voltage. For semiconductors, the capacitance values are very small and are
expressed in units of picofarad (10 –12 farad, denoted by pF) or femtofarad
(10 –15 farad, denoted fF). Similar parallel-plate capacitances are also formed if
any overlap regions exist between the gate and the source or the gate and the
drain. Even for self-aligned process, a certain amount of channel capacitance
between the gate-to-source and the gate-to-drain will exist. These capaci-
tances are denoted CGSO and CGDO, respectively, and must be added with COX
to find the total gate capacitance CG of the MOS transistor because they are
all connected in parallel. The values of these capacitances are specified by the
manufacturer with gate voltage VG, negative or zero—that is, with no deple-
tion region underneath the gate. With an increase in the gate voltage the
phenomena of accumulation, depletion, and inversion start to take place. A
depletion capacitance CD, formed between the gate and the depletion region
boundary, connected in series with COX lowers the effective gate capacitance
CG. This is shown in Figure 2.63. The value of CD depends on the depth of the
depletion region. The initial depth of the depletion region depends on the
built-in contact or barrier potential (typical value 0.7 V) and then increases
with increasing VGS. As VGS is increased so as to exceed the threshold volt-
age Vth, inversion takes place and the channel forms the conducting plate
instead of the substrate, the depletion capacitances no longer exist, and the
total capacitance shows a marked increase compared to its original oxide
capacitance value.
Here we have assumed that the gate voltage is static or varies very slowly
so that the phenomena of accumulation, depletion, and inversion take place
in proper sequence. If V varies very rapidly (i.e., when the signal frequency
of the gate voltage is rather high), the channel may not be formed. On aver-
age the device will appear to be in the depleted state all the time, bringing
in the effects of the depletion capacitances CD to reduce the total capacitance
(Figure 2.63). This dynamic behavior of the capacitance does not really con-
cern us because we will have to operate at considerably lower frequency to
guarantee proper switching of each transistor.
It is seen that one part of the capacitances CGS and CGD is due to the gate
overlaps at the source and the drain sides. Even if there is no overlap, it is

Gate
capacitance

Vth VGS

FIGURE 2.63
Variation of the gate capacitance with gate voltage.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 127

useful to visualize CG as consisting of a parallel connection of CGCS and CGCD

because the channel can be viewed as a physical extension of the source and
the drain regions. When the transistor is operating in the linear region, the
two component capacitances have almost equal value; that is, CGCS = CGCD =
0.5 CGC = 0.5 COXWL. When the transistor is saturated, the channel disappears
near the drain end and we can assume that CGCS = CGC = 2/3 COXWL.

2.23.6  Interconnect Capacitances

The so-called stray or wiring capacitances of the paths connecting the active
channels could become significantly high, depending on the length of the
wire, accounting for a major part of the circuit delays. This is because the
wiring capacitances need to be charged up together with the gate capaci-
tances for signals to be detected by the transistors. It is therefore convenient
to be able to express the wiring capacitances in terms of the gate capacitance
of a transistor of some standard size. It is also important to recognize that the
diffusion wires are buried in the substrate, and their capacitance depends
on two factors: the total area and the perimeter of the wire. The perimeter
determines the so-called “side-wall” capacitance, which is at least 20% of the
capacitance determined by the total area.
The relevant capacitances are denoted as

CG: gate capacitance (pF/μm2)

Cpln: p-channel source—drain capacitance
Cnln: n-channel source—drain capacitance
Cmf: metal-to-field oxide capacitance
Cmp: metal-to-polysilicon capacitance
Cmt: metal-to-oxide capacitance
Cpf: polysilicon-to-field oxide capacitance

2.24  Moore’s Law

Since the invention of the first calculation machines, miniaturization has been
a constant challenge to increase speed and complexity in the microelectron-
ics industry. Linear scaling of device dimensions to a quasi-nanometer level
allows building a complex system integrated on a chip which reduces the vol-
ume and power consumption per function, while increasing speed [42–45].
The steady downscaling of transistor dimensions over the past two decades
has been the main stimulus to the growth of silicon integrated circuits (ICs)
and the information industry. Moore’s law [42], which states that the number of
128 Technology Computer Aided Design: Simulation for VLSI MOSFET

transistors on a given chip can be doubled every two years, has been the guid-
ing principle of the continuous reduction of CMOS device dimension since
Gordon Moore, co-founder of Intel, first predicted it in 1965. Over the last few
decades, CMOS devices have been scaled down to the sub-100-nm regime.
Although the basic device geometry has remained relatively unchanged, the
gate length has been reduced from 10 mm in the 1970s to less than 0.1 μm in
2001, and the gate oxide thickness from 1000 Å to less than 20 Å [43].

2.25  Introduction to Scaling

MOS transistors are scaled primarily due to the two reasons mentioned below:

1. Increased device packing density: The design of high-density chips in

MOS VLSI technology requires that the packing density of MOSFETs
be as high as possible, such that the sizes of the transistors are as
small as possible.
2. Improved frequency response (transit time) is proportional to 1/L:
If the length of the device is small, then the transit time required
for the charged carrier to move from the source to the drain end is
small, and thus the device can be operated at higher frequencies.

Two types of scaling are common:

• Constant field scaling

• Constant voltage scaling

Constant field scaling warrants a reduction in the power supply voltage as the
minimum feature size is decreased, but it yields the largest reduction in the
power-delay product of a single transistor. In contrast, power supply voltage is
not reduced in the constant voltage scaling and is therefore the preferred scaling
method because it provides voltage compatibility with older circuit technologies.
The disadvantage of the constant voltage scaling is that the electric field increases
as the minimum feature length is reduced. This leads to velocity saturation, mobil-
ity degradation, increased leakage currents, and lower breakdown voltages.

2.26  Constant Field Scaling

The principle of constant field scaling is that the device dimension and the
device voltages are to be scaled in such a way that both the horizontal and
vertical electric fields remain essentially constant [46]. To ensure the reliabil-
ity of the device, the electric field in the scaled device must not increase. This
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 129

scaling attempts to preserve the magnitude of internal electric fields in the

MOSFET, while the dimensions are scaled down. To achieve this, all voltages
must be scaled down in proportion to the device dimension.
The channel length is scaled from L to αL (α > 1). To maintain a constant
horizontal electric field, drain voltage must be scaled from VDS to VDS/α. The
gate voltage should also be scaled from VGS to VGS/α, so that the gate and the
drain voltages remain compatible. To ensure a constant vertical electric field,
gate oxide thickness must also be scaled from tox to tox/α.
Because the channel length is being reduced, the depletion width also
needs to be reduced. If the substrate doping concentration is increased by
the factor (α), then the depletion width is reduced approximately by the same
factor α, because VDS is reduced by 1/α.

2.27  Constant Voltage Scaling

In constant voltage scaling, all dimensions of the MOSFET are reduced by a
factor of α (>1) as in constant field scaling. The power supply voltage and the
terminal voltages, on the other hand, remain unchanged. Because the chan-
nel length is being reduced, the depletion width also needs to be reduced. If
the substrate doping concentration is increased by the factor (α2), then deple-
tion width is reduced approximately by the factor α.

2.28 Why Constant Voltage Scaling Is More

Useful than Constant Field Scaling
In constant field scaling, the scaling of voltages will be unpractical in many
cases. In particular, the peripheral and interface circuitry may require cer-
tain voltage levels for all input and output voltages. To accommodate the
different voltage levels, the multiple power supply arrangement is necessary,
and complicated level shifters are required. To get rid of these external volt-
age level constraints, constant voltage scaling is preferred, knowing that it
can cause serious device reliability issues. In actual technology evolution,
the voltages need not be reduced with the same scaling factor.

2.29  ITRS Roadmap for Semiconductors

Due to the significant resources and investments required to develop the
next generation of CMOS technologies, it is necessary to identify goals and
put collective efforts toward developing new equipment and technologies.
130 Technology Computer Aided Design: Simulation for VLSI MOSFET

100 nm
102 node
LG = 65 nm
35 nm node tOX = 13Å LG = 80 nm
Ioff (nA/micrometer)

LG = 22 nm
tOX = 16Å
tOX = 5.5Å LG = 100 nm
tOX = 19Å 180 nm node
LG = 140 nm
101 tOX = 25Å

LG = 70 nm 130 nm node
tOX = 14Å LG = 120 nm
LG = 85 nm
tOX = 22Å
tOX = 17Å

100
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Target Supply Voltage (V)

FIGURE 2.64
ITRS roadmaps for high-performance technologies for the year 1999. Plot of target IOFF versus
VDD [47].

The semiconductor roadmap represents a consensus among industry leaders

and gives projected needs based on past trends. The International Technology
Roadmap for Semiconductors (ITRS) [47] is the standard accepted roadmap.
Figure 2.64 shows the roadmap specifications for drive current and off-state
leakage current for high-performance circuits, along with the associated
power supply voltages and the technology nodes. The drive currents of the
nMOSFET/pMOSFET are fixed at constant values of 750/350 µA/µm, while
the off-state leakage current continually increases with scaling. The gate
insulator needs to be aggressively scaled down to improve the drive current
and to suppress short-channel effects. In the 130 nm technology node with
a 70 nm physical gate length, the gate oxide thickness is only 15 Å, which is
approximately six atomic layers thick. To continue past trends in CMOS scal-
ing, a sub-10 Å effective oxide thickness will soon be required, which is about
four atomic layers thick. Beyond that point, SiO2 may lose its properties as an
insulator, and we may need a different materials system. The roadmap distin-
guishes two different applications: high-performance and low-power circuits.
In summary, scaling improves cost, speed, and power per function with
every new technology generation. All of these attributes have been improved
by 10 to 100 million times in four decades—an engineering achievement
unmatched in human history.

2.30  Different Groups of MOSFETs

Moving a design from an old technology to a newer one, with smaller
design rules, has always been an interesting way to lower power consump-
tion and to obtain higher speed. The overall parasitic capacitances (i.e., gates
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 131

and interconnects) are decreased, the available active current per device
is higher, and consequently, the same performance can be achieved with
a lower supply voltage. Moving to a new technology generation, however,
induces a scale down of the power supply voltage (Vdd), the threshold voltage
(Vth), and the gate oxide thickness (TOX). Starting from the 0.18 μm technolo-
gies, it appeared that building a transistor with a good active current (Ion)
and a low leakage current (Ioff) was becoming more difficult. The four main
causes of limitations are as follows:

1. Voltage limits and subthreshold leakage

2. Tunneling currents
3. Statistical dispersions
4. Poly depletion and quantum effects

Two families of transistors were introduced: high-speed transistors and low-

leakage transistors. The threshold voltages of the two families are tuned dif-
ferently, using different channel doping. When moving to more advanced
technologies, those two families are no longer sufficient regarding techno-
logical constraints. The ITRS introduces three main groups of transistors:

1. High performance (HP)

2. Low operating power (LOP)
3. Low standby power (LSTP)

A new kind of MOS device has been introduced in deep submicron technolo-
gies, starting from the 0.18 µm CMOS process generation. The new MOS,
called a low leakage MOS device, is available as well as the original, called
high-speed MOS.
For I/Os operating at high voltage, specific MOS devices called high volt-
age MOS are used. The high voltage MOS is built using a thick oxide, two to
three times thicker than the low voltage MOS, for handling high voltages, as
required by the I/O interfaces, shown in Figure 2.65(a),(b), and (c).

IDS High Voltage

High Speed Low Leakage
IDS IDS
VGS = 3.3V
ION VGS = 1.8V
ION VGS = 1.8V
VGS = 1.8V

VDS VDS VDS

FIGURE 2.65
Three different types of MOSFETs introduced by ITRS roadmap.
132 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.31  Short-Channel Effects of MOSFET

A MOSFET device is considered to be short when the channel length is of
the same order of magnitude as the depletion-layer widths (xdD, xdS) of the
source and the drain junctions. Short-channel effects occur as the channel
length L is reduced to increase both the operation speed and the number of
components per chip.
The short-channel effects are attributed to two physical phenomena:

1. The limitation imposed on electron drift characteristics in the channel

2. The modification of the threshold voltage due to the shortening of
the channel length

Reduction of channel length of MOSFETs leads to the short-channel effects

such as:

• Reduction in the threshold voltage

• Drain-induced barrier lowering
• Increase in the saturation drain current with increasing VDS
• Increase in the off-state leakage current
• Punch-through effect
• Mobility degradation
• Increase in the parasitic resistance and the capacitance
• Hot carrier effect

All these effects are discussed in detail in the following sections.

2.32  Reduction of the Effective Threshold Voltage

In a long-channel device, channel formation is controlled by the gate and
the substrate. The gate voltage controls all the space charge induced in the
channel region. As the channel length decreases, the charge in the channel
region decreases. As the drain bias is increased, the reverse biased space
charge region at the drain extends farther into the channel and the gate con-
trol decreases (i.e., in a short-channel device the n+ type source and the drain
induce a large amount of the depletion charge which cannot be neglected).
For short-channel devices, the charge control of the channel is shared by the
four terminals (gate, substrate, source, and drain), called charge sharing. The
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 133

Channel
inversion layer
Depeletion
region
Gate
Oxide

+++++++++++++++ Poly
+ +
+ +
n+ Source + + n+ Drain
+ +
+ +
+ + + +
+ +

– –

p-substrate

Imaged by gate Imaged by the

source the drain

FIGURE 2.66
Charge sharing between the source/drain depletion regions and the channel depletion region.

depletion regions of the source and the drain are very close to each other.
Through a charge sharing mechanism as in Figure 2.66, this phenomenon can
be explained as in [48]. In case of a short-channel device, a considerable por-
tion of the field lines emanating from the bulk charge terminate in the source
and the drain regions instead of the gate. It is easier for the gate to deplete the
amount of channel charge, lowering the threshold voltage of the device.
To sum up,

• Long-channel MOS transistor: The depletion is only due to the electric

field created by the gate voltage.
• Small-geometry transistor: In addition to the previous contribution, the
depletion charge near n+ regions contributes a significant amount of
the depletion charge.

The expression of the threshold voltage in long-channel MOSFET thus

overestimates the depletion charge supported by the gate voltage. Thus the
amount of the gate voltage required to offset the depletion charge reduces.
The estimated threshold voltage value from the threshold voltage expression
of long-channel MOSFET will be larger than the actual value of the short-
channel MOSFET.
134 Technology Computer Aided Design: Simulation for VLSI MOSFET

The deeper depletion region is accompanied by larger surface potential,

making the channel more attractive for electrons. Thus the device can con-
duct more current. This effect may be considered as the reduction of Vth, as
the drain current is the function of (VGS – Vth). Increase in VDS and reduc-
tion of channel length will decrease the effective threshold voltage. In other
words, the bulk depletion charge contributed by the gate is smaller than the
expected charge, controlled solely by the gate, as a significant portion of the
total depletion region charge under the gate is actually due to the source
and the drain depletion junction. As the threshold voltage is a function of
bulk depletion charge induced by the gate, the expression must be modi-
fied to account for this reduction in the bulk depletion charge. The threshold
voltage of the short-channel MOSFET can be expressed as Vth (SC) = Vth – VthO,
where VthO is the change in threshold voltage from the long to the short-
channel MOSFET.
The depletion due to the source and the drain contacts encroaches
substantially underneath the gate, decreasing the additional gate volt-
age required to create the strong inversion compared to the long-channel
case. This is shown in Figure 2.67 where the source and the drain regions
are assumed to be cylindrical with radius xj and the depletion depth of
extent xd.
The amount of charge imaging on the gate electrode is assumed by a
trapezoidal approximation to be

 L + L/ 
Q/B = − qN A xd  (2.143)
 2 

In the long-channel case,

QB = − qN A xd L (2.144)

xj
n+
n+

xd

L´

FIGURE 2.67
Schematic of the channel region of a short-channel MOSFET.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 135

The charge in the shaded regions image is on the gate and not on the con-
tacts. Thus the reduced bulk charge is the source of the reduced threshold
voltage from

QB
VT = 2 Φ F + VFB − (2.145)
COX

Q/B
V /T = 2 Φ F + VFB − (2.146)
COX

QB − Q/B Q  Q/B 
VT = = B  1 − (2.147)
COX COX QB 

Q/B
Now as L/ → L, then QB
◊ 1 (i.e., the long-channel case).

2.33  Hot Electron Effects

The longitudinal electric field in the channel increases from the source to the
drain ends. For abrupt source and drain junctions, the peak field is at the drain-
to-channel junction, and its value depends on VDS and L. When carriers move in
the electric fields that exceed the value of the onset velocity saturation, they con-
tinue to acquire kinetic energy from the electric field, but their velocity is ran-
domized by the excessive collision such that their velocity along the electric field
direction no longer increases but their random kinetic energy does. Depending
on the statistics of scattering, a small fraction of the overall carrier population
acquires a significant energy, and these are called hot carriers. The electric field
heats the normal lattice electrons coming into the pinch-off region [49].
The carriers crossing from the inverted channel pinch-off point to the
drain travel at their maximum saturated speed, and so gain their maximum
kinetic energy in saturation. These carriers having high energy are called hot
carriers. They travel from the source to the drain along the channel gaining
kinetic energy at the expense of electrostatic potential energy in the pinch-
off region, and they behave as a hot electron. Some of them obtain energy
to create impact ionization with silicon lattice atoms, as a result of which
new electrons and holes are created: this effect is referred to as weak ava-
lanche. The new electrons created join the other channel electrons and move
toward the drain. Some hot carriers in small numbers can acquire enough
energy so as to surmount the Si-SiO2 interface barrier and thus move into
the gate oxide as in Figure 2.68. Most of the injected carriers are collected by
the gate electrode resulting in the gate current IG, reducing the input imped-
ance. Because the barrier potential for this process is very high, the number
of hot carriers injected into the gate will be much smaller compared to those
136 Technology Computer Aided Design: Simulation for VLSI MOSFET

Injection over
barrier

Fowler-Nordheim
Hot carriers tunneling

EC Direct
tunneling
EV

Silicon Oxide Gate

FIGURE 2.68
Three types of carrier injection into the gate causing hot carrier effects.

causing impact ionization. Therefore, the gate current will be smaller than the
substrate current by a few orders of magnitude. It must be noted that carriers
can also enter the gate oxide by tunneling. For direct tunneling, the oxide
has to be very thin and the field is high. Even for the thicker oxide, the carrier
with energy less than the energy barrier can tunnel through the barrier. This
effect is called Fowler-Nordheim tunneling.
A small fraction of the high energy carriers create damage at the silicon-
oxide interface which manifests itself as an increase in the interface state
density, and yet another fraction becomes trapped in the oxide. The traps
in the oxide significantly affect reliability. The accumulation of such traps
behaves as a fixed oxide charge, causing a change in the threshold voltage of
the device, and this affects the gate’s control, giving rise to oxide breakdown.
A lightly doped drain (LDD) structure can reduce this hot-carrier effect. This
is because, in such a case, part of the depletion region would be inside the
drain, absorbing some of the potential that otherwise would exist in the
pinch-off region, and lowering the maximal electric field.

2.34  Avalanche Breakdown and Parasitic Bipolar Action

An undesirable short-channel effect that occurs due to the high velocity
of electrons in the presence of a large longitudinal electric field generates
electron-hole pairs by impact ionization of the silicon atoms as in [50]. The
presence of high longitudinal fields in a short-channel MOSFET can acceler-
ate electrons that can ionize silicon atoms by impacting against them.
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 137

When the electric field in the channel is increased, due to high energetic
hot electrons, avalanche breakdown occurs in the channel at the drain end. This
increases the flow of current. The electrons are attracted by the drain, while
the holes enter the substrate to form part of the parasitic substrate current.
There is also parasitic bipolar action taking place. The region between the
source and the drain can act like the base of an n-p-n transistor, with the
source playing the role of the emitter and the drain that of the collector. Holes
generated by the avalanche breakdown move from the drain to the substrate
underneath the inversion layer. The hole current forward biases the source-
body p-n diode. Also if the holes coming from avalanche are collected by
the source and the corresponding hole current creates a voltage drop in the
substrate material of the order of 0.6V, the normally reverse biased substrate
source p-n junction will conduct appreciably. The electrons are also injected
as the minority carriers into the p-type substrate underneath the inversion
layer from the forward biased junction, similar to the injection of electrons
from the emitter to the base. They can obtain enough energy as they move
toward the drain to create new e-h pairs. These electrons arrive at the drain
and create further electron-hole pairs through the avalanche multiplication.
The positive feedback between the avalanche breakdown and the parasitic
bipolar action results in breakdown at lower drain voltage. The process is
shown in Figure 2.69, and the steps are as follows:
Process 1: Hot carriers having sufficient energy to overcome the oxide-
Si barrier are injected from the channel to the gate oxide (process 1)
causing the gate current to flow. Trapping of some of this charge can
change Vth permanently.
Process 2: Avalanching can take place producing electron-hole pairs.
Process 3: The holes produced by avalanching are collected by the sub-
strate contact causing parasitic substrate current Isub.
Process 4: Voltage drop due to Isub can cause the substrate-source junc-
tion to be forward biased.
Process 5: The forward biased substrate-source junction causes the
minority electrons to be injected from the source into the substrate.
Some of them are collected by the reverse biased drain and cause a
parasitic bipolar action.

2.35  DIBL (Drain-Induced Barrier Lowering)

The population of channel carriers in the long channel devices is controlled by
the gate voltage that creates the vertical electric field, whereas the horizontal
field controls the current between the drain and the source. The current flow
in the channel depends on creating and maintaining an inversion layer on
138 Technology Computer Aided Design: Simulation for VLSI MOSFET

VG

VD

Oxide (1)
Channel current
–
n+ – n+
+

–
(2)
(5) (3) Holes Impact
Additional electron swept into ionization
injection into the base
drain +
Isub RB (4) Potential drop due to hole current
make substrate-to-source junction
–
forward biased

FIGURE 2.69
Impact ionization and parasitic bipolar action in a short-channel MOSFET.

the surface. If the gate voltage is not sufficient to invert the surface (VG < Vth),
the carriers (electrons) in the channel face a potential barrier that blocks the
flow. Increasing the gate voltage reduces this potential barrier and eventually
allows the flow of carriers under the influence of the channel electric field.
In long-channel devices, the horizontal and the vertical electric fields can be
treated as having separate effects on the device characteristics. When the device
is scaled down, the drain region moves closer to the source, and its electric field
influences the whole channel. The drain-induced electric field also plays a role
in attracting carriers to the channel without the control from the gate terminal.
This effect is known as drain-induced barrier lowering (DIBL) because the drain
lowers the potential barrier for the source carriers to form the channel. The
threshold voltage lowers to feel the impact of this effect. DIBL attracts carriers
with a loss in the gate control resulting in increased off-state leakage current.

2.36  Velocity Saturation in MOSFET

Velocity saturation due to the mobility reduction is important in the sub-
micron devices. In the derivation of I-V relationship of the long-channel
MOSFET, we explicitly assume that the mobility is a constant. However, this
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 139

assumption must be modified for two reasons. Two effects are combined in
the transistors to account for this mobility; reduction due to the horizontal
electric field, and the mobility reduction due to the vertical electric field.
The performance of short-channeled devices is also affected by the velocity
saturation, which reduces the transconductance in the saturation mode. At low
electric field, the electron drift velocity Vd in the channel varies linearly with
the electric field intensity [51]. However, as the electric field increases above
104 V/cm, the drift velocity tends to increase more slowly, and approaches a
saturation value of Vd(sat) = 107 cm/s around the electric field = 105 v/cm at 300 K.
For a MOS device, if VDS = 5 V and the channel length L = 1 µm, the aver-
age electric field is 5 * 104 V/cm, and thus velocity saturation is more likely to
occur in the short-channel devices for length L < 1 µm because drift velocity
saturates around electric field = 105 V/cm.
Due to very high longitudinal electric field (drain bias) in the pinch-off region
in long-channel devices, the carrier velocity saturates. This is more prominent
in the short-channel devices as the corresponding horizontal electric field is
generally even larger than long-channel MOSFET. For an ideal long-channel
I-V relationship, the current saturation occurs when the inversion charge den-
sity becomes zero at the drain terminal or when VDS = VDS(sat) = VGS – Vth.
However, velocity saturation can change this condition. Velocity satura-
tion will yield an ID(sat) value smaller than that predicted in an ideal relation,
and it will yield a smaller VDS (sat) value than predicted. In a short-channel
MOSFET before attaining pinch off, carrier drift velocity saturates and thus
the current saturation occurs at a low value of VDS. ID will be linear with
VGS. The short-channel devices therefore experience an extended saturation
region and tend to operate more often in saturation conditions than their
long-channel counterparts, as shown in Figure 2.70.

IDS
In mA
Long channel
MOSFET

Short channel
MOSFET

0 VDSsat VGS – Vth VDS

In volts

FIGURE 2.70
Current saturates in short-channel devices for small VDS.
140 Technology Computer Aided Design: Simulation for VLSI MOSFET

2.37  Mobility Degradation

There are two reasons for mobility reduction in MOSFET:

1. Due to the vertical electric field

2. Due to the horizontal electric field

2.37.1  Vertical Electric Field Mobility Degradation

A vertical electric field exists in MOSFET due to the applied gate voltage,
which creates the conduction channel. When carriers move within the chan-
nel under the effect of the horizontal electric field, they feel the effect of the
gate-induced vertical electric field, pushing carriers toward the gate oxide.
This causes the carriers to collide with the oxide-channel interface. The
oxide-channel interface is rough and imperfect, and carriers thus lose mobil-
ity. This effect is called surface scattering. It reduces mobility. If there is a posi-
tive fixed oxide charge near the oxide-semiconductor interface, the mobility
will be further reduced due to additional coulomb attraction.
The effective inversion charge mobility is a strong function of temperature
because of lattice scattering. As temperature decreases, mobility increases. The
mobility used in the MOSFET model is not the mobility of electrons in the
silicon crystal, called bulk mobility. Rather, it is a surface mobility. The surface
mobility is lower than the bulk mobility because of increased scattering of
the electrons at the silicon-oxide interface, as shown in Figure 2.71. The sur-
face mobility depends on how much the electrons interact with the interface
and, therefore, on the vertical electric field that “pushes” the electrons against
the interface. The higher the electric field, the lower is the surface mobility.

2.37.2  Surface Scattering

The mobility is reduced in a small dimension compared to a larger dimen-
sion due to an increase in the average vertical field in the inversion layer. As
the channel length becomes smaller due to the lateral extension of the deple-
tion layer into the channel region, the longitudinal electric field component
Ey increases, and the surface mobility becomes field dependent. Because the
carrier transport in a MOSFET is confined within the narrow inversion layer,
and the surface scattering (the collisions suffered by the electrons that are
accelerated toward the interface by Ey) causes reduction of the mobility, the
electrons move with great difficulty parallel to the interface, so that the aver-
age surface mobility, even for small values of Ey, is about half as much as that
of the bulk mobility. The mobility in the inversion layer is distinctly lower
than in bulk material. This is due to the fact that the electron wave-function
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics 141

+VGS
VDS

Vertical E-Field

n+ n+

P-substrate

Inversion charge layer

Induced space charge

Inversion layer
Oxide

Drain
Space charge

Carrier Surface Scattering

FIGURE 2.71
Vertical electric field in a short-channel MOSFET and due to that, surface scattering is seen.

extends into the oxide and the carrier mobility is lowered due to the lower
mobility in the oxide.

2.37.3  Horizontal Electric Field Mobility Degradation

The mobility degradation due to the lateral field Ey (drain voltage) plays a
more significant effect on the device current equations than does the normal
field Ex (gate voltage). This is because an increase in the lateral field even-
tually causes velocity saturation of the carriers. For a given normal field,
the velocity v of a carrier is proportional to Ey, at low lateral fields, and the
proportionality constant is the surface mobility µs. However, as Ey increases,
the carrier velocity tends to saturate. Carriers in the short-channel devices
reach the velocity saturation at lower values of VDS than for the long-channel
142 Technology Computer Aided Design: Simulation for VLSI MOSFET

devices. This effect is due to the channel length reduction that implies higher
horizontal electric fields for equivalent drain to-source voltages than the
long-channel MOSFETs. The horizontal electric field within the channel is
due to the voltage applied to the drain terminal. Due to this horizontal elec-
tric field, horizontal mobility also decreases.

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3
Review of Numerical Methods for
Technology Computer Aided Design (TCAD)

Kalyan Koley

CONTENTS
3.1 Introduction................................................................................................. 145
3.2 Numerical Solution Methods.................................................................... 146
3.3 Non-Linear Iteration................................................................................... 146
3.3.1 Newton Iteration............................................................................. 146
3.3.2 Gummel Iteration............................................................................ 147
3.3.3 Block Iteration.................................................................................. 148
3.3.4 Combining the Iteration Methods................................................ 148
3.4 Convergence Criteria for Non-Linear Iterations.................................... 149
3.5 Initial Guess Requirement......................................................................... 149
3.6 Numerical Method Implementation........................................................ 150
3.7 Basic Drift Diffusion Calculations........................................................... 151
3.8 Drift Diffusion Calculations with Lattice Heating................................ 152
3.9 Energy Balance Calculations..................................................................... 152
3.10 Energy Balance Calculations with Lattice Heating............................... 152
3.11 Setting the Number of Carriers................................................................ 153
3.12 Important Parameters of the METHOD Statement................................ 153
3.12.1 Restrictions on the Choice of METHOD..................................... 154
3.12.2 Pisces-II Compatibility................................................................... 154
References.............................................................................................................. 154

3.1 Introduction
In this chapter we discuss the numerical method used in the simulator. In an
iterative method for solving, we start with a guess for the solution (often just
the zero vector) and then successively renew this guess, getting closer to the
solution at each stage. This iteration is usually performed until it converges
to a result and a desired accuracy is achieved. The power of most iterative
methods lies in their ability to achieve this convergence efficiently. However,
two conflicting issues for a particular iterative method are high speed and

145
146 Technology Computer Aided Design: Simulation for VLSI MOSFET

convergence. Say, for example, to achieve a convergence for an equation a

large number of iterations are needed. This will severely affect the speed and
hence the time consumed. Conversely, a high-speed solver may not achieve
a convergence. In the following sections the different iterative techniques
implemented in technology computer aided design (TCAD) to achieve con-
vergence efficiently are described in detail.

3.2  Numerical Solution Methods

For semiconductor devices, different solution methods are used depend-
ing upon the situation. It is also possible to use several different numerical
methods to obtain solutions. And in addition, different combinations of
models for a particular numerical method are also required for solving
equations. There are three different types of solution techniques commonly
used for obtaining solutions for semiconductor devices. These are repre-
sented by (a) de-coupled (GUMMEL), (b) fully coupled (NEWTON), and
(c) BLOCK. The de-coupled technique like the Gummel method solves for
each unknown in an equation while keeping the other variables constant
and repeats the process until a stable solution is achieved [1]. In fully cou-
pled techniques such as the Newton method, the total system of unknowns
are solved together. Finally, in the combined or block method, the solution
is obtained by solving some equations by the fully coupled method, while
others are solved by the de-coupled method. Both techniques mentioned
are broadly classified under the non-linear iteration method where the
method converges to a solution nonlinearly and provides a more accurate
result than its linear counterpart. In the next section these techniques are
discussed in detail.

3.3  Non-Linear Iteration

3.3.1  Newton Iteration
For the solution of nonlinear systems, the scheme developed by Bank and
Rose is applied. This scheme tries to solve the nonlinear system by using
the Newton method: Each iteration of the Newton method solves a lin-
earized version of the entire non-linear algebraic system. The size of the
problem is relatively large, and each iteration takes a relatively long time.
However, the iteration will normally converge quickly (in about three to
eight iterations) so long as the initial guess is sufficiently close to the final
solution. Strategies that use automatic bias step reduction in the event of
Review of Numerical Methods for Technology Computer Aided Design 147

non-convergence loosen the requirement of a good initial guess. Newton’s

method is the default for drift-diffusion calculations in ATLAS. There
are several calculations for which ATLAS requires that Newton’s method
be used. These are DC calculations that involve lumped elements, tran-
sient calculations, curve tracing, and when frequency-domain small-signal
analysis is performed. The Newton-Richardson method is a variant of the
Newton iteration that calculates a new version of the coefficient matrix
only when slowing convergence demonstrates that this is necessary. An
automated Newton-Richardson method is available in ATLAS, and it
improves performance significantly on most problems. The automated
Newton-Richardson method is enabled by specifying the AUTO parameter
of the METHOD statement [2]. If convergence is obtained only after many
Newton iterations, the problem is almost certainly poorly defined. The grid
may be very poor (i.e., it contains many obtuse or high aspect ratio trian-
gles), or a depletion region may have extended into a region defined as an
ohmic contact, or the initial guess may be very poor.

3.3.2  Gummel Iteration

Each iteration of Gummel’s method solves a sequence of relatively small lin-
ear sub-problems. The sub-problems are obtained by linearizing one equa-
tion of the set with respect to its primary solution variable, while holding
other variables at their most recently computed values. Solving this lin-
ear sub-system provides corrections for one solution variable. One step of
Gummel iteration is completed when the procedure has been performed for
each independent variable. Gummel iteration typically converges relatively
slowly, but the method will often tolerate relatively poor initial guesses. The
Gummel algorithm cannot be used with lumped elements or current bound-
ary conditions. Two variants of Gummel’s method can improve its perfor-
mance slightly. These both limit the size of the potential correction that is
applied during each Gummel loop.
The first method, called damping, truncates corrections that exceed a max-
imum allowable magnitude. It is used to overcome numerical ringing in the
calculated potential when bias steps are large (greater than 1 V for room tem-
perature calculations). The maximum allowable magnitude of the potential
correction must be carefully specified: too small a value slows convergence,
while too large a value can lead to overflow. The DVLIMIT parameter of
the METHOD statement is used to specify the maximum allowable magni-
tude of the potential correction. By default, the value of this parameter is 0.1
V. Thus, by default Gummel iterations are damped. To specify undamped
Gummel iterations, the user should specify DVLIMIT to be negative or zero.
The second method limits the number of linearized Poisson solutions per
Gummel iteration, usually to one. This leads to under-relaxation of the poten-
tial update. This “single-Poisson” solution mode extends the usefulness of
148 Technology Computer Aided Design: Simulation for VLSI MOSFET

Gummel’s method to higher currents. It can be useful for performing low

current bipolar simulations, and simulating MOS transistors in the satura-
tion region. It is invoked by specifying the SINGLEPOISSON parameter of
the METHOD statement.

3.3.3  Block Iteration

ATLAS offers several block iteration schemes that are very useful when
lattice heating or energy balance equations are included. Block iterations
involve solving subgroups of equations in various sequences. The subgroups
of equations used in ATLAS have been established as a result of numeri-
cal experiments that established which combinations are most effective in
practice.
In non-isothermal drift-diffusion simulation, specifying the BLOCK
method means that Newton’s method is used to update potential and carrier
concentrations, after which the heat flow equation is solved in a de-coupled
step. When the carrier temperature equations are solved for a constant lat-
tice temperature, the BLOCK iteration algorithm uses Newton’s method to
update potential and concentrations [2]. The carrier temperature equation is
solved simultaneously with the appropriate continuity equation to update
the carrier temperature and carrier concentration.
When both the heat flow equation and the carrier temperature equations
are included, the BLOCK scheme proceeds as described previously for the
carrier temperature case, and then performs one de-coupled solution for lat-
tice temperature as a third step of each iteration.

3.3.4  Combining the Iteration Methods

It is possible to start with the GUMMEL scheme and then switch to BLOCK
or NEWTON if convergence is not achieved within a certain number of itera-
tions. One circumstance where this can be very helpful is that the Gummel
iteration can refine an initial guess to a point from which a Newton iteration
can converge [3].
The number of initial GUMMEL iterations is limited by GUM.INIT. It may
also be desirable to use BLOCK iteration and then switch to NEWTON if con-
vergence is not achieved. This is the recommended strategy for calculations
that include lattice heating or energy balance. The number of initial BLOCK
iterations is limited by NBLOCKIT.
Any combination of the parameters GUMMEL, BLOCK, and NEWTON
may be specified on the METHOD statement. ATLAS will start with
GUMMEL if it is specified. If convergence is not achieved within the
specified number of iterations, it will then switch to BLOCK if BLOCK is
specified; if convergence is still not achieved the program will then switch
to NEWTON.
Review of Numerical Methods for Technology Computer Aided Design 149

3.4  Convergence Criteria for Non-Linear Iterations

After a few non-linear iterations, the errors will generally decrease at a char-
acteristic rate as the iteration proceeds. Non-linear iteration techniques typi-
cally converge at a rate that is either linear or quadratic. The error decreases
linearly when Gummel iteration is used (i.e., it is reduced by about the same
factor at each iteration). For Newton iteration the convergence is quadratic
(i.e., small errors less than one are approximately squared at each iteration).
The non-linear iteration is terminated when the errors are acceptably small.
The conditions required for terminations are called convergence criteria.
Much effort has gone into developing reliable default convergence criteria
for ATLAS [3]. The default parameters work well for nearly all situations, and
most users will never need to change them.

3.5  Initial Guess Requirement

Non-linear iteration starts from an initial guess. The quality of the initial
guess (i.e., how close it is to the final solution) affects how quickly the solu-
tion is obtained, and whether convergence is achieved. Users of ATLAS are
not required to specify an initial guess strategy. If no strategy is defined,
ATLAS follows certain rules that implement a sensible, although not neces-
sarily optimum, strategy. There is some interaction between the choice of
non-linear iteration scheme and the initial guess strategy. De-coupled itera-
tion usually converges linearly, although perhaps slowly, even from a rela-
tively poor initial guess. Newton iteration converges much faster for a good
initial guess but fails to converge if started from a poor initial guess. One
simple initial guess strategy is to use the most recent solution as the initial
guess. Of course, there is no previous solution for the first calculation in a
series of bias points. In this case, an initial solution is obtained for equilib-
rium conditions [3]. There is no need to solve the current continuity equa-
tions at equilibrium, and a solution of Poisson’s equation is quickly obtained.
It is also possible to modify the initial guess in a way that makes some allow-
ance for the new bias conditions. Typical strategies include

• Using two previous solutions and interpolation to project a new

solution at each mesh point.
• Solving a form of current continuity equation with carrier concen-
trations held constant. This strategy yields an improved estimate of
new potential distribution.
• Modifying the majority carrier quasi-Fermi levels by the same
amount as the bias changes.
150 Technology Computer Aided Design: Simulation for VLSI MOSFET

• Parameters on the SOLVE statement can be used to specify an initial

guess strategy. Five initial guess strategies are available.
• INITIAL starts from space charge neutrality throughout the device.
This choice is normally used to calculate a solution with zero
applied bias.
• PREVIOUS uses the currently loaded solution as the initial guess
at the next bias point. The solution is modified by setting a different
applied bias at the contacts.
• PROJECTION takes two previous solutions whose bias conditions
differ at one contact and extrapolates a solution for a new applied
bias at that contact. This method is often used when performing a
voltage ramp.
• LOCAL sets the applied bias to the specified values and changes the
majority carrier quasi-Fermi levels in heavily doped regions to be
equal to the bias applied to that region. This choice is effective with
Gummel iteration, particularly in reverse bias. It is less effective with
Newton iteration.
• MLOCAL starts from the currently loaded solution and solves
a form of the total current continuity equation that provides an
improved estimate of the new potential distribution. All other
quantities remain unchanged. MLOCAL is more effective than
LOCAL because it provides a smooth potential distribution in
the vicinity of p-n junctions. It is usually more effective than
PREVIOUS because MLOCAL provides a better estimate of
potential. This is especially true for highly doped contact regions
and resistor-like structures.

When a re-grid is performed, the solution is interpolated from the original

grid onto a finer grid. This provides an initial guess that can be used to start
the solution of the same bias point on the new grid.
Although the initial guess is an interpolation of an exact solution, this type
of guess does not provide particularly fast convergence.

3.6  Numerical Method Implementation

The Gummel method is effective where the system of equations is weakly
coupled, with only linear convergence. The Newton method is effective where
the system of equations is strongly coupled and has quadratic convergence.
However, it may so happen that in a system of equations some of the quanti-
ties are weakly coupled while others are strongly coupled, or we can say a
Review of Numerical Methods for Technology Computer Aided Design 151

mixed coupled system. In such cases the Newton method consumes extra
time solving for quantities that are essentially constant or weakly coupled. In
accession to that, the Newton method requires a more accurate initial guess
for the problem to obtain convergence. In order to compensate for the issues
associated with the Newton method, it is better to use the block method
to achieve convergence efficiently. The block method provides a compara-
tively faster simulation time in the mixed case over the Newton method [4].
Because Gummel can often furnish better initial guesses to problems, it is
more appropriate to start a solution with a few Gummel iterations in order to
generate a better initial guess and then switch to Newton to attain the final
solution. The different solution methods are carried out by including the fol-
lowing statement for simulation:

METHOD GUMMEL BLOCK NEWTON

The exact meaning of the statement and the combination of the solution
method depend upon the particular models to which it is applied. In the fol-
lowing sections the insights of this statement with respect to different mod-
els are described in detail.

3.7  Basic Drift Diffusion Calculations

The isothermal drift diffusion model requires the solution of three
equations for potential, electron concentration, and hole concentration.
Specifying GUMMEL or NEWTON alone on METHOD statement will pro-
duce simple Gummel or Newton solutions of the equations as described
earlier. For almost all cases the Newton method is preferred because of its
quadratic convergence to produce more accurate solution; hence, it is set
as the default method. However, there are also alternative methods such
as specifying:

METHOD GUMMEL NEWTON

This will cause the solver to initially start with Gummel iterations and
then switch to Newton, if convergence is not achieved. This method is very
robust, even though it consumes more time to obtain solutions for any device.
However, this method is highly recommended for all simulations with float-
ing regions such as silcon on insulator (SOI) transistors. A floating region is
defined as an area of doping that is separated from all electrodes by a p-n
junction. It may also be noted that BLOCK is equivalent to NEWTON for all
isothermal drift-diffusion simulations.
152 Technology Computer Aided Design: Simulation for VLSI MOSFET

3.8  Drift Diffusion Calculations with Lattice Heating

When the lattice heating model is added to drift diffusion, an extra equation
is added. The BLOCK algorithm solves the three drift diffusion equations as a
Newton solution and follows this with a de-coupled solution of the heat flow
equation. The NEWTON algorithm solves all four equations in a coupled man-
ner. NEWTON is preferred once the temperature is high; however, BLOCK is
quicker for low temperature gradients. Typically the combination used is

METHOD BLOCK NEWTON

3.9  Energy Balance Calculations

The energy balance model requires the solution of up to five coupled equa-
tions. GUMMEL and NEWTON have the same meanings as with the
drift diffusion model (i.e., GUMMEL specifies a de-coupled solution, and
NEWTON specifies a fully coupled solution). However, BLOCK performs a
coupled solution of potential, carrier continuity equations followed by a cou-
pled solution of carrier energy balance, and carrier continuity equations. It is
possible to switch from BLOCK to NEWTON by specifying multiple solution
methods on the same line. For example,

METHOD BLOCK NEWTON

This will begin with BLOCK iterations and then switch to NEWTON if con-
vergence is still not achieved. This is the most robust approach for many
energy balance applications. The points at which the algorithms switch is
predetermined but can also be changed on the METHOD statement. The
default values set by TCAD tool Silvaco work well for most circumstances.

3.10  Energy Balance Calculations with Lattice Heating

When non-isothermal solutions are performed in conjunction with
energy balance models, a system of up to six equations must be solved.
GUMMEL or NEWTON solve the equations iteratively or fully coupled,
respectively. BLOCK initially performs the same function as with energy
balance calculations, and then solves the lattice heating equation in a de-
coupled manner.
Review of Numerical Methods for Technology Computer Aided Design 153

3.11  Setting the Number of Carriers

ATLAS can solve both electron and hole continuity equations, or only for one or
none. This choice can be made using the parameter CARRIERS. For example,

METHOD CARRIERS = 2

This specifies that a solution for both carriers is required. This is the default.
With one carrier the parameter ELEC or HOLE is needed. For example, for
hole solutions only,

METHOD CARRIERS = 1 HOLE

To select a solution for potential only, specify

METHOD CARRIERS = 0

3.12  Important Parameters of the METHOD Statement

It is possible to alter all of the parameters relevant to the numerical solution
process. This is not recommended unless you have expert knowledge of the
numerical algorithms [5]. All of these parameters have been assigned opti-
mal values for most solution conditions. It is beyond the scope of this chapter
to give more details.
Two parameters, however, are worth noting at this stage:

1. CLIMIT or CLIM.DD specifies minimal values of concentrations

to be resolved by the solver. Sometimes it is necessary to reduce
this value to aid solutions of breakdown characteristics. A value of
CLIMIT = 1e-4 is recommended for all simulations of breakdown
where the pre-breakdown current is small. CLIM.DD is equivalent
to CLIMIT but uses the more convenient units of cm−3 for the critical
concentration.
2. DVMAX controls the maximum update of potential per iteration
of Newton’s method. The default corresponds to 1 V. For power
devices requiring large voltages, an increased value of DVMAX
might be needed. DVMAX = 1e8 can improve the speed of high-
voltage bias ramps.
154 Technology Computer Aided Design: Simulation for VLSI MOSFET

3. CLIM.EB controls the cut-off carrier concentration below which the

program will not consider the error in the carrier temperature. This
is applied in energy balance simulations to avoid excessive calcula-
tions of the carrier temperature at locations in the structure where
the carrier concentration is low. However, if this parameter is set too
high so that the carrier temperature errors for significant carrier con-
centrations are being ignored, unpredictable and mostly incorrect
results will be seen.

3.12.1  Restrictions on the Choice of METHOD

The following cases all require METHOD NEWTON CARRIERS = 2 to be
set for isothermal drift-diffusion simulations. Both BLOCK and NEWTON
are permitted for lattice heat and energy balance:

• Current boundary conditions

• Distributed or lumped external elements
• AC analysis
• Impact ionization

3.12.2  Pisces-II Compatibility

Previous releases of ATLAS (2.0.0.R) and other PISCES-II based programs
use the SYMBOLIC command to define the solution method and the num-
ber of carriers to be included in the solution. In the current version of ATLAS,
the solution method is specified completely on the METHOD statement. The
COMB parameter that was available in earlier ATLAS versions is no longer
required, as it is replaced by either the BLOCK method or the combination of
GUMM EL and NEWTON.

References
1. Sentaurus TCAD Manuals, Synopsys Inc., Mountain View, CA.
2. Taurus Medici Manuals, Synopsys Inc., Mountain View, CA.
3. ATLAS User’s Manual, Silvaco Int., Santa Clara, CA, May 26, 2006
4. M.K. Jain, S.R.K. Iyengar, and R.K. Jain, Numerical Methods for Scientific and
Engineering Computations, New Age International, New Delhi, India, 2004.
5. M.K. Jain, Numerical Solution of Differential Equations, 2nd ed., New Age
International, New Delhi, India, 2008.
4
Device Simulation Using ISE-TCAD

N. Mohankumar

CONTENTS
4.1 Introduction................................................................................................. 155
4.2 Design Flow................................................................................................. 156
4.3 Sentaurus Structure Editor........................................................................ 156
4.3.1 Design of a 2D Bulk Metal-Oxide-Semiconductor
Field-Effect Transistor (MOSFET) of Channel Length 100 nm.... 158
4.3.2 Meshing............................................................................................ 168
4.4 Mesh.............................................................................................................. 169
4.4.1 Design Continuation...................................................................... 170
4.5 Sentaurus Device........................................................................................ 170
4.5.1 Input-Output Files of the Tool...................................................... 171
4.5.2 Physical Models............................................................................... 173
4.5.2.1 Transport Equations........................................................ 174
4.5.2.2 Poisson Equation and Continuity Equations............... 174
4.5.2.3 Drift-Diffusion Model..................................................... 174
4.5.2.4 Quantization Models....................................................... 175
4.5.2.5 Mobility Models............................................................... 177
4.5.3 Design Continuation...................................................................... 180
4.6 Tecplot.......................................................................................................... 182
4.6.1 Input Files........................................................................................ 182
4.7 Inspect.......................................................................................................... 183
4.8 Parameterized Scripting............................................................................ 183
4.9 Sentaurus Workbench................................................................................ 185
4.10 Summary...................................................................................................... 186
References.............................................................................................................. 186

4.1 Introduction
Technology computer aided design (TCAD) is a design technique that
involves computer simulation procedures to develop and characterize semi-
conductor processing technologies and devices. The two major components
of a TCAD design process are process simulations and device simulations.

155
156 Technology Computer Aided Design: Simulation for VLSI MOSFET

Current major suppliers of TCAD tools include Synopsys, Silvaco, and

Crosslight. Synopsys provides both process and device simulation tools.
It supports a broad range of applications such as complementary metal-
oxide-semiconductor (CMOS), power, memory, solar cells, etc. In addition,
Synopsys provides tools for interconnect modeling and parasitic extraction
procedure which are required for optimizing the performance of an inte-
grated circuit chip.
In this chapter, we discuss techniques for device simulation using the
Synopsys tool suite. The tool suite includes tools for constructing device
structures, meshing, simulation, visualization of electrical characteristics,
plotting of various curves, and extraction of performance parameters. The
working of each tool is described with the help of examples. The principles
of operations involved are also discussed. The details of each tool are not
provided, but readers are referred to corresponding user guides.

4.2  Design Flow

A typical design flow consists of either the creation of a device structure
by a process simulation (Sentaurus Process or Taurus TSUPREME-4) tool or
through computer aided design (CAD) operations and process emulation
steps (using tools like Sentaurus Structure Editor). The constructed device is
meshed intelligently using tools like Sentaurus Mesh/Noffset 3D. Sentaurus
Device is used to simulate the electrical characteristics of the device. It simu-
lates numerically the electrical behavior of a single semiconductor device
in isolation or several physical devices combined in a circuit. Terminal cur-
rents, voltages, and charges are computed based on a set of physical device
equations that describes the carrier distribution and the conduction mecha-
nisms. Finally, Tecplot SV is used to visualize the output from the simulation
in 2D and 3D, and Inspect tool is used to plot the electrical characteristics.
The design flow is shown in Figure 4.1.

4.3  Sentaurus Structure Editor

Sentaurus Structure Editor is a device editor and process emulator based on
CAD technology, used for constructing a semiconductor device. As shown
in Figure  4.2, it has three distinct operational nodes: 2D structure editing,
3D structure editing, and 3D process emulation. Using Sentaurus Structure
Editor, device structures are constructed or edited interactively using a
graphical user interface (GUI) facility. Alternatively, devices can be generated
Device Simulation Using ISE-TCAD 157

Device,
Geometry
and
Technology
Parameters

Device Creation by
Sentaurus Structure *.sat file (model geometry in ACIS format)
Editor (2D/3D generates *.scm file (script contains various parameter settings)
Structure Editing) or *.bnd or *.tdr file (boundary file containing device structure)
3D Process *.cmd file (mesh command file containing doping information)
Emulation

takes the *.bnd or *.Idr file and *.cmd files as input

Grid Generation by *_msh.dat (contains the doping information)

Meshing Engine generates *_msh.grd (contains the mesh geometry information)
(Sentaurus Mesh/ *_msh.log (used as log file)
Noffset3D/Mesh)

takes *_des.cmd, *_msh.dat and *_msg.grd as input

*_des.dat (contains final spatial solution for all the

variables on the structure mesh)
Device Simulation generates *_des.plt (contains electrical output data like
by Sentaurus currents, voltages, charges at electrodes)
Device *_des.log (protocol file that is generated
whenever Sentaurus Device is run)

takes *_msh.dat and *_msg.grd files as input

2D/3D Scientific
Visualization and
Plotting of
Simulated Data by
Tecplot_SV

Curve Display
and analysis by
Inspect

FIGURE 4.1
Design flow of device simulation process using ISE-TCAD, Synopsys.

in batch mode using Scheme scripting language. When a GUI action is per-
formed, Sentaurus Structure Editor prints the corresponding Scheme com-
mand in the command-line window. From the GUI, 2D and 3D device models
are created geometrically using 2D or 3D primitives such as rectangles,
polygons, cuboids, etc. In the process emulation mode (Procem), Sentaurus
Structure Editor translates processing steps such as etching and deposition,
158 Technology Computer Aided Design: Simulation for VLSI MOSFET

Sentaurus
Structure
Editor

2D Structure 3D Structure 3D Process

Editing Editing Emulation

FIGURE 4.2
Operational modes of Structure Editor.

patterning, fill, and polish into geometric operations. Procem supports vari-
ous options such as isotropic or anisotropic etching and deposition, round-
ing, and blending. The working of the Structure Editor is explained with the
help of a design example, which is presented in the next sub-section.

4.3.1 Design of a 2D Bulk Metal-Oxide-Semiconductor Field-Effect

Transistor (MOSFET) of Channel Length 100 nm
The 2D metal-oxide-semiconductor (MOS) structure that we attempt
to create in Sentaurus Device Editor (SDE) is shown in Figure  4.3. The
step-by-step design process using commands is illustrated pictorially in
sequence in Figures 4.4 to 4.12.
Here we illustrate the steps required to create a rectangle that will be used
as bulk silicon material. This involves the creation of a rectangle whose diag-
onally opposite corner coordinates are required to be specified, and com-
mands are as follows. SDE will consider rectangular material as “Silicon”
and this will be named “region_1”. As this is a 2D MOS Device, the Z coor-
dinate is considered to be 0.

Gate

Oxide
n+ n+
Source Drain

p
Substrate x

FIGURE 4.3
Schematic of 2D MOS structure. Positive X and Y axes are right-hand side and downward
direction, respectively. For 2D MOS device, Z coordinate is always considered to be 0.
Device Simulation Using ISE-TCAD 159

FIGURE 4.4
Schematic of bulk silicon creation in SCE by drawing a rectangle using a command whose
corner coordinates are (–0.1 0.0 0.0) and (0.1 0.2 0.0).

To start Sentaurus Structure Editor, on the command line, enter:

sde
(sdegeo:create-rectangle
(position -0.1 0.0 0.0) (position 0.1 0.2 0.0)
“Silicon” “region_1”)

(sdegeo:create-rectangle
(position -0.05 -0.002 0.0) (position 0.05 0 0.0)
“Oxide” “region_2”)

FIGURE 4.5
The creation of oxide on the bulk silicon by using sequential command.
160 Technology Computer Aided Design: Simulation for VLSI MOSFET

FIGURE 4.6
Molybdenum gate on oxide material. This is the actual MOS structure. Rectangular molybde-
num material corner coordinates are (–0.05, –0.002, 0.0) and (0.05, –0.08, 0.0).

One needs to run the sequential command to get the entire structure [1–4].
Sequential command will now create another rectangle on the bulk silicon
material which will be used as oxide or gate oxide. The material has been
selected by command “Oxide” whose diagonally opposite corner coordinates
are (–0.05 –0.002 0.0) and (0.05 0 0.0), and this oxide region is named “region_2”.

(sdegeo:create-rectangle
(position -0.05 -0.002 0.0) (position 0.05 -0.08 0.0)
“Molybdenum” “region_3”)
(sdegeo:define-contact-set “gate” 4 (color:rgb 1 0 0) “##”)
(sdegeo:set-current-contact-set “gate”)

FIGURE 4.7
MOS structure with gate contact on top.
Device Simulation Using ISE-TCAD 161

FIGURE 4.8
Body contact in which contact edge point coordinate (0.0 0.2 0) has been selected by the
program.

(sdegeo:define-2d-contact (list (car (find-edge-id (position

0.0 -0.08 0)))) “gate”);gate contact position and contact name

For the external connection to the 2D MOS device, a 2D gate contact has
to be defined. Here contact is defined at the gate edge with proper coordi-
nate point. Though the coordinate can be anywhere at the gate edge, for this
device the middle point of the gate edge has been selected with coordinates
(0.0 -0.08 0) and contact name “gate”.
(sdegeo:define-contact-set “body” 4 (color:rgb 1 0 0) “##”)
(sdegeo:set-current-contact-set “body”)

FIGURE 4.9
Source/drain 2D contact at position (–0.075 0 0) “source”.
162 Technology Computer Aided Design: Simulation for VLSI MOSFET

FIGURE 4.10
SDE shows the final MOS structure with all the contacts. Here another source/drain contact
point is created here whose coordinate is (0.075 0 0) and name of “drain.”

(sdegeo:define-2d-contact (list (car (find-edge-id (position

0.0 0.2 0))))”body”)

(sdegeo:define-contact-set “source” 4 (color:rgb 1 0 0) “##”)

(sdegeo:set-current-contact-set “source”)
(sdegeo:define-2d-contact (list (car (find-edge-id (position
-0.075 0 0)))) “source”)

(sdegeo:define-contact-set “drain” 4 (color:rgb 1 0 0) “##”)

(sdegeo:set-current-contact-set “drain”)

FIGURE 4.11
The SDE diagram after refinement window selection, source/drain and bulk material doping.
Device Simulation Using ISE-TCAD 163

FIGURE 4.12
Complete structure of the 2D MOSFET in Sentaurus Editor after proper meshing at different
places.

(sdegeo:define-2d-contact (list (car (find-edge-id (position

0.075 0 0)))) “drain”)

Now the device requires proper doping at a different place to work as a

MOSFET. For that purpose a different place has to be selected for doping.
The techplots showing electrostatic potential and conduction band energy

FIGURE 4.13 (See color insert)

Tecplot_sv showing electrostatic potential across the device at VGS = 2.0 V, VDS = 2.0 V.
164 Technology Computer Aided Design: Simulation for VLSI MOSFET

FIGURE 4.14 (See color insert)

Tecplot_sv showing conduction band energy (eV) across the device at VGS = 2.0 V, VDS = 2.0 V.

FIGURE 4.15
Inspect showing VGS versus ID both in normal and logarithmic plots at VGS = 2.0 V, VDS = 2.0 V.
Device Simulation Using ISE-TCAD 165

Origin
TOX = 3
Gate height = 20
Region 8

Region 9 Region 11 Region 10

Region 4 Region 3 Region 5

xsd = 50 xsd =50
Ysw

xsw = 100 Lg xsw = 100

tSi = 70

Region 6 Region 7
Lg/2 Lg/2
Region 2
tSub = 50

Region 1

FIGURE 4.16
Construction of a proposed parameterized MOSFET.

FIGURE 4.17
Creation of Region 1 shown in Figure 4.16.

FIGURE 4.18
Creation of Region 2 shown in Figure 4.16.

FIGURE 4.19
Creation of Region 3 shown in Figure 4.16.
166 Technology Computer Aided Design: Simulation for VLSI MOSFET

FIGURE 4.20
Creation of Region 4 shown in Figure 4.16.

FIGURE 4.21
Creation of Region 5 shown in Figure 4.16.

FIGURE 4.22
Creation of Region 6 shown in Figure 4.16.

FIGURE 4.23
Creation of Region 7 shown in Figure 4.16.

FIGURE 4.24
Creation of Region 8 shown in Figure 4.16.
Device Simulation Using ISE-TCAD 167

FIGURE 4.25
Creation of Region 9 shown in Figure 4.16.

across the device are shown in Figures 4.13 and 4.14. The characteristic plots
in normal and logarithmic scale are shown in Figure 4.15. The diagram of
a proposed parameterized MOSFET is shown in Figure 4.16. Figures 4.17
to 4.27 show the construction steps of the 11 Regions of the parameterized
MOSFET structure shown in Figure 4.16. The following command [1] will
select a different place as a rectangular window, and doping in that window
is possible according to the requirement and command:
(sdedr:define-constant-profile “ConstantProfileDefinition_1”
“BoronActiveConcentration” 0.4e18)
(sdedr:define-constant-profile-material
“ConstantProfilePlacement_1”
“ConstantProfileDefinition_1” “Silicon”)
Here the profile name is “ConstantProfileDefinition_1” and the dop-
ant is “BoronActiveConcentration” as boron is needed to be implanted
in the bulk material whose doping concentration is 0.4e18 (0.4 × 1018) per cm3
and whose name is mentioned as “BoronActiveConcentration”. This

FIGURE 4.26
Creation of Region 10 shown in Figure 4.16.

FIGURE 4.27
Creation of Region 11 shown in Figure 4.16.
168 Technology Computer Aided Design: Simulation for VLSI MOSFET

“ConstantProfileDefinition_1” will be placed wherever it will find “Silicon”

material [1]. In this way, the entire bulk material will be doped by boron with
a doping concentration of 0.4 × 1018 per cm3.

(sdedr:define-refeval-window “RefEvalWin_1” “Rectangle”

(position -0.1 0 0) (position -0.05 0.03 0))
(sdedr:define-constant-profile “ConstantProfileDefinition_2”
“ArsenicActiveConcentration” 1e+20)
position(sdedr:define-constant-profile-placement
“ConstantProfilePlacement_2” “ConstantProfileDefinition_2”
“RefEvalWin_1” 0 “Replace”)

Now source/drain doping is needed, and for this purpose two rectangular
areas must be selected. For source doping, a rectangular window has been
selected by the command line whose corner coordinates are (–0.1 0 0) and
(–0.05 0.03 0). This is named “RefEvalWin_1” and a doping profile has been
selected “ArsenicActiveConcentration” as Arsenic is required as a dopant
whose doping concentration is 1020 per cm3, and finally this profile definition
name is “ConstantProfileDefinition_2”. Similarly, using the command below,
drain doping has been done. Here the “Replace” command [1] will replace
previous boron doping by new arsenic doping with the mentioned doping
profile.

(sdedr:define-refeval-window “RefEvalWin_2” “Rectangle”

(position 0.05 0 0) (position 0.1 0.03 0)) position
(sdedr:define-constant-profile “ConstantProfileDefinition_3”
“ArsenicActiveConcentration” 1e+20)
(sdedr:define-constant-profile-placement
“ConstantProfilePlacement_3” “ConstantProfileDefinition_3”
“RefEvalWin_2” 0 “Replace”)

4.3.2 Meshing
The input and output files of Sentaurus Structure Editor are:

• Scheme script file (.scm)

This is a user-defined script file that contains scheme script com-

mands describing the steps to be executed by Sentaurus Structure
Editor in creating a device structure. This file can be edited to change
its contents.

• ACIS SAT file (.sat)

This file contains the model geometry in native ACIS format and
cannot be edited directly.
Device Simulation Using ISE-TCAD 169

• DF-ISE boundary file (.bnd)

This is a boundary representation file written in the DF-ISE for-

mat. It can be directly loaded into Sentaurus Structure Editor and
then to mesh engines.

• DF-ISE doping and refinement file (.cmd)

This is a DF-ISE format file containing doping and mesh refine-

ment information that, in conjunction with the corresponding
boundary file, uniquely defines the geometry of the model.

4.4 Mesh
Mesh Generation Tools is a suite of tools that produce finite-element meshes
for use which are required in semiconductor device simulation or pro-
cess simulation. Once the device structure is created, meshing is usually
required before the device can be numerically solved for its electrical pro­
perties. The Mesh Generation Tools are composed of three mesh generation
engines: Sentaurus Mesh, Noffset3D, and Mesh. The choice of which mesh
generator to use in an application depends largely on the geometry of the
device. These mesh generators generate high-quality spatial discretizations
for 1D, 2D, and 3D devices using a variety of mesh generation algorithms
and procedures. Meshing basically involves defining a meshing strategy
where the maximum and minimum sizes of the meshes are defined. These
definitions are then placed in a specific region that may be a material or a
device region or a user-defined refinement/evaluation (Ref/Eval) window.
Ref/Eval windows are areas in which a certain mesh refinement or dop-
ing profile is to be applied. In some cases, the mesher can be instructed to
refine the mesh in areas of steep doping gradients or near interfaces. For
example, in the channel of a MOS transistor, a dense meshing is suitable
near the silicon-oxide interface. The tightness of the grid spacing may be
relaxed toward the bulk. This keeps the problem at a minimum of central
processing unit (CPU) time.
Files in the Mesh Generator tool:

Input files: *.bnd or *.tdr and *.cmd files from SSE

Output Files: *_msh.dat (contains the doping information), *_msh.grd
(contains the mesh geometry information), and *_msh.log (used as
log file)
170 Technology Computer Aided Design: Simulation for VLSI MOSFET

To summarize, after meshing, the device is divided into numbers of criss-

cross points (which depend on the size of the mesh). Every point contains the
following information:

1. Location of the point

2. Material of the point
3. Doping concentration of the point

This information may also be stored in a single *_msh.tdr file instead of

*_msh.grd and *_msh.dat to enable the user to input a single file instead of
two files to the next stage (i.e., Simulation).

4.4.1  Design Continuation

The following commands are used to mesh the generated structure:

(sdedr:define-refeval-window “RefEvalWin_4” “Rectangle”

(position -0.1 -0.08 0) (position 0.1 0.2 0)) ;global meshing

(sdedr:define-refinement-size “RefinementDefinition_1” 0.005

0.005 0 0.005 0.005 0)
(sdedr:define-refinement-placement “RefinementPlacement_1”
“RefinementDefinition_1” “RefEvalWin_4”)

(sdedr:define-refeval-window “RefEvalWin_3” “Rectangle”

(position -0.05 -0.002 0) (position 0.05 0.03 0))

(sdedr:define-refinement-size “RefinementDefinition_2” 0.001

0.001 0 0.001 0.001 0)
(sdedr:define-refinement-placement “RefinementPlacement_2”
“RefinementDefinition_2” “RefEvalWin_3”)

(sde:build-mesh “mesh” “-P -discontinuousData -f -t -d -F tdr “

“crc”);

This last command will generate a file name crc_mesh.tdr which is required
for further simulation of the device.

4.5  Sentaurus Device

Sentaurus Device is a comprehensive device simulator framework for simu-
lating the electrical, thermal, and optical characteristics of silicon-based and
compound semiconductor devices. The device simulation tool simulates the
Device Simulation Using ISE-TCAD 171

characteristics of the devices as a response to external electrical, thermal, or

optical signals and boundary conditions.

4.5.1  Input-Output Files of the Tool

The input command file of Sentaurus Device consists of several command
sections, each of which executes a relatively independent function. The
default extension of this file is _des.cmd. The input command file typically
consists of the following sections:

1. File
2. Electrode
3. Physics
4. Plot
5. Math
6. Solve

The File section describes the various input files and output files. The
essential input file consists of the information regarding the device geo­
metry and field values (_msh.tdr), for example, the doping on the structure.
In addition, an optional parameter file can be specified. The device geometry
information consists of the regions and materials of the device, location of
the contacts, and the mesh points including the location of nodes and ver-
tices. The optional parameter file (.par) consists of the user-defined model
parameters. The Sentaurus Device simulation tool produces several output
files. The Current file contains the electrical output data, such as currents,
voltages, and charges at each of the contacts. The default extension of this file
is _des.plt. In addition, a log file is generated that contains all the informative
texts that the tool has downloaded during a run, including the error mes-
sages. The default extension of this file is _des.log.
The Electrode section consists of the definitions of the various contacts of
the device, together with their initial bias conditions. Any special boundary
condition for a contact can also be defined here. It may be noted with care
that each electrode defined here must match (case sensitive) an existing con-
tact name in the structure file, and only those contacts that are named in the
Electrode section are included in the simulation process.
The Physics section consists of a declaration of the physical models that
are to be used in the simulation procedure. Typically it consists of the carrier
mobility model, the band-gap narrowing model, the carrier generation and
recombination model, etc. With the use of a qualifier in the Physics section,
it can be specified in which material or regions the models are to be acti-
vated. For example, Material = “[material name]”, Region = “[region name]”.
172 Technology Computer Aided Design: Simulation for VLSI MOSFET

In this section, the models are declared on activation only. The model param-
eters, if different from the default, are defined and loaded using the optional
Parameter file specified in the File section. The Physics section typical of a
simple NMOSFET simulation is given here.

Physics {
Mobility (DopingDep HighFieldSat Enormal)
EffectiveIntrinsicDensity(OldSlotboom)
}

The Plot section is used to specify the solution variables that are to be
saved in the Plot file after the simulation process is completed. The solution
of these variables can later be visualized using tools like Tecplot SV.
The Math section is used to control the numeric solver involved in the
simulation process. A typical Math section is shown below which may be
used as a guideline.
Math {
Extrapolate
RelErrControl
NotDamped=50
Iterations=20
}

• Extrapolate: In quasi-stationary bias ramps, the initial guess for a

given step is obtained by extrapolation from the solutions of the pre-
vious two steps (if they exist).
• RelErrControl: Switches error control during iterations from using
internal error parameters to more physically meaningful parameters.
• NotDamped = 50: Specifies the number of Newton iterations over
which the right-hand side (RHS) norm is allowed to increase. With
the default of 1, the error is allowed to increase for one step only. It is
recommended that NotDamped > Iterations be set to allow a simula-
tion to continue despite the RHS-norm increasing.
• Iterations = 20: Specifies the maximum number of Newton iterations
allowed per bias step (Default = 50). If convergence is not achieved
within this number of steps, for a quasi-stationary or transient sim-
ulation, the step size is reduced by the factor decrement and simula-
tion continues.

The Solve section defines a sequence of solutions to be obtained by the

solver. To simulate the Id–Vg characteristic, it is necessary to ramp the gate
bias and obtain solutions at a number of points. By default, the size of the
step between solutions points is determined by Sentaurus Device. As the
Device Simulation Using ISE-TCAD 173

simulation proceeds, output data for each of the electrodes (currents, volt-
ages, and charges) are saved to the current file after each step and therefore
the electrical characteristic is obtained. This can be plotted using Inspect.
The Solve section is shown below.

Solve {
Poisson
Coupled {Poisson Electron}
Quasistationary (Goal {Name=“gate” Voltage=2})
{Coupled {Poisson Electron}}
}

• Poisson: This specifies that the initial solution is of the nonlinear

Poisson equation only. Electrodes have initial electrical bias condi-
tions as defined in the Electrode section.
• Coupled {Poisson Electron}: The second step introduces the continu-
ity equation for electrons, with the initial bias conditions applied.
In this case, the electron current continuity equation is solved fully
coupled to the Poisson equation, taking the solution from the previ-
ous step as the initial guess. The fully coupled or “Newton” method
is fast and converges in most cases.
• Quasistationary (Goal {Name = “gate” Voltage = 2})
• {Coupled {Poisson Electron}}

The Quasistationary statement specifies that quasi-static or steady-state

“equilibrium” solutions are to be obtained. A set of Goals for one or more
electrodes is defined in parentheses. In this case, a sequence of solutions
is obtained for increasing gate bias up to and including the goal of 2 V. A
fully coupled (Newton) method for the self-consistent solution of the Poisson
and electron continuity equations is specified in braces. Each bias step is
solved by taking the solution from the previous step as its initial guess. If
Extrapolate is specified in the Math section, the initial guess for each bias
step is calculated by extrapolation from the previous two solutions.

4.5.2  Physical Models

The Physics section allows a selection of the physical models to be applied in
the device simulation [2]. The physical phenomena that actually occur within
semiconductor devices are very complicated and are generally described
using differential equations (partial and full) of different levels of complex-
ity. The coefficients and the boundary conditions required for solving the
equations depend on the structure of the device, the principle of action,
and the applied bias. Sentaurus Device allows for arbitrary combinations of
transport equations and physical models.
174 Technology Computer Aided Design: Simulation for VLSI MOSFET

4.5.2.1  Transport Equations

Depending on the device required to be simulated and the level of modeling
accuracy required, four different simulation models can be selected:

• Drift-diffusion isothermal simulation: Described by basic semiconduc-

tor equations and is suitable for low-power density devices with
long active regions.
• Thermodynamic: Accounts for self-heating and is suitable for devices
with low thermal exchange, particularly, high-power density devices
with long active regions.
• Hydrodynamic: Accounts for energy transport of the carriers. Suitable
for devices with small active regions.
• Monte Carlo: Allows for full band Monte Carlo device simulation in
the selected window of the device.

4.5.2.2 Poisson Equation and Continuity Equations

The three fundamental equations that dictate the charge transport in semi-
conductor devices are the Poisson equation and the electron and hole conti-
nuity equations. The Poisson equation is given as:

⋅ε = − q( p − n + N D − N A ) − ρtrap (4.1)


where ε is the electrical permittivity, q is the elementary electronic charge, n
and p are the electron and hole densities, N D is the concentration of ionized
donors, N A is the concentration of ionized acceptors, and ρtrap is the charge
density contributed by traps and fixed charges. The keyword for the Poisson
equation is Poisson. The keywords for the electron and hole continuity equa-
tions are electron and hole, respectively. They are written as:
→ ∂n → ∂p
⋅ J n = qRnet + q − ⋅ J p = qRnet + q (4.2)
∂t   ∂t
→
where Rnet is the net
→
electron–hole recombination rate, J n is the electron cur-
rent density, and J p is the hole current density.

4.5.2.3  Drift-Diffusion Model

The drift-diffusion model is widely used for the simulation of carrier transport
in semiconductors and is defined by the Poisson and continuity equations, see
(4.1) and (4.2), where current densities for electrons and holes are given by:
→
J n = − nqµ n Φ n
→ (4.3)
J p = − pqµ p Φ p

Device Simulation Using ISE-TCAD 175

where μn and μp are the electron and hole mobilities, and Φn and Φp are the
electron and hole quasi-Fermi potentials, respectively.
The thermodynamic or non-isothermal model extends the drift-diffusion
model to account for electrothermal effects. It assumes that the charge carriers
are in thermal equilibrium with the lattice. In this model the electron and hole
temperatures are assumed to be equal to the lattice temperature. The ther-
modynamic model is described by (4.1), (4.2), and lattice heat flow equations.
Because the size of power devices is extremely large compared to that of CMOS
devices, the drift-diffusion model including thermodynamic effects is usually
sufficient in terms of accuracy. The drift-diffusion transport model, however,
fails to describe the internal and external characteristics of deep submicron
semiconductor devices. In particular, the drift-diffusion approach cannot
reproduce velocity overshoot and often overestimates the impact ionization
generation rates. The Monte Carlo method for the solution of the Boltzmann
kinetic equation is the most general approach. However, it suffers from high
computational requirements. Hence, it cannot be used for the routine simula-
tion of devices in an industrial setting. The hydrodynamic (or energy balance)
model is a good compromise. In the hydrodynamic transport model, carrier
temperatures are allowed to be different from the lattice temperature.

4.5.2.4  Quantization Models

Some features of current MOSFET devices such as oxide thickness, channel
width, etc., have reached their quantum-mechanical length scales. Therefore,
the wave nature of electrons and holes can no longer be neglected. Quantization
effects in a classical device simulation are included by incorporating potential,
like quantity Λ n in the classical carrier density formula as follows:

 E − EC − Λ n 
n = N C F1/2  F ,n 
 kTn (4.4)

An analogous quantity Λ p is used for holes. Sentaurus Device implements

four quantization models—that is, four different models for Λ n and Λ p .
They differ in accuracy, computational expense, and robustness:

• The van Dort model is a numerically robust, fast, and proven model.
However, it is only suited to bulk MOSFET simulations. The impor-
tant terminal characteristics are well described by this model, but it
does not give the correct density distribution in the channel.
• The 1D Schrödinger equations make up the most accurate quantization
model. It can be used for MOSFET simulation, and quantum well and
ultrathin silicon-on-insulator (SOI) simulation. However, the simula-
tion procedure is slow and often leads to convergence problems that
restrict its use to situations with small current flow. It is used mainly
for the validation and calibration of other quantization models.
176 Technology Computer Aided Design: Simulation for VLSI MOSFET

• The density gradient model is numerically robust but significantly

slower than the van Dort model. It can be applied to MOSFETs,
quantum wells, and SOI structures. It gives reasonable description
of terminal characteristics and charge distribution inside a device.
Compared to the other quantization models, it can describe 2D and
3D quantization effects.
• The modified local-density approximation (MLDA) is a numerically
robust and fast model. It can be used for bulk MOSFET simulations
and thin SOI simulations. Although it sometimes fails to calculate
accurate carrier distribution in the saturation regions because of its
one-dimensional characteristic, it is suitable for three-dimensional
device simulations because of its numeric efficiency.

Due to the wide usage of the density gradient model, we briefly discuss
this below.
The density gradient model for Λ n in (4.4) is given by a partial differen-
tial equation:

γ 2
{ } γ 2 2
1 n
Λn = − 2
ln n + ( ln n)2 = − (4.5)
12 mn 2 6mn n

where γ is a fitting parameter. The density gradient equation for electrons

and holes is activated by the eQuantumPotential and hQuantumPotential
switches in the Physics section. These switches can also be used in region
wise or material wise in the Physics section. In metal regions, the equa-
tions are never solved. Apart from activating the equations in the Physics
section, the equations for the quantum corrections must be solved by using
eQuantumPotential or hQuantumPotential, or both in the Solve section. For
example:

Physics {
eQuantumPotential
}
Plot {
eQuantumPotential
}
Solve {
Coupled {Poisson eQuantumPotential}
Quasistationary (
Do Zero InitialStep=0.01 MaxStep=0.1 MinStep=1e-5
Goal {Name=“gate” Voltage=2}
){
Coupled {Poisson Electron eQuantumPotential}
}
}
Device Simulation Using ISE-TCAD 177

4.5.2.5  Mobility Models

Sentaurus Device provides several options for the description of carrier
mobilities. The various causes of mobility degradation can be individu-
ally modeled. In the simplest case, the mobility is considered to be a func-
tion of the lattice temperature. This is referred to as the constant mobility
model and accounts only for phonon scattering. This should only be used
for undoped materials. In doped semiconductors, scattering of the carriers
by charged impurity ions leads to degradation of the carrier mobility. This
is modeled in Sentaurus Device [4]. In the channel region of a MOSFET,
the high transverse electric field forces carriers to interact strongly with
the semiconductor–insulator interface. Carriers are subjected to scattering
by acoustic surface phonons and surface roughness. This phenomenon of
mobility degradation at interface is also modeled in Sentaurus Device. The
carrier-carrier scattering effect can also be modeled. The carrier-carrier
contribution to overall mobility degradation is combined with mobility
contributions from other degradation models following Matthiessen’s rule.
The Philips unified mobility model unifies the description of majority and
minority carrier bulk mobilities. In addition to describing the temperature
dependence of the mobility, the model takes into account electron–hole
scattering, screening of ionized impurities by charge carriers, and cluster-
ing of impurities. The mobility degradation due to high electric field can
also be modeled in Sentaurus Device.

4.5.2.5.1  Doping-Dependent Mobility Degradation

The models for the mobility degradation due to impurity scattering are acti-
vated by specifying the DopingDependence flag to Mobility:

Physics {Mobility (DopingDependence...)...}

Different models are available and are selected by options to

DopingDependence: Physics {Mobility (DopingDependence ([Masetti |
Arora |UniBo])...)...}
If DopingDependence is specified without options, Sentaurus Device uses
a material-dependent default. The default model used by Sentaurus Device
to simulate doping-dependent mobility in silicon was proposed by Masetti
et al. This is as follows:

 P  µ − µ min 2 µ1
µ dop = µ min 1 exp  − c  + const − (4.6)
 N tot  1 + ( N tot/Cr )α 1 + (Cs/N tot )β

The reference mobilities µ min 1, µ min 2, and µ 1; the reference doping concentra-
tions Pc , Cr Cs ; and the exponents α and β are accessible in the parameter
set DopingDependence. The corresponding values for silicon are given in
Table 4.1.
178 Technology Computer Aided Design: Simulation for VLSI MOSFET

TABLE 4.1
Masetti Model: Default Coefficients
Symbol Parameter Name Electrons Holes Unit
μmin1 Mumin1 52.2 44.9 Cm2/Vs
μmin1 Mumin2 52.2 0 Cm2/Vs
μ1 Mu1 43.4 29.0 Cm2/Vs
pc Pc 0 9.23 × 1016 cm–3
cr Cr 9.68 × 1016 2.23 × 1017 cm–3
cs Cs 3.34 × 1020 6.10 × 1020 cm–3
α Alpha 0.680 0.719 1
β Beta 2.0 2.0 1

4.5.2.5.2  Mobility Degradation at Interfaces

In the channel region of a MOSFET, the high transverse electric field forces
carriers to interact strongly with the semiconductor–insulator interface.
The carriers are thus subjected to scattering by acoustic surface phonons
and surface roughness. The models in this section describe mobility degra-
dation caused by these effects. To select the calculation of field perpendicu-
lar to the semiconductor–insulator interface, specify the Enormal option to
Mobility:

Physics {Mobility (Enormal...)...}

The surface contribution due to acoustic phonon scattering has the form:

B C( N /N )λ
µ ac = + 1/3 tot 0 k (4.7)
Fn Fn (T/300K )

And the contribution attributed to surface roughness scattering is given by:

−1
 Fn/Fref )A* Fn3 
µ sr =  +  (4.8)
 δ η

These surface contributions to the mobility are then combined with the bulk
mobility according to Mathiessen’s rule:

1 1 D D
= + + (4.9)
µ µ b µ ac µ sr

where Fref = 1 V/cm, Fn = Normal electric field, D = exp (–x⁄ lcrit) (where x is
the distance from the interface and lcrit is a fit parameter). In the Lombardi
Device Simulation Using ISE-TCAD 179

model, the exponent in (4.8), A* is equal to 2. According to another study, an

improved fit to measured data is achieved if A* is given by:

α ⊥ (n + p)N refv
A* = A + (4.10)
( N tot + N 1 )v

The respective default parameters that are appropriate for silicon are given
in Table 4.2.

4.5.2.5.3  High-Field Saturation

In high electric fields, the carrier drift velocity is no longer proportional
to the electric field; instead, the velocity saturates to a finite speed vsat. The
high-field saturation models include three sub-models: the actual mobility
model, the velocity saturation model, and the driving force model. With
some restrictions, these models can be freely combined. The actual mobil-
ity model is selected by flags eHighFieldSaturation or hHighFieldSaturation.
The default is the Canali model whose parameter values for Silicon are given
in Table 4.3. The Canali model originates from the Caughey–Thomas for-
mula but has temperature-dependent parameters, which were fitted up to
430 K by Canali et al. [5]:

(α + 1)µ low
µ( F ) = (4.11)
( )
1/β
α + 1 + 
( α+ 1)µlow Fhfs β


vsat 

TABLE 4.2
Lombardi Model: Default Coefficients for Silicon
Parameter
Symbol Name Electrons Holes Unit
B B 4.75 × 107 9.925 × 106 Cm/s
C C 5.80 × 102 2.947 × 103 Cm5/3/V–2/3s–1
NO NO 1 1 Cm–3
λ Lambda 0.1250 0.0317 1
K K 1 1 1
δ Delta 5.82 × 1014 2.0546 × 1014 Cm2/Vs
A A 2 2 1
α⊥ Alpha 0 0 cm–3
N1 N1 1 1 cm–3
V Nu 1 1 1
η Eta 5.82 × 1030 2.0546 × 1030 V2cm–1s–1
lcrit L-crit 1 × 10–6 1 × 10–6 cm
180 Technology Computer Aided Design: Simulation for VLSI MOSFET

TABLE 4.3
Canali Model Parameters (Default Values for Silicon)
Parameter
Symbol Name Electrons Holes Unit
β0 Beta0 1.109 1.213 1
βexp Betaexp 0.66 0.17 1
α alpha 0 0 1

where µ low denotes the low-field mobility, and Fhfs is the driving field. The
exponent β is temperature dependent according to:

βexp
 T  (4.12)
β = β0 
 300 K 

4.5.3  Design Continuation

This file “crc_des.cmd” is required to apply voltage at its different terminals.
This file script is given here.

* Quantum

File{
Grid = “ crc_mesh.tdr “
Plot = “crc_des.tdr”
Current = “crc_des.plt”
Output = “crc_des.log”
}
Electrode{
{Name=“source” Voltage=0.0}
{Name=“drain” Voltage=0.0}
{Name=“gate” Voltage=0.0}
{Name=“body” Voltage=0.0}
}

Physics{
* DriftDiffusion
eQuantumPotential
EffectiveIntrinsicDensity(OldSlotboom)
Mobility(
DopingDep
eHighFieldsaturation(GradQuasiFermi)
hHighFieldsaturation(GradQuasiFermi)
Device Simulation Using ISE-TCAD 181

Enormal
)
Recombination(
SRH(DopingDep)
)
}
Plot{
*— Density and Currents, etc
eDensity hDensity
TotalCurrent/Vector eCurrent/Vector hCurrent/Vector
eMobility hMobility
eVelocity hVelocity
eQuasiFermi hQuasiFermi

*— Temperature
eTemperature Temperature * hTemperature

*— Fields and charges

ElectricField/Vector Potential SpaceCharge

*— Doping Profiles
Doping DonorConcentration AcceptorConcentration

*— Generation/Recombination
SRH Band2Band * Auger
AvalancheGeneration eAvalancheGeneration
hAvalancheGeneration

*— Driving forces
eGradQuasiFermi/Vector hGradQuasiFermi/Vector
eEparallel hEparallel eENormal hENormal

*— Band structure/Composition
BandGap
BandGapNarrowing
Affinity
ConductionBand ValenceBand
eQuantumPotential
}
Math {
Extrapolate
Iterations=20
Notdamped=100
RelErrControl
ErRef(Electron)=1.e10
ErRef(Hole)=1.e10
}
182 Technology Computer Aided Design: Simulation for VLSI MOSFET

Solve {
*- Build-up of initial solution:
NewCurrentFile=“init”
Coupled(Iterations=100){Poisson eQuantumPotential}
Coupled{Poisson Electron Hole eQuantumPotential}

*- Bias drain to target bias

Quasistationary(
InitialStep=0.01 Increment=1.35
MinStep=1e-5 MaxStep=0.2
Goal{Name=“gate” Voltage=2.0 }
){Coupled{Poisson Electron Hole eQuantumPotential}
}

*- gate voltage sweep

NewCurrentFile=“”

Quasistationary(
InitialStep=1e-3 Increment=1.35
MinStep=1e-5 MaxStep=1.1
Goal{Name=“drain” Voltage=2.0}
){Coupled{Poisson Electron Hole eQuantumPotential}
CurrentPlot(Time=(Range=(0 1) Intervals=20))
}
* none
}

This will generate output files “crc_des.tdr”, “crc_des.plt”, and “crc_des.log”.

4.6 Tecplot
Tecplot is a plotting software with extensive 2D and 3D capabilities for visu-
alizing data from simulations and experiments. Tecplot can be started at the
command prompt without loading any data file:

> tecplot_sv

4.6.1  Input Files

Two types of files can be loaded into Tecplot SV. The first type is the .tdr file.
This file is used to describe a device structure, corresponding meshing, and
the values of the field quantities existing in the corresponding device. The
other type is the .plt file. Datasets included in this file are used by Tecplot SV
to generate X-Y plots. Loading can be performed initially when Tecplot SV is
started from the command line or interactively after Tecplot SV has started.
Device Simulation Using ISE-TCAD 183

4.7 Inspect
Inspect tool is used for efficient viewing of X-Y plots such as doping profiles
and I-V curves. An Inspect curve is a sequence of points defined by an array
of x coordinates and y coordinates. Inspect extracts parameters such as junc-
tion depth, threshold voltage, and saturation currents from the respective
X-Y plot. It is possible to manipulate curves interactively by using scripts.
Inspect features a large set of mathematical functions for curve manipulation
such as differentiation, integration, and to find min/max. The inspect script
language is open to tool command language (TCL) and therefore inherits all
the power and flexibility of TCL. To start inspect, at the command line type:
inspect.

4.8  Parameterized Scripting

This section describes the use of script language for constructing parameter-
ized devices. This technique enables the user to generate a device of various
geometries without explicitly specifying the coordinates while constructing.
This considerably reduces the device construction time.

; Model for Halo doped/Conventional DG Tunnel FET device

; Model for Asymmetric Heavily/Lightly Doped DG MOSFET
; All Dimensions in Nanometer initially

(sde:clear)
(define Lg 100) ;Gate length (considered the X direction)
(define tsi 70)  ;Channel Thickness (considered the Y
direction)
(define Toxf 3) ;Oxide thickness
(define xsw 100) ;shallow source drain length
(define ysw 33) ;shallow source drain depth
(define sub 50) ;substrate depth
(define GateHght 20) ;Gate Height thickness
(define Xsd (/Lg 2)) ;S/D width along X direction
(define Nsd 3.7e20) ;Constant Source drain doping (p++ type)
(define Nssd 2e20) ;
Constant shallow source Drain doping
(n++ type)
(define Ns 1e16) ;Constant reto Channel doping (n type)
(define Na 1e18) ;Constant sub Channel doping (n type)
(define Nd 1e16) ;Constant delta Channel doping (n++ type)

; TCAD Sentaurus by default assumes all dimensions in

micrometer. Thus, all the definitions stated above are
184 Technology Computer Aided Design: Simulation for VLSI MOSFET

considered in micrometer. However, to convert the dimension

from micrometer to nanometer, the following steps are performed.

(set! Lg (/Lg 1e3))

Let us consider the first command i.e., (set! Lg (/Lg 1e3)).
Here, the originally defined value of Lg=100 micrometer is
divided by 1e3 (1×103) to finally set the value of Lg to 100
nanometer.

(set! tsi (/tsi 1e3))

(set! Toxf (/Toxf 1e3))
(set! Xsd (/Xsd 1e3))
(set! Xsp (/Xsp 1e3))
(set! xsw (/xsw 1e3))
(set! ysw (/ysw 1e3))
(set! sub (/sub 1e3))
(set! GateHght (/GateHght 1e3))

(define d_Xmax (+ (+ Xsd (+ Xsd Lg)) (* xsw 2)))

(define d_Ymax (+ (+ (+ Toxf GateHght) tsi) sub)) ;

Let us illustrate the steps required to create region 1. This involves the cre-
ation of a rectangle, the coordinates of whose diatonically opposite corners
A and B are to be specified.

;create substrate
(sdegeo:create-rectangle
(position (* (+ (+ (/Lg 2) xsw) Xsd) -1) tsi 0)
(position (+ (+ (/Lg 2) xsw) Xsd) (+ sub tsi) 0)
“Silicon” “Body_3”)

;create channel_2
(sdegeo:create-rectangle
(position (+ (/Lg 2) xsw) tsi 0)
(position (* (+ (/Lg 2) xsw) -1) ysw 0)
“Silicon” “Body_2”)

;create channel_1
(sdegeo:create-rectangle
(position (/Lg -2) 0 0)
(position (/Lg 2) ysw 0)
“Silicon” “Body_1”)

;create shallow source

(sdegeo:create-rectangle
(position (/Lg -2) 0 0)
(position (- (/Lg -2) xsw) ysw 0)
“Silicon” “source_sh”)
Device Simulation Using ISE-TCAD 185

;create shallow drain

(sdegeo:create-rectangle
(position (+ (/Lg 2) xsw) 0 0)
(position (/Lg 2) ysw 0)
“Silicon” “drain_sh”)

;create source
(sdegeo:create-rectangle
(position (* (+ (/Lg 2) xsw) -1) 0 0)
(position (* (+ (+ (/Lg 2) xsw) Xsd) -1) tsi 0)
“Silicon” “Source”)

;create drain
(sdegeo:create-rectangle
(position (+ (/Lg 2) xsw) 0 0)
(position (+ (+ (/Lg 2) xsw) Xsd) tsi 0)
“Silicon” “Drain”)

;create oxide
(sdegeo:create-rectangle
(position (/Lg -2) 0 0)
(position (/Lg 2) (* Toxf -1) 0)
“SiO2” “oxide”)

;create oxide spacer

(sdegeo:create-rectangle
(position (* (+ (/Lg 2) xsw) -1) 0 0)
(position (* (/Lg 2) -1)(* (+ Toxf GateHght) -1) 0)
“SiO2” “oxide_2”)

;create oxide spacer

(sdegeo:create-rectangle
(position (+ (/Lg 2) xsw) 0 0)
(position (/Lg 2) (* (+ Toxf GateHght) -1) 0)
“SiO2” “oxide_1”)

;create gate electrode

(sdegeo:create-rectangle
(position (/Lg -2) (* Toxf -1) 0)
(position (/Lg 2) (* (+ Toxf GateHght) -1) 0)
“PolySi” “gate”)
186 Technology Computer Aided Design: Simulation for VLSI MOSFET

4.9  Sentaurus Workbench

Sentaurus Workbench is the complete graphical environment that inte-
grates various Sentaurus tools. It is used throughout the semiconduc-
tor industry to design, organize, and run simulations. Simulations are
comprehensively organized into projects. Sentaurus Workbench auto-
matically manages the information flow, which includes preprocessing
of user input files, parameterizing projects, setting up and executing tool
instances, and visualizing results. Sentaurus Workbench allows users to
define parameters and variables in order to run comprehensive paramet-
ric analyses. The resulting data can be used with statistical and spread-
sheet software.

4.10 Summary
TCAD refers to the use of computer simulations to model semiconductor
processing and devices. The two major functionalities of TCAD are device
simulation and process simulation. The device simulation process starts
from construction of the devices based on geometry and process parameters.
Subsequently, the device is meshed intelligently and simulated. The various
electrical characteristics can be visualized and plotted. This chapter demon-
strates the device simulation procedure through examples using Sentaurus
TCAD tool of Synopsys.

References
1. Integrated Systems Engineering (ISE) TCAD Manuals, 2006, Release 10.0.
2. Saha, Samar. Extraction of substrate current model parameters from device
simulation, Solid-State Electronics, Volume 37, Issue 10, October 1994, Pages
1786–1788.
3. Saha, Samar. Design considerations for 25 nm MOSFET devices, Solid-State
Electronics, Volume 45, Issue 10, October 2001, Pages 1851–1857.
4. MOSFET test structures for two-dimensional device simulation, original
research article, Solid-State Electronics, Volume 38, Issue 1, January 1995, Pages
69–73.
5. Canali, C., G. Majni, R. Minder, and G. Ottaviani, Electron and hole drift veloc-
ity measurements in silicon and their empirical relation to electric field and tem-
perature, IEEE Trans. on Electron Devices, vol. ED-22, pp. 1045–1047, 1975.
5
Device Simulation Using
Silvaco ATLAS Tool

Angsuman Sarkar

CONTENTS
5.1 Introduction................................................................................................. 188
5.1.1 History of Silvaco Technology Computer Aided Design
(TCAD)............................................................................................. 189
5.1.2 Device Simulation Challenges...................................................... 189
5.1.3 Application of Device Simulation................................................. 190
5.2 How the Device Simulator ATLAS Works.............................................. 190
5.3 ATLAS Inputs and Outputs...................................................................... 192
5.4 Simulation Setup......................................................................................... 194
5.5 Brief Review of Electro-Physical Models Employed in ATLAS........... 195
5.6 Choice of METHOD in ATLAS................................................................. 197
5.7 Mobility Models in ATLAS....................................................................... 199
5.8 Benchmarking of MOSFET Simulations................................................. 202
5.8.1 Method of Simulator Calibration.................................................. 203
5.8.2 Calibration of Process Simulator.................................................. 204
5.8.3 Calibration of Device Simulator................................................... 204
5.9 Importance of Mesh Optimization........................................................... 204
5.9.1 Strategy to Obtain a Satisfactory Mesh....................................... 205
5.9.2 Mesh Re-Gridding.......................................................................... 206
5.10 Introduction to Other Tools from Silvaco Used in Conjunction
with ATLAS................................................................................................. 206
5.10.1 Process Simulation Tools............................................................... 208
5.10.2 ATHENA and ATLAS.................................................................... 209
5.11 Example 1: Bulk n-Channel MOSFET Simulation.................................. 209
5.11.1 Program for Bulk n-Channel MOSFET Simulation................... 210
5.11.2 Simulation Results.......................................................................... 212
5.12 Example 2: Silicon-on-Insulator (SOI) MOSFET Simulation................ 213
5.12.1 Program Description for SOI MOSFET Simulation................... 213
5.12.2 Simulation Results.......................................................................... 219
5.13 Example 3: 0.18 µm Bulk nMOS Transistor with Halo Implant........... 219
5.13.1 Program for 0.18 µm Bulk nMOS.................................................. 220
5.13.2 Simulation Results..........................................................................225

187
188 Technology Computer Aided Design: Simulation for VLSI MOSFET

5.14 Example 4: Volume Inversion Double-Gate (DG) MOSFET................. 226

5.14.1 Program for Structure of DG MOSFET....................................... 227
5.14.2 Program to Obtain Potential Variation of DG MOSFET........... 228
5.14.3 Simulation Results.......................................................................... 229
5.14.4 Program to Obtain Ids-Vgs Characteristics of DG MOSFET....... 231
5.14.5 Simulation Results.......................................................................... 232
5.15 Summary...................................................................................................... 232
References.............................................................................................................. 233

5.1 Introduction
One of the critical issues for the fabrication of integrated circuits (ICs) is
precise design of the operation of the circuits containing huge numbers of
transistors. It is quite natural to predict the device operation by computer
calculations using the simulators and device models. Devices scaled down
to deca-nanometer range, operating at their physical limits, put stringent
requirements on the modeling and simulation of device characteristics [1].
Computer aided modeling and simulation plays a crucial role in the devel-
opment and prediction of the properties of modern technologies. Because
of trial manufacturing and circuit redesign, the cost of modern, highly
dense ICs containing deep sub-micron devices is very high. Simulation
allows visualization and better understanding of the microscopic physical
phenomenon and effects taking place over very small lengths or over small
periods in macroscopic dimensions. To achieve these goals, over the past
twenty years, two/three-dimensional numerical technology computer aided
design (TCAD) device simulation tools have evolved into a well-accepted
and extremely important branch of electronic design and automation (EDA)
tools. It is suitable for the analysis and characterization of semiconductor
structures and devices standing alone and/or coupled in integrated circuits
[2]. TCAD has already been considered an invaluable tool in the research and
development of new technology at the level of semiconductor process and
device design.
The goal of this chapter is to introduce the device simulation of metal-
oxide-semiconductor field-effect transistor (MOSFET) using Silvaco (Silicon
Valley Corporation) TCAD device simulation tools using selected examples.
The chapter illustrates the key aspects of Silvaco TCAD tools, showing their
capability to understand the physical behavior and potential of a device
structure. Silvaco TCAD device simulators provide unique insight into the
internal operation of the analyzed device structure using a variety of com-
plex physics-based models and advanced numerical solvers securing stable
calculations.
Device Simulation Using Silvaco ATLAS Tool 189

Any semiconductor device is represented by a structure whose electrical

and physical properties are discretized onto a mesh of nodes. The two/three-
dimensional device structure may be the output of the process simulator or
can be supplied from an input file containing the mesh information, types
of materials, doping profiles in specific regions, names of the terminals, and
properly defined boundary conditions with applied external electrical, opti-
cal, mechanical, magnetic, and thermal fields. An extensive set of electro-
physical models is also supplied to characterize the behaviors of various
physical effects present in a semiconductor. A device simulator calculates
the output characteristics by solving a set of partial differential equations
through iterative numerical techniques.
Two-dimensional device simulation with properly selected calibrated
models and a well-defined appropriate mesh structure are very useful for
predictive parametric analysis of novel device structures.

5.1.1  History of Silvaco Technology Computer Aided Design (TCAD)

Examples of early numeric simulation of semiconductors can be found in
[3,4]. The journey of modern commercial TCAD started with the devel-
opment of two famous general-purpose simulation software programs.
SUPREM (Stanford University Process Engineering Models) and PISCES
(Poisson and Continuity Equation Solver) came as an outgrowth of the
research done at Stanford University. SUPREM3 is a one-dimensional pro-
cess simulator, while SUPREM4 is a two-dimensional process simulator.
PISCES is the corresponding two-dimensional device simulator. TSUPREM4
and MEDICI are the versions of these programs of Technology Modeling
Associates (TMA) formed in 1979. ATHENA and ATLAS are commercial
equivalent alternatives of these programs, as Silvaco later licensed these pro-
grams from Stanford University. The other major TCAD vendor is Integrated
Systems Engineering (ISE). Their equivalent alternative products are DIOS
and DESSIS from ISE.
Many other specific MOSFET device simulators have been developed, such
as MINIMOS from the Technical University of Vienna, SEQUOIA Device
Designer, FLOOPS/FLOODS from the University of Florida, IBM’s FEDSS/
FIELDAY, Agere’s PROPHET/PADRE, APSYS, C-SUPREM and PROCOM
from Crosslight, and Visual TCAD from Cogenda.

5.1.2  Device Simulation Challenges

There was always skepticism within the industry about the ability of TCAD
device simulation procedure to correctly predict the experimental results.
The primary reason for these discrepancies includes the lack of adequate
models to describe the physical behavior of the actual device, the selection of
appropriate electro-physical models, proper optimization of mesh structure,
and the constant evolution of technology. As the technology scales down,
190 Technology Computer Aided Design: Simulation for VLSI MOSFET

MOS transistors with channel lengths as small as 10 nm are now being

actively studied both theoretically and experimentally [5]. Advances in scal-
ing of MOSFET resulted in new physical effects like quantum mechanical
effects, stress effects, introduction of new materials, etc., which are becom-
ing pertinent to deep sub-micron devices. Therefore, the current challenge
in device simulation is to address those new physical effects [5,6] in order to
obtain accurate results.

5.1.3  Application of Device Simulation

The goal of the device simulation procedure is to use the output of the simu-
lation process for predictive analysis of the properties and behavior of the
simulated device structure with a unique insight into the internal process
and structure operation, along with the possibility of further optimization
and development. Two- and three-dimensional modeling and the simulation
process contribute to a better understanding of the properties and behavior
of the new devices by identifying the inevitable parasitic devices attributing
to standard malfunction behaviors and degraded performances. Based on
the interpretation of experimentally obtained data along with the result of
device simulation, new structures and devices with modified layouts and
concentration profiles can be designed and verified. More on TCAD applica-
tions can be found in [7,8].

5.2  How the Device Simulator ATLAS Works

ATLAS is a device simulation tool. The framework of ATLAS combines sev-
eral one-, two-, and three-dimensional simulation tools into one compre-
hensive device simulation package. This allows for the simulation of a wide
variety of modern semiconductor devices.
ATLAS is a physically based predictive device simulator that predicts the
electrical characteristics associated with specified physical structures and
bias conditions to provide insight within device operation and behavior.
To simulate a device in ATLAS, a description of the device is required.
Descriptions of the device meshed with a two- or three-dimensional grid
are provided via ASCII command line instructions supplied to ATLAS. The
two- or three-dimensional grid approximating the device structure consists
of a number of grid points known as nodes. The maximum number of grid
points is limited to 20,000, a constraint set by ATLAS.
Figure 5.1 illustrates the main components of semiconductor device simu-
lation. There are two main strongly coupled sets of equations that must be
solved consistently. They are the transport equations governing the flow of
the charges within the semiconductor, and the fields driving such charge
Device Simulation Using Silvaco ATLAS Tool 191

Electronic structures,
Lattice dynamics

J, ρ
Electromagnetic Transport Equations
Fields
E, B

Device Simulation

FIGURE 5.1
The ATLAS device simulation approach.

flow. Such fields are obtained from the solution of Maxwell’s equations.
These quasi-static fields are calculated from Poisson’s equations with the aid
of available boundary conditions. These fields are the driving forces for the
charge transport.
In ATLAS, the transport of carriers is calculated at every node of the grid
by applying a set of differential equations, derived from Maxwell’s laws
along with physical models (i.e., with appropriate numerical solvers invoked
by the user). A set of differential equations on the grid is applied. With a bias
point specified, the properties of the carriers in the device are solved through
an iterative procedure. This facilitates the user to analyze electrical, thermal,
and optical characteristics of the devices through simulation without having
to manufacture the actual device and also to determine static and transient
terminal currents and voltages in DC, AC, or transient modes of operation.
In order to complete a simulation run, ATLAS solves six equations for
every point on the mesh structure defined. They are the Poisson’s equation,
two carrier continuity equations, two energy balance equations, and the lat-
tice heat flow equation. The choice of techniques in solving these numerical
equations can strongly affect the convergence time of a complete simulation
run. However, in some circumstances it is sufficient to solve only one (either
hole or electron) carrier continuity equation. It is possible to supply param-
eters to the METHOD statement to specify which carrier (electron, hole,
or both) continuity equation is to be solved. The choice can be made using
the parameters CARRIERS. For example, to include both electron and hole,
the user must specify “CARRIERS = 2” and for only holes “CARRIERS = 1
HOLE” in the METHOD statement.
The user has to provide the structural information of the device to be sim-
ulated (appropriate mesh structure) to invoke the appropriate physical mod-
els and their associated numerical solvers and to set the desired bias profile
for ATLAS to predict the electrical behavior of a particular device.
192 Technology Computer Aided Design: Simulation for VLSI MOSFET

5.3  ATLAS Inputs and Outputs

To set up a device simulation, the first step required is to define the mesh
structure of the device. Mesh structure can be created by entering text-based
command line instructions in DECKBUILD or graphically by DEVEDIT.
The text-based commands like Mesh, region, electrode, doping, etc., require
definition of a structure given in a particular order, shown in Figure  5.2.
Examples in Sections 5.11, 5.12, and 5.14 demonstrate the creation of device
structure using command line instructions. It is possible to create the same
structures using DEVEDIT (GUI-based structure and mesh editor) which
work in conjunction with ATLAS. DEVEDIT is normally preferred to solve
the problems of inadequate or excessive triangles to generate non-uniform
mesh structure. DEVEDIT is also useful for re-meshing a device structure
suffering with unsatisfactory mesh density during the process and the
device simulation, or in an intermediate stage between the process and the
device simulation. But it is worth mentioning that numerical process simula-
tor ATHENA should not be replaced by DEVEDIT when it is important to
obtain a device structure close to the real-world fabricated device. DEVEDIT
produces two types of output: (1) standard Silvaco structure file format (*.str)
containing mesh, region, impurity information, etc., and (2) command for-
mat (*.de) containing list of DEVEDIT instructions to specify the current state
of mesh development. The Meshbuild command creates a mesh using the
mesh parameters available. DEVEDIT file should be saved into two formats:
(1) standard Silvaco structure (*.str) to be used in subsequent device simula-
tion using tools like ATLAS and TONYPLOT or (2) command file (*.de) with
the possibility to change the structure and mesh at a later time. The output of
the process simulator ATHENA also produces structure file to be simulated
using ATLAS (demonstrated via example in Section 5.13).
In summary, simulations generally use two inputs: a text file that has com-
mands for ATLAS to execute and a structure file that defines the structure
of the device. The text file with simulator-specific commands is created with
DECKBUILD. The syntax of the input file statement is:

<statement> <parameter>=<value>.

The parameters can be real, integer, character, or logical.

The designer uses ATLAS to solve the input files to generate and visualize
output data. ATLAS provides three types of output:

1.
Run-time output: The progress of the simulation and error or warning
messages are given by the run-time output. The various parameters
displayed during the SOLVE statement are (a) “proj” denoting the
initial guess methodology used (previous, local, or init); (b) “i,j,m”
indicates the iteration number of outer loop, inner loop for decoupled
Device Simulation Using Silvaco ATLAS Tool 193

(a) Structure Specification

(d) Solution Specification
• Structure MESH specification
• LOG file declaration to contain
• Structure REGION specification
I-V characteristics
• ELECTRODE placement • Solution of device using SOLVE
with intervals for bias voltage
• DOPING profile specification
(or drive current) specification

• Specifying data types to be

solved (e.g., recombination
(b) Model Specification parameter, bad energy, etc.).

• Defining MATERIAL type for

each region (SiO2 or Al, etc.) (e) Result Analysis

• Invoke appropriate physical • Parameter extraction via

MODELS EXTRACT command
• Setting boundary conditions • Analyzing device structure
and CONTACT information with different bias condition
• INTERFACE specification using graphical post-process-
ing tool TONYPLOT

(c) Numerical Method Selection

• Invoke suitable numerical solv-

ers such as Gummel, Newton,
or Bulk METHOD for differ-
ent operating conditions with
appropriate parameters such as
number of iteration, error limit,
etc.

FIGURE 5.2
The order of each command group to be specified in ATLAS from (a) to (e).

method and numerical method used; m = G, B or N denoting G =

Gummel, B = Block, and N = Newton, respectively. (c) x,rhs denotes
norms of the equation being solved, and (d) (*) indicates the error
measure.
2.
Log files: These contain the electrical information, or more precisely
I-V data, generated with the currents and terminal voltages applied
during device analysis.
194 Technology Computer Aided Design: Simulation for VLSI MOSFET

ATLAS
Runtime output
output
&
ATLAS parameters
input extracted in
Command deckbuild
Deckbuild
file

ATLAS device
simulator Log files
Athena

Tonyplot
Structure
file Solution
files saved
Devedit in structure

FIGURE 5.3
Input and output in ATLAS.

3.
Silvaco general structure file: The structure files store the two- and
three-dimensional data relating to the values of solution variables
such as electric field, electrostatic potentials, etc., within the device
for a single bias point.

The log files and the solution structure files are visualized using
TONYPLOT. Figure  5.3 summarizes the various input and output tech-
niques available for device simulation using ATLAS.

5.4  Simulation Setup

Once a structure file is defined in ATLAS, the remaining part of the setup
(except for result analysis) consists of providing command line instruc-
tions that must be used to instruct ATLAS in order to complete a simulation
run. The order in which these instructions are given is important and can
be divided into five groups of statements outlined in Figure 5.2. Failing to
adhere to this order may result in premature termination of a simulation
run, or in an error message being produced. The order of statements within
each group such as structural definition, model specification, and solution
groups is also important. Failing to place these statements in proper order
may result in aforementioned complications.
Device Simulation Using Silvaco ATLAS Tool 195

5.5 Brief Review of Electro-Physical

Models Employed in ATLAS
The accuracy of the results obtained by device simulation process using
ATLAS depends on the models used in the simulation process. Normally
physics-based models are used to account for the complex dependencies of
the device properties on dimensions and other process variables. Generally,
the model parameters are derived from measurements and characteristics of
the devices.
The drift-diffusion (DD) model is the simplest current transport model
and is derived from Boltzmann’s transport equation (BTE). It is famous for
its simplicity and most efficient approach. Over a long period of time, this
model has been at the core of semiconductor device simulation. The robust
discretization of the DD equations proposed by Scharfetter and Gummel
[9] is still in use today. In isothermal simulation, this simplest DD model
includes three partial differential equations (PDEs): Poisson’s equation and
current continuity equations for electrons and holes. The total current den-
sity at any point (sum of electron and hole current) of the structure is found
after solving the free electron and hole concentrations using potential and
variable parameters like mobility, electric field and generation-recombination
rate, etc.
As technology moves forward, devices scale down to sub-micron regime,
without scaling the supply voltages proportionately. This results in a large
electric field inside the device. As this large electric field changes quickly
over small lengths, it brings about non-local and hot-carrier effects that tend
to dominate device performance. Therefore, non-stationary carrier transport
phenomenon such as velocity overshoot, which substantially influences the
on-current (mainly the drift-current) of the MOSFET should be taken into
account in the simulation. This makes the suitability of the DD model highly
questionable for the simulation of nanometer MOSFET, as it neglects non-
stationary effects.
As a result, transport models have been refined and extended to capture
the practical transport phenomena more accurately. To address this issue,
extensions of the DD model have been proposed. The extensions add a bal-
ance equation for the average carrier energy. They also add a driving term to
the current relation, proportional to the gradient of the carrier temperature.
A non-isothermal thermodynamic model is chosen where self-heating
effects are involved. Therefore, additional PDEs corresponding to non-
isothermal temperature distribution must be coupled [10].
A more complex hydrodynamic (HD) or energy balance model is chosen
for deep sub-micron devices, which involves solution of six coupled par-
tial differential equations: three basic semiconductor equations and three
196 Technology Computer Aided Design: Simulation for VLSI MOSFET

energy balance equations. The individual electron and hole temperatures are
calculated from the energy balance equation.
In the HD model the equation set of the DD model is extended by the
energy balance equation to allow for non-stationary carrier transport. The
disadvantages of the HD model are that it is less stable than DD, it is less effi-
cient in terms of computation time than DD, and it sometimes overestimates
the current in MOSFET [11].
The typical hierarchy of the MOSFET simulation approach consists of DD,
HD, and Monte Carlo (MC) methods. MC is most reliable for calculation
of on-current. Unfortunately, the added accuracy comes at the expense of
higher computational complexity as compared to HD and DD. Thus MC is
not suitable for investigations where large numbers of different transistors
are to be simulated. Even 3D simulations necessary for FinFETs are diffi-
cult with MC. Furthermore, because of its statistical nature, the MC method
has serious problems in calculating the very low subthreshold currents of
MOSFETs accurately.
In a recent study, it was shown that the DD on-current is 10% less than
MC-current calculated for a 100-nm MOSFET [12]. For shorter length
MOSFET such as 40 nm, the difference of on-current is about 40% [13].
However, the on-current simulated by DD can be improved by adjusting
the mobility model used. For the calculation of subthreshold current, the
DD model is best suited for both long and short channel MOSFETs [14].
Granzner et al. [15] suggested that modifications of the velocity-field char-
acteristics in the DD simulations are suggested to improve the accuracy of
the DD model, and for the simulation of subthreshold current the standard
DD model is best suited.
To incorporate quantum-mechanical effects (QMEs) that are significant for
highly scaled deca-nanometer devices, the Schrödinger equation should be
solved self-consistently in order to obtain the most accurate simulation result.
Therefore, to achieve maximum predictive capability one needs to
move toward the quantum transport regime of the hierarchical struc-
ture shown in Figure  5.4. The green function’s approach [16] shown
in Figure  5.4 is most difficult in terms of complexity of equations and
numerical efficiency.
The details of various advanced electro-physical models to characterize
the properties and behavior of analyzed semiconductor device structures
can be found in the user manual of simulator ATLAS [17].
Physical models are specified in the “MODELS” statement depending on
the material used and physical nature of the device. For example, the state-
ment “MODELS CVT SRH FERMIDIRAC” enables the Lombardi mobil-
ity model (constant voltage and temperature, CVT), Shockley-Read-Hall
recombination with fixed carrier lifetimes (SRH) and Fermi-Dirac statistics
(FERMIDIRAC) for common long-channel Si-MOSFET simulation.
Device Simulation Using Silvaco ATLAS Tool 197

Approximate
Easy, Fast

Compact models Appropriate for circuit design

Semi-classical
Approaches
Simpler and efficient, but not suitable for sub-micron
Drift-diffusion equations
devices, can not capture non-stationary carrier transport
Extension of DD model with energy balance equation, can
Hydrodynamic models
treat velocity overshoot effect
Boltzmann’s Transport equation
Accurate up to classical limits
Monte Carlo Method
In addition to all classical Hydrodynamic features, quantum
Exactness of Solution
Numerical Complexity

Quantum Hydrodynamics
correction terms are present to obtain more exact solution
In addition to all classical features, quantum correction

Approaches
Quantum Monte Carlo

Quantum
terms are present to obtain more exact solution
Include correlations in both time and space domains,
Green’s Function
higher accuracy with a higher numerical complexity
Self consistent Schrödinger’s Most accurate, at the same time most difficult solution
Equation solution type, can be solved for small number of particles
Difficult

Exact

FIGURE 5.4
Hierarchy of transport model in Silvaco ATLAS.

5.6  Choice of METHOD in ATLAS

The equations can be solved either by a fully coupled (Newton), de-coupled
(Gummel), or combined (Block) manner. The coupled solutions with all equa-
tions solved at once are best when the interactions between the equations
are strong (e.g., high current producing sufficient local heating). Newton’s
method is a fully coupled procedure that solves the equations simultane-
ously, through a generalization of the Newton-Raphson’s method for solving
the roots of an equation. However, they need a good initial guess as to the
solution variables for reliable convergence. Unless special techniques such
as projection are used for calculating the initial guess, the voltage step size
during a bias ramp in a fully coupled solution might be small in order to
obtain reliable convergence. Also, the Newton method may spend extra time
solving the quantities that are weakly coupled or almost constant. Newton’s
method is the default method or drift-diffusion calculation in ATLAS. Other
than that, ATLAS requires Newton’s method for DC calculations using
lumped elements, transient calculations, and frequency-domain small-
signal analysis.
198 Technology Computer Aided Design: Simulation for VLSI MOSFET

On the other hand, de-coupled solutions where a subset of the equation

is solved while others are held constant has shown an advantage when the
interaction between the equations is small (typically low voltage and current
levels). They tolerate a relatively poor initial guess for convergence. They tend
to either diverge or take excessive central processing unit (CPU) time once
the interaction among the equations becomes stronger. Gummel’s method
cannot be used with lumped elements or current boundary conditions. In a
typical fully de-coupled procedure, if we choose quasi-Fermi level formula-
tion, at first non-linear Poisson’s equation is solved. The potentials obtained
are substituted into continuity equations that are now linear and solved
directly. The results in terms of quasi-Fermi levels are substituted back to
Poisson’s equation until the convergence is reached, as shown in Figure 5.5.
In general, Gummel’s method is useful where the system of equations is weakly
coupled, but it has only linear convergence. The Newton method is useful when
the system of equations is strongly coupled and has quadratic convergence.
Gummel’s method can provide better initial guess to the problems.
Therefore, it is possible to start a solution using few Gummel’s iterations to
generate a good initial guess and then switch to Newton to complete the
simulation [18], as shown in Figure 5.6.
The combined method will solve some equations fully coupled and the
remaining others using a de-coupled method. The Block method can pro-
vide faster simulation than Newton’s method for solving quantities that are
weakly coupled. They involve solving a subgroup of equations in various
sequences. In non-isothermal drift-diffusion simulation using Block method,

Guess V, n, p

Solve Poisson’s equation for

new V

Repeat
until Solve electron concentration for
satisfied new n

Solve hole concentration for

new p

FIGURE 5.5
Uncoupled numerical solution.
Device Simulation Using Silvaco ATLAS Tool 199

Set up device Newton’s

dimensions, Converged? method for
numerical Yes better accuracy
properties, bias No
conditions,
temperature,
doping profile etc.

Iterative
Gummel’s Current C
Block method Continuity?
solve for Φ, n, p No

Yes

Initial
Discretization of Extract electron,
guess for
semiconductor hole concentration,
Φ, Φn
equation current density, I-V
and Φp
characteristics etc.

FIGURE 5.6
Steps for numerical solutions.

Newton’s method is solved for a constant lattice temperature to update car-

rier concentration and potential, after which a heat flow equation with the
appropriate continuity equation is solved using a de-coupled method to
update carrier temperature and carrier concentration.

5.7  Mobility Models in ATLAS

The choice of carrier mobility models is one of the most important decisions
of TCAD device simulation. This is governed by physical parameters, ambi-
ence, and operating conditions.
Electrons and holes accelerate by electric fields but lose momentum due to
various scattering processes like lattice vibrations (phonons), impurity ions
or other carriers, surfaces, and other material imperfections. Various micro-
scopic phenomena affect the macroscopic mobility specified in the transport
equation. Hence these mobilities are functions of the local electrical field,
doping concentration, lattice temperature, and many other parameters.
Based on the operating region, mobility models can generally be classified
into four types: (1) low field, (2) high field, (3) bulk semiconductor region, and
(4) inversion region.
From an alternative perspective, mobility models can be categorized
into three types: (1) physically based, (2) semi-empirical, and (3) empirical.
200 Technology Computer Aided Design: Simulation for VLSI MOSFET

Physical-based mobility models are obtained from fundamental calcula-

tions using a lot of approximations, and they rarely match the experimental
data. In a semi-empirical model, to obtain an agreement between the model
and the experimental result, the coefficients of the physical-based models
are allowed to vary, keeping the power law dependencies preserved. In con-
trast, it is possible to vary the power-law dependencies in a purely empirical
model, exhibiting the lowest physical content and a narrower range of validity.
The most popular mobility models used in ATLAS are listed in Table 5.1.
Low field mobility degrades upon phonon and impurity scattering and
is valid for carriers present in the bulk under low electric field. The high
TABLE 5.1
Summary of the Popular Mobility Model Used in ATLAS
Model Behavior Syntax Features
Constant Low-field MUN, MUP, TMUN, Constant low-field mobility
low-field behavior and TMUP are with only temperature
mobility model specified in variation
MOBILITY statement
Concentration- Low-field CONMOB in MODELS Look up table based, valid
dependent behavior statement and for Si, GaAs at 300 K
low-field model parameters in
MOBILITY statement
Concentration, Low-field ANALYTIC in Based on Caughey-Thomas
temperature- behavior MODELS and formulae, valid between 77
dependent parameters in and 450 K
analytical model MOBILITY statement
Arora’s analytical Low-field ARORA in MODELS Alternatives to analytic
model behavior and parameters in model, doping and
MOBILITY statement temperature dependent
Masetti analytical Low-field MASETTI in MODELS Optimized for room
model for behavior and parameters in temperature, concentration
low-field MOBILITY statement dependent
mobility
Carrier-carrier Low-field CCSMOB parameter in Temperature, doping, and
scattering model behavior MODELS and carrier-carrier scattering
with parameters in dependent, useful when
carrier- MOBILITY statement carrier concentration is
carrier very high such as forward
scattering bias power devices
Klassen unified Low-field KLA parameter in Temperature dependent,
low-field behavior MODELS and KLA.N doping dependent,
mobility model and KLA.P includes the effect of lattice
parameters in scattering, impurity
MOBILITY statement scattering, carrier-carrier
scattering, and impurity
clustering. Uses separate
mobility for majority and
minority carriers, useful
for bipolar devices
Device Simulation Using Silvaco ATLAS Tool 201

TABLE 5.1 (CONTINUED)
Summary of the Popular Mobility Model Used in ATLAS
Model Behavior Syntax Features
Lombardi (CVT) Inversion CVT on the MODELS Transverse field, doping, and
inversion layer layer statement and temperature-dependent
mobility model parameters in parts of mobility are
MOBILITY statement combined. Overrides any
other mobility model used
in MODELS statement
Yamaguchi Inversion YAMAGUCHI in Low-field, doping-
inversion layer layer MODELS and dependent mobility with
mobility model parameters in surface-degradation
MOBILITY statement dependent on parallel filed
included
Tasch model Inversion TASCH in MODELS Explicitly for MOSFETs,
layer statement and includes transverse field
parameters in dependence for planar
MOBILITY statement devices with very fine
mesh structure
Shirahata model Inversion SHI in MODELS General-purpose MOSFET
layer statement and SHI.N mobility model, an
and SHI.P parameters alternative surface
in MOBILITY mobility model that can be
statement combined with Klassen
model
Watt surface Perpendicular SURFMOB parameter Includes phonon scattering,
mobility model electric field on the MODELS surface roughness
dependent statement and scattering, and charged
parameters in impurity scattering
MOBILITY statement
Saturation Parallel FLDMOB parameter on Caughey and Thomas
velocity model electric field the MODELS expression is used to
dependent statement and BETAN calculate field-dependent
mobility and BETAP mobility, getting reduced
parameters in at high field due to
MOBILITY statement velocity saturation effect,
model parallel field
dependence for Si and
GaAs

electric field dependent parameter decreases with increasing high electric

field, making the velocity of the carrier constant known as saturation velocity.
Bulk mobility modeling generally requires:

1. Identification of low field mobility as a function of doping and lat-

tice temperature
2. Identification of saturation velocity as a function of temperature
3. Description of transition between high and low field region
202 Technology Computer Aided Design: Simulation for VLSI MOSFET

In ATLAS, low field mobility for the bulk region includes:

1. Constant mobility model

2. Caughey and Thomas model (doping and temperature dependent) [19]
3. Arora model (doping, temperature and carrier-carrier scattering
dependent) [20]
4. Klaassen unified low-field mobility model (unified minority and
majority carrier mobility, includes lattice scattering, carrier-carrier
scattering, impurity-clustering effects at high concentrations) [21,22]

It is important to model mobility dependent on the transverse electric field

associated with inversion layers in order to obtain accurate results. ATLAS
supports five major transverse field-dependent mobility models. They are
the CVT (Lombardi) MODEL [23], Watt model [25], Shirahata model [26],
Yamaguchi model [27], and Tasch model [28].
In ATLAS, the CVT [23] model is selected by specifying CVT on the model
statement. This model overrides any other mobility model specification. In
the CVT model, three different components based on transverse field and
doping concentrations are combined using Mathiessen’s rule [24]. The com-
ponents are µAC, µsr, and µb. µAC is the surface mobility limited by scattering
with acoustic phonons. µsr is a mobility component limited by surface rough-
ness. µb is the mobility component limited by scattering with optical inter-
valley phonons. According to Mathiessen’s rule the total mobility in a CVT
model is given by µT−1 = µ −AC
1
+ µ −sr1 + µ b−1 .
The Watt model (SURFMOB) [25] is a surface mobility model and is acti-
vated by specifying the parameter WATT in the MODEL statement. The Watt
model takes into consideration the phonon scattering, surface scattering, and
charge impurity scattering mechanisms in the inversion layer.
The Shirahata model [26] is enabled by specifying the SH parameter of
the model statement. It is a general-purpose MOS mobility model that takes
into account the screening effect in inversion layers and perpendicular field
dependence for thin gate oxides. When the user enables Shirahata model,
ATLAS automatically enables Klaassen’s model [21,22].
The Yamaguchi model [27] and the Tasch model [28] are selected by set-
ting YAMAGUCHI and TASCH, respectively, on the MODEL statement. The
model overrides all mobility models other than CVT.
ATLAS invokes filed dependent mobility models if FLDMOB is specified
in the MODEL statement. FLDMOB should always be specified unless one of
the inversion layer mobility models (exhibits parallel field dependency itself)
is specified.
In ATLAS, it is possible to use more than one mobility model. The
default mobility model is the constant low field mobility µno and µpo for
electron and hole, respectively. Values of µno and µpo may be specified in
the MATERIAL statement using the parameters “MUN” and “MUP”. This
Device Simulation Using Silvaco ATLAS Tool 203

particular constant mobility is of no practical use because it leads to unre-

alistic high carrier velocity at high electric fields. Therefore, in order to
achieve a successful prediction of a MOSFET device, it is necessary to use
multiple non-conflicting mobility models simultaneously. It is also neces-
sary to know which models are overriding others when conflicting mobil-
ity models are defined.
In ATLAS the mobility model to be used is specified in the MODEL state-
ment. Detailed parameters associated with the chosen mobility models are
specified on a separate MOBILITY statement.
For example, the ATLAS model statement shown below uses the constant
voltage and temperature (CVT) Mobility Model for MOSFET in an ATLAS
program. It is beyond the scope of this chapter to discuss in detail the param-
eters of the mobility model used.

models srh conmob fldnob b.electrons=2 b.holes=l evsatmod=0

hvsatmod=0 cvt boltzmann print numcarr=1 electrons temperature=300

mobility material=CVT parameter bn.cvt=4.75e+07 bp.cvt=9.92

5e÷06 cn.cvt=174000 cp.cvt=884200 taun.cvt=0.125
taup.cvt=0.0317 gamn.cvt=2.5 gamp.cvt=2.2 mu0n.cvt=52.2
mu0p.cvt=44.9 mu1n.cvt=43.4 mu1p.cvt=29 mumaxn.cvt=1417
mumaxp.cvt=470.5 crn.cvt=9.16e+16 crp.cvt=2.23e+17 csn.cvt=3
43e+20 csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 bctap.cvt=2 pcn.cvt=0 pcp.cvt=2.3e+15
deln.cvt=5.82e+14 delp.cvt=2.0546e+14

5.8  Benchmarking of MOSFET Simulations

Computer simulations allow modified devices to be tested within a few hours,
although this can stretch out to days, and simulations also do not consume
valuable raw materials or production time. However, the accuracy of computer
models is always subject to question. This has led to the development of many
different models for carrier mobility as well as different carrier transport models.

5.8.1  Method of Simulator Calibration

Typical TCAD tools, including both the process and the device simulators,
are accurate, or predictive, but only for a sufficiently stable and mature tech-
nology, and after a lengthy calibration procedure [29]. This poses the issue of
the relevance of device simulation for the development of a new technology
204 Technology Computer Aided Design: Simulation for VLSI MOSFET

node, in which new processes and materials are introduced which are not
under complete control until the technology is finally released, and for
which doping profiles and geometry are not known with sufficient accu-
racy. However, although not fully predictive, the positive aspects of TCAD
that make them useful are that they still provide optimization guidelines,
explanations of the characterization results, and insights into the transport
mechanisms. Therefore, it is extremely important to calibrate the process
and device simulator tools not just to reproduce qualitative behaviors but
also to obtain accurate device characterization.

5.8.2  Calibration of Process Simulator

Selection of the appropriate process coefficients and the process models of
processes like diffusion, ion-implantation, etc., is the most critical part of the
entire calibration procedure of a process simulator creating a virtual two-
dimensional device simulator. Thereafter the lengthiest task is to match the
profiles of the actual device with the virtual device, for example, doping pro-
file extraction from a physical device. The matching procedure effectively
calibrates the simulator for a given process. It is a tedious task to tune the
large number of undefined coefficients present in the empirical-based mod-
els in the process simulator considering the length of the subsequent process
simulation runs.
The matching process is iterative. An exact match is rarely obtained.
Generally there will be slight discrepancies between the structure generated
by the process simulator and the physical fabricated device.

5.8.3  Calibration of Device Simulator

To calibrate a device simulator (ATLAS), the experimental I-V characteristics
of the device obtained are set to best match the output of the DECKBUILD
ATLAS program based on the same device dimension and structure. In
order to obtain a match between the electrical characteristics of a real fab-
ricated device and that with a simulated one, different advanced mobil-
ity models taking care of different scattering along with different doping
profiles and different carrier transport models are analyzed iteratively, as
shown in Figure 5.7.

5.9  Importance of Mesh Optimization

A mesh refers to a collection of volumetric elements whose union defines
the interior and exterior of the device. The large number of small surface
mesh elements allows finer geometrical resolution resulting in more accu-
rate simulation.
Device Simulation Using Silvaco ATLAS Tool 205

Experimental Data
from Real
Fabricated MOSFET
Devices

TCAD TCAD Extract

Match?
Program Simulator Yes Parameters

No
Change Structure or
Circuit
Change Materials or
Simulation
Change Physical Models

FIGURE 5.7
Method for calibration.

In ATLAS, advanced nonlinear iterative solvers are employed for numeri-

cal solution of PDEs. Higher accuracy is correlated with the large number
of nodes obtained from a dense mesh, but the tradeoff is between a lon-
ger elapsed time and memory. In order to obtain the desired accuracy and
efficiency of solution, the mesh structure should be optimized. Very dense
mesh is used in the region of interest of the device structure where the gra-
dient of impurity and potential and current density is high. For example, in
a MOSFET, very dense mesh is used in the channel region under the gate-
oxide interface and in the drain region where electric field is the highest. The
tradeoff between the requirement of accuracy and computational time (com-
plexity) dominated by the specification of the mesh structure causes prob-
lems for users. This problem always causes a dilemma for users. The time
needed to complete a simulation run is roughly proportional to Na, where
N is the number of nodes (grid points) and a is a constant that varies from 2
to 3 depending upon the complexity of the problem. Unfortunately, the size
of the device pushes the number of nodes used close to 20,000—the maxi-
mum number of nodes permitted by ATLAS. The meshing procedure is thus
extremely relevant to the way nodes are distributed throughout the device.
ATLAS uses triangular meshes. It is shown that although optimal mesh gen-
eration is not exactly deterministic, guidelines and heuristics for defining
satisfactory meshes with good triangulation scheme yield better results [30].

5.9.1  Strategy to Obtain a Satisfactory Mesh

1. Generate enough points to provide the required accuracy.
2. Do not generate many unnecessary points that impair accuracy.
3. Minimize or avoid generation of obtuse triangles and long, thin tri-
angles which tends to impair accuracy, convergence, and robustness.
206 Technology Computer Aided Design: Simulation for VLSI MOSFET

4. Transition from a region with larger-sized triangles to a region with

small triangles must be smooth (i.e., avoid abrupt discontinuity).
5. Generate dense mesh in critical areas where the movements of electrons
and holes are rapid in order to prevent information loss and accuracy.
6. Use coarse mesh density for non-critical areas.
7. For a symmetrical structure, simulators allow simulation of one-half
of the structure and then reflection of the results on the other half to
save computational time and memory.

5.9.2  Mesh Re-Gridding

Re-gridding is used for refinement of regions of the initial/base mesh
according to some specified criterion. If the value of the specified solution
variable (such as carrier concentration, doping concentration, electric field,
etc.) exceeds a certain value or when the change in the value within a mesh
triangle exceeds a certain value, then mesh refinement will take place.
ATLAS supports mesh re-gridding based upon doping or a wide range of
suitable solution variables as the basis for mesh refinement. Regrid algo-
rithms will search for the triangle that satisfies the criteria specified for
refinement. Once they are identified, those triangles will be divided into
four congruent sub-triangles. Grid solution quantities (electric field poten-
tial, carrier concentration, etc.) are interpolated into the new nodes using
linear or logarithmic interpolation. The initial or base mesh is referred to
as “level 0,” and new triangles are referred to as “level 1.” After all level
0 triangles are examined, level 1 triangles will be examined by the same
procedure. Therefore, sub-triangles of level 1 become level 2 triangles.
This process continues until no more triangles meet the refinement cri-
terion. It is possible to specify the “maximum level” which is the limit-
ing factor for amount of refinement and size of the grid after refinement.
Re-gridding can produce obtuse triangles causing inaccurate results.
Therefore, smoothing should be performed on both the initial grids and
subsequent re-grids.

5.10 Introduction to Other Tools from Silvaco

Used in Conjunction with ATLAS
Virtual Wafer Fab (VWF) is a suite of software programs used to create
a multifunctional environment for the simulation of semiconductor
technology. VWF of Silvaco allows cost and yield estimation as well
as comprehensive parametric analysis of semiconductor processing
Device Simulation Using Silvaco ATLAS Tool 207

by integrating process simulation, device simulation, and para­

meter extraction within an interactive graphical user-friendly inter-
face. ATLAS can be used as a stand-alone or as a core tool in a VWF
environment.
DECKBUILD is the software to run the code and provides the general
input and output interface for Silvaco (for all TCAD modules) for
changing and altering the code. ATLAS works in conjunction with
DECKBUILD. The top half of the DECKBUILD window is the com-
mand input listed in the form of a program created by a text edi-
tor. The bottom half of the DECKBUILD window is where program
execution and “extract” information is listed as the program runs
and the execution/results are displayed.
DEVEDIT is a program that allows for structure editing, structure
specification, and grid generation graphically by drawing on the
screen. All of Silvaco’s programs use a mesh or grid. Mesh or grid
is used to determine the level of detailing the simulation will gen-
erate in a specific area of the device. Therefore, it allows users to
cut down the simulation time by removing detailing from areas
with less interest containing uniform or no reaction to change/
alter simulation results. The creation of these meshes is the main
function of DEVEDIT; however, it is also used for the editing and
specification of two- and three-dimensional devices created with
the VWF tools.
TonyPlot is the graphical plotting program used to plot the data
extracted from the simulation using ATLAS. Simulation results
do not automatically load into TonyPlot when a simulation is
complete. Users have to save results into a file that can be opened
directly from TonyPlot. The data can be plotted as desired by the
user either in 1D x-y data, 2D contour data, Smith charts, or polar
charts. Measured data can also be imported and plotted in the
above-mentioned types. The overlay feature helps in comparing
the multiple simulation runs. It annotates plots to create meaning-
ful figures for reports and presentations. It enables 2D structure
plots to be cut by multiple, independently controlled 1D slices.
It supports plotting of user-defined equations with the variables
being either electrical data (e.g., drain current) or physical param-
eters (e.g., electric field).
S-Pisces and Blaze are two primary simulators used for silicon device
and advanced heterojunction devices, respectively. In addition, there
are other simulators like Giga, MixedMode, ESD, TFT, Luminous,
and LASER to supplement available process and device simulators
with specialized capabilities. Giga supports non-isothermal calcula-
tions. ESD provides the simulation of electrostatic discharge phe-
nomenon. TFT provides the support for simulation of devices with
208 Technology Computer Aided Design: Simulation for VLSI MOSFET

amorphous and polycrystalline materials. MixedMode provides the

ability to simulate circuits using a combination of SPICE models and
ATLAS devices. Luminous and Laser support general optoelectronic
and semiconductor laser devices, respectively.
Mixed-mode simulations with mesh-based device structures within
a circuit defined by SPICE models are also supported in order to
enhance the capability. For the transient mode of simulation, the
device properties are re-solved at any increment of time. In addition
to the device design, the mixed device/circuit simulation environ-
ment allows users to evaluate the device performance in a real circuit,
and there is no limitation as to whether a compact model ever exists
or not for the device under test. By examining the simulation results
for the new structure, designers can make tradeoffs among design
parameters to achieve optimal device characteristics. MIXEDMODE
is a circuit simulator of Silvaco to provide mixed-mode circuit simu-
lation of multiple device structures simulated using device simula-
tion and compact circuit models.
Device 3D, INTERCONNECT3D, and THERMAL3D provide support
for three-dimensional device capabilities for three-dimensional
simulation, parasitic extraction, and three-dimensional thermal
analysis.

5.10.1  Process Simulation Tools

Semiconductor process simulation involves the numerical solution of
equations describing the physics of dopant diffusion, silicon oxidation,
lithography, ion implantation, etching, and deposition steps resulting in
geometry and doping profiles that define a device. A number of programs
each specialized to solve a specific set of equations are used to simulate the
entire process flow. However, the various programs use different solution
strategies.
ATHENA is a framework program that integrates several smaller pro-
grams into a more complete process simulation tool. This program focuses
upon the simulation of fabrication processes. In ATHENA, devices are cre-
ated through simulation of the fabrication process. To optimize the device
characteristics, changes in process parameters supplied to the ATHENA
process simulator environment are required, as certain process parameters
change the device characteristics. ATHENA consists of four primary and
several secondary tools. The primary tools are SSuprem4 for simulating ion
implantation, diffusion, oxidation, and silicidation process for silicon; Flash
for simulating implantation and diffusion for advanced materials; Elite for
topography simulation; and Optolith for lithography simulation. ATHENA
also provides options for modeling silicides, Monte Carlo modeling of ion
implantation, etc.
Device Simulation Using Silvaco ATLAS Tool 209

5.10.2  ATHENA and ATLAS

ATLAS is very often used in conjunction with the ATHENA process simu-
lator to take advantage of the automatic interface between them. ATHENA
predicts the physical structures that result from the processing steps. The
resulting physical structures are used as input by ATLAS, which then predicts
the electrical characteristics for a particular bias. Therefore, it is possible to
determine the effect of process parameters on device characteristics by the
combination of ATHENA and ATLAS. However, it is much more difficult to
control the actual device parameters and its operation in the ATHENA pro-
cess simulator environment in comparison to the ATLAS device simulator
environment. It is possible to precisely control the device structure, materi-
als, and doping concentrations in specific regions through the given code
syntax in ATLAS. However, a change in the individual process parameter
affects the entire structure of the device in ATHENA, which makes a device
constructed in ATHENA more difficult to characterize. However, a device
realized in ATHENA is much closer to a true fabricated transistor.

5.11  Example 1: Bulk n-Channel MOSFET Simulation

Figure 5.8 shows the schematic cross-sectional diagram of an n-channel bulk
MOSFET with channel length L = 80 nm, oxide thickness tOX = 2 nm, junction

Source Gate Drain

2 nm
30 nm

n+ n+

50 nm 80 nm 50 nm
70 nm

P-type
substrate

FIGURE 5.8
An n-channel bulk MOSFET.
210 Technology Computer Aided Design: Simulation for VLSI MOSFET

depth Xj = 30 nm, n+ source/drain having uniform doping concentration 1020

cm–3, and with a p-type substrate doping of 1018 cm–3. To simulate this device
using ATLAS, the following steps are required. The ATLAS program code
provided in the text demonstrates the use of these steps to simulate the device.

Step 1: Generate the device structure file using ATHENA/Atlas/

DEVEDIT.
1.1: simulator specification
1.2: mesh definition
1.3: region definition
1.4: electrode specification
1.5: doping specification
1.6: contact specification

Step 2: Set the material model.

Step 3: Set the method used to do the calculation.
Step 4: Obtain the initial solution.
Step 5: Run the simulator to obtain a solution for a different bias condition.
Step 6: Display the results.

5.11.1  Program for Bulk n-Channel MOSFET Simulation

# Program to simulate n-channel bulk MOSFET
# In DECKBUILD # indicates a comment line, not a part of the program.
# Step 1: Generate the device structure
# 1.1 simulator specification
go atlas

# 1.2 mesh definition

mesh space.mult=1.0

# mesh definition in x direction

# loc stands for location, specifying the location of the grid
line
x.mesh loc=0.00 spac=0.01
# spac stands for spacing, specifying mesh spacing at a given
location
x.mesh loc=0.05 spac=0.001
x.mesh loc=0.09 spac=0.004
x.mesh loc=0.13 spac=0.001
x.mesh loc=0.18 spac=0.01

# mesh definition in y direction

y.mesh loc=-0.002 spac=0.0005
Device Simulation Using Silvaco ATLAS Tool 211

y.mesh loc=0 spac=0.0004

y.mesh loc=0.03 spac=0.008
y.mesh loc=0.10 spac=0.01

# 1.3 region definition

region num=1 y.min=0 silicon
region num=2 y.max=0 oxide

# 1.4 electrode declaration

electrode name=gate number=1 x.min=0.05 x.max=0.13 top
electrode name=source number=2 left length=0.05 y.min=0 y.max=0
electrode name=drain number=3 right length=0.05 y.min=0 y.max=0
electrode name=substrate number=4 bottom

# 1.5 doping specification of distribution, type

doping uniform conc=2e18 p.type region=1
doping uniform conc=1e20 n.type x.left=0 x.right=0.05 y.min=0
y.max=0.03
doping uniform conc=1e20 n.type x.left=0.13 x.right=0.18
y.min=0 y.max=0.03

# 1.6 contact specification

# n.poly sets n+ doped polysilicon as contact material with
workfuction=4.17eV
contact name=gate n.poly
contact name=source neutral
contact name=drain neutral
contact name=substrate neutral

#Step 2: Set the material model

models mos print

#Step 3: Set the specific method used to do the calculation

method newton trap

#Step 4: generate initial solution at zero bias

solve init

#Step 5: Run the simulator to obtain solution for different

bias condition
#solution for different drain bias
solve vdrain=0.1 outf=solve_vdrain1
solve vdrain=0.2 outf=solve_vdrain2
solve vdrain=0.3 outf=solve_vdrain3
solve vdrain=0.4 outf=solve_vdrain4

# ramp gate bias with a specific drain bias solution

load infile=solve_vdrain1
212 Technology Computer Aided Design: Simulation for VLSI MOSFET

#output the result in a specific log file

log outf=gate1.log
solve name=gate vgate=0 vfinal=1.2 vstep=0.1

load infile=solve_vdrain2
log outf=gate2.log
solve name=gate vgate=0 vfinal=1.2 vstep=0.1

load infile=solve_vdrain3
log outf=gate3.log
solve name=gate vgate=0 vfinal=1.2 vstep=0.1

load infile=solve_vdrain4
log outf=gate4.log
solve name=gate vgate=0 vfinal=1.2 vstep=0.1

#Step 6: Display the results

# display all the log files overlaid together
tonyplot -overlay gate1.log gate2.log gate3.log gate4.log
quit

5.11.2 Simulation Results

Figure 5.9 shows the simulated Id – Vgs characteristics for the MOSFET device
structure shown in Figure 5.8 with drain bias 0.1, 0.2, 0.3, and 0.4 V.

6.0×10–4

Vds = 0.1 V
5.0×10–4
Vds = 0.2 V
Vds = 0.3 V
Drain Current Ids in [A]

4.0×10–4 Vds = 0.4 V

3.0×10–4

2.0×10–4

1.0×10–4

0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate-to-source Voltage Vgs in [V]

FIGURE 5.9
Id – Vgs characteristics of a bulk n-channel MOSFET with channel length L = 80 nm, tOX = 2 nm.
Device Simulation Using Silvaco ATLAS Tool 213

5.12 Example 2: Silicon-on-Insulator
(SOI) MOSFET Simulation
A fully depleted silicon-on-insulator (SOI) device is a silicon-based device
built upon a thick SiO2 layer as an insulating substrate that starts at or
within the depletion layer. SOI technology appears as an interesting alterna-
tive to standard planar bulk devices [31,32]. This thick silicon dioxide layer
is also known as the buried oxide (BOX) layer. The silicon layer above the
BOX is where the device is fabricated. A fully depleted SOI device offers
many advantages over bulk silicon MOSFETs, like reduction in junction
capacitances between drain (source) and body, decrease in leakage currents,
improvement in cross-talk immunity [33], low level of dielectric loss with
high resistivity SOI substrates important for radio frequency (RF) applica-
tions [34], and higher immunity to radiation effects. The SOI structure not
only kills the latch-up and improves digital error immunity, but it also allows
for better control of the channel, leading to an improved subthreshold slope
and lower short-channel effects. However, the SOI circuits suffer from sev-
eral dynamic floating body effects [35]. In this example, a simplified version
of the SOI MOSFET device is created using ATLAS with a facility to vary
parameters like gate length, doping, etc., easily. To perform this simulation,
the main Silvaco tools used are DECKBUILD, ATLAS, and TONYPLOT. The
following text illustrates the use of the commands with required explana-
tions to complete the device simulation.

5.12.1  Program Description for SOI MOSFET Simulation

Step 1: Declare and initialize variables used.
Variables are useful for ease of changing certain parameters when
a code is being run multiple times with different values. For a new
design, only the values declared with a set command need to be altered.

# Program for SOI Device Simulation

# To open ATLAS in DECKBUILD
go atlas

#location of the midpoint of the silicon thickness i.e. sMp=tSi/2

set sMp=0.0125

#location of the bottom of the silicon thickness i.e. sTsi=tSi

set sTsi=0.025

#location of the end of the bottom oxide layer thickness

set sToxb=0.1
214 Technology Computer Aided Design: Simulation for VLSI MOSFET

# location of the start of the front (gate) oxide layer thickness

set sToxf=-0.002

# minimum x location of gate electrode

set gmin=1

# maximum x location of gate electrode

set gmax=2

Step 2: Define the mesh to construct the structure.

The first step in defining the structure of a SOI device is to set the
mesh with a larger number of points in the areas of interest. The first
mesh command must be the mesh space multiplier command. This
command will tell ATLAS the scaling factor of the mesh. In this
case, the device is rectangular, not cylindrical. The default mesh
symmetry is rectangular. To specify cylindrical symmetry, a cylin-
drical parameter must be appended in the first mesh statement.
The mesh will be less dense for a large number and more dense for
a smaller number. The value for this is normally set to equal 1. Mesh
statements are entered in as vertical and horizontal lines in microns
and as distance from the center line. ATLAS divides the grid using a
triangle format. The user can use a dense mesh density in the region of
interest.

mesh space.mult=1.0

# mesh definition in x direction

x.mesh loc=0.00 spac=0.50
x.mesh loc=1.15 spac=0.02
x.mesh loc=1.5 spac=0.1
x.mesh loc=1.85 spac=0.02
x.mesh loc=3 spac=0.5

# mesh definition in y direction

y.mesh loc=$sToxf spac=0.02
y.mesh loc=0.00 spac=0.005
y.mesh loc=$sMp spac=0.02
y.mesh loc=$sTsi spac=0.01
y.mesh loc=$sToxb spac=0.25

Step 3: Define the regions with different numbers and correspond-

ing locations.
After defining the mesh structure, it is necessary to define the
regions. For this example of SOI MOSFET, three regions are to be
defined: (1) gate oxide layer for insulating gate contact, (2) silicon
region with thickness tSi, and (3) buried oxide (BOX).
Device Simulation Using Silvaco ATLAS Tool 215

The regions will be used to assign materials and properties to the

device. The regions must be defined along the mesh lines, and the
statements will be similar to those used for the mesh states. ATLAS
allows the user to define up to 200 different regions for one device.
If the designer overlaps any of the two regions, ATLAS will assign
the material type to the last region that was defined. The entire two-
dimensional mesh area must be defined into regions or ATLAS will
not run successfully.

# region definition
region number=1 x.min=0 x.max=3 y.min=$sToxf y.max=0
material=Oxide
region number=2 x.min=0 x.max=3 y.min=0 y.max=$sTsi
material=Silicon
region number=3 x.min=0 x.max=3 y.min=$sTsi y.max=$sToxb
material=Oxide

Step 4: Define the names of each electrode with corresponding location.

The electrodes are to be defined in order to tell the program about
the location of the metal contacts like gate, source, and drain. One
can observe the dissimilarities between the fabrication process and
ATLAS program because the top oxide layer and the electrodes are
defined before the silicon is doped. ATLAS requires the structure
to be defined in this order in order to achieve easier calculation.
Because the gate electrode is above the top oxide layer, both the y.min
and y.max values can be set to sToxf (–0.002), which will put it above
the oxide layer, but with no thickness. Similarly, the substrate elec-
trode is located below the bottom oxide layer.
# electrode definition
electrode name=gate number=1 x.min=$gmin x.max=$gmax
y.min=$sToxf y.max=$sToxf
electrode name=source number=2 x.min=0 x.max=0.5 y.min=0 y.max=0
electrode name=drain number=3 x.min=2.5 x.max=3 y.min=0 y.max=0
electrode name=substrate number=4 x.min=0 x.max=3 y.min=$sToxb
y.max=$sToxb

Step 5: Set the contact and interface properties.

The command “contact” is used to tell ATLAS how to treat the
electrode. In the default condition, an electrode in contact is assumed
to be ohmic. If the designer wants the electrode to be treated like
a Schottky contact, the design must use the workfunction. The gate
contact material is set to n+ doped polysilicon by the n.poly parame-
ter. In another approach, instead of using the material name (n.poly)
required, workfunction can be mentioned by setting the workfunc-
tion parameter to the required value. For example, the statement
“contact name=gate workfunction=4.17” is equivalent to the
216 Technology Computer Aided Design: Simulation for VLSI MOSFET

statement “contact name=gate n.poly” because the workfunc-

tion of n+ polysilicon equals 4.17 eV.
The fabrication process, no matter how well controlled, intro-
duces interface states at the SiO2-Si interface, which critically
affects the electrical characteristics of the device. Interface states,
whether inherent, process related, or operationally generated, were
found to cause degradation in device parameters such as trans-
conductance, carrier mobility, and threshold voltage and to gener-
ally reduce device reliability and lifetime [36,37]. The “interface”
statement is used to define the interface charge density interfaces
between semiconductors and insulators. It indicates that all inter-
faces between semiconductors and oxide have a fixed charge of 3 ×
1010 C/cm2 [37].
contact name=gate n.poly
interface qf=3e10
contact name=source neutral
contact name=drain neutral
contact name=substrate neutral

Step 6: Define doping in the MOSFET structure.

The next action, doping, is one of the most important actions a
designer does to affect the electrical properties of the structure
being designed. Silvaco allows the designer to specify the type of
dopant and the concentration. It also allows the designer to specify
the distribution of the doping material. ATLAS has the ability to
distribute the dopants in a uniform, analytical Gaussian, or other
supported profiles. For this device, all the doping will be defined in
region 2, where the silicon is located. Initially a p-type uniformly
distributed doping is specified in the whole region 2. It is followed
by a Gaussian distribution n-type doping specification targeting
the source and the drain region of the structure. The concentra-
tion listed in the command for Gaussian doping in the source and
the drain will have the peak concentration = 1 × 1020 cm–3 at y =
0 and the characteristics = 0.05 which is the principal characteris-
tic length of the implant (standard deviation) for which the doping
level will drop off in a vertical direction. The lateral fall-off outside
the x-coordinates mentioned in the doping statement is defined by
the lat.char parameter.

# p-type doping with a uniform concentration throughout all of

the silicon doping uniform conc=2e17 p.type direction=y regions=2

# Gaussain doping profile in the source

doping gaussian characteristic =.05 conc=1e20 n.type x.left=0
x.right=$gmin y.top=0 lat.char=0.05 direction=y
Device Simulation Using Silvaco ATLAS Tool 217

# Gaussain doping profile in the drain

doping gaussian characteristic =.05 conc=1e20 n.type
x.left=$gmax x.right=3 y.top=0 lat.char =.05 direction=y

Step 7: Save and display the structure file.

The “master” after the name of the out file specifies that the output
file needs to be written as a standard structure file instead of binary
format. The generated MOSFET structure can be visualized with the
help of TonyPlot.
struct outf=SOI.str master
tonyplot SOI.str

Step 8: Select the models used in this simulation.

In this simulation, for mobility standard concentration dependent
(conmob) and parallel field dependent mobility (fldmob) to model, the
velocity saturation effect is chosen. For carrier statistics, Fermi-Dirac
and band-gap narrowing (bgn) are chosen. The parameters evsatmod
and hvsatmod with b.electrons and b.holes supplied are used to select a
particular field-dependent equation to be used. Carrier generation and
recombination are the processes by which the semiconductor material
is moved away from thermal equilibrium and returned to equilibrium
after being disturbed from it. For recombination Shockley-Read-Hall
(SRH) and Auger recombination models are chosen.
In the presence of heavy doping (greater than 1018cm–3), the
p-n product in silicon becomes doping dependent [38]. As dop-
ing increases, the band gap decreases, where the conduction band
decreases the same amount as the valence band is raised. This fea-
ture is considered by using the model “BGN” (band-gap narrowing).
# model specification
models auger srh conmob fldmob b.electrons=2 b.holes=1 evsat-
mod=0 hvsatmod=0 bgn temperature=300

Step 9: Define the numerical methods.

The Newton method is chosen with a maximum number of itera-
tion equal to 25. To overcome the problem with diverging solution
with a poor initial guess, a “trap” statement is used, where maxtrap
is the maximum allowed number of trials (default = 4) with the
bias step reduced by the factor supplied in the parameter known as
atrap. To enhance the performance for slow convergence, a variant
of Newton’s method known as the Newton-Richardson method is
enabled by the autonr parameter.
# method specification
method newton itlimit=25 trap atrap=0.5 maxtrap=4 autonr
218 Technology Computer Aided Design: Simulation for VLSI MOSFET

Step 10: Solve for specified bias.

The initial guesses for potential and carrier concentrations must
be made from the doping profile at zero bias by using the “solve
init” statement, when no previous solutions are available. If the user
omits this statement, ATLAS automatically evaluates this before exe-
cuting the first “solve” statement.
It is most difficult to obtain good convergence for the first two non-
zero solve statements because they use solution at zero bias provided
by the “solve init” statement as a poor initial guess. This is why the
first two non-zero solve statements should use small voltage steps.
However, once their solutions are obtained, by the use of the projec-
tion algorithm, the remaining solve statements obtain a good initial
guess, resulting in good convergence.

# Set the initial values and solve

# solve the device for zero bias
solve init
# solve for drain bias with 0.01 then 0.05 to finally to 0.1
# first two non-zero solve statements are given small bias step
solve vdrain=0.01
solve vdrain=0.02
solve vdrain=0.1

# Extraction of Id-Vds characteristics or different Vgs

solve vgate=1.0 outf=solve_vgate1
solve vgate=1.5 outf=solve_vgate2
solve vgate=2.0 outf=solve_vgate3
solve vgate=2.5 outf=solve_vgate4

load infile=solve_vgate1
log outf=SOI11.log
solve name=drain vdrain=0 vfinal=2.0 vstep=0.1

load infile=solve_vgate2
log outf=SOI21.log
solve name=drain vdrain=0 vfinal=2.0 vstep=0.1

load infile=solve_vgate3
log outf=SOI31.log
solve name=drain vdrain=0 vfinal=2.0 vstep=0.1

load infile=solve_vgate4
log outf=SOI41.log
solve name=drain vdrain=0 vfinal=2.0 vstep=0.1
Device Simulation Using Silvaco ATLAS Tool 219

Source Gate Drain

2.0 nm
25 nm

100 nm
n+ n+
100 nm 100 nm
65 nm

Buried Oxide

FIGURE 5.10
Cross-sectional diagram of a fully depleted n-channel SOI MOSFET.

Step 11: Display the output characteristics.

# plot of the log files overlaid together

tonyplot -overlay SOI11.log SOI21.log SOI31.log SOI41.log
# denotes end of the program
quit

5.12.2 Simulation Results

Figure 5.11 shows the simulated Id-Vds characteristics for the n-channel fully
depleted SOI MOSFET device structure displayed in Figure 5.10 for gate bias
1.0, 1.5, 2.0, and 2.5 V, respectively.

5.13 Example 3: 0.18 µm Bulk nMOS

Transistor with Halo Implant
The device used for this simulation is a LDD 0.18 µm [39] n-channel MOSFET.
The device is fabricated using silicon with a <100> orientation. The p-type
substrate is formed by doping with 3 × 1013 atoms/cm3 of boron. The n– region
is formed by implanting a dose of 1015 atoms/cm3, and the n+ region is formed
by implanting 5 × 1015 atoms/cm3 of arsenic. The program starts with a mesh
definition. The mesh is defined for one-half of the symmetric MOSFET struc-
ture. After all the process fabrication steps, the structure will be mirrored
220 Technology Computer Aided Design: Simulation for VLSI MOSFET

1.4×10–3
Vgs = 1.0 V
1.2×10–3 Vgs = 1.5 V
Vgs = 2.0 V
Drain Current Ids in [A]

1.0×10–3 Vgs = 2.5 V

8.0×10–4

6.0×10–4

4.0×10–4

2.0×10–4

0.0
0.0 0.4 0.8 1.2 1.6 2.0
Drain-to-source Voltage Vds in [V]

FIGURE 5.11
Plot of drain current Ids as a function of drain-to-source voltage Vds for gate-to-source voltage
Vgs = 1.0 V, 1.5 V, 2.0 V, and 2.5 V, respectively, obtained by simulation for an n-channel fully
depleted SOI MOSFET.

to generate full MOSFET structure. The different steps performed to simu-

late the fabrication of n-channel MOSFET followed by extraction of different
MOSFET parameters of it are described below. The status of the MOSFET
structure and the effect of every successive process step can be visualized by
inserting a command for plotting the structure (tonyplot structure_name.
str) after every step described below.

5.13.1  Program for 0.18 µm Bulk nMOS

Step 1: Provide mesh definition and structure declaration.

# start process simulator ATHENA

go Athena

# Define mesh for x-plane

line x loc=0.15 spac=0.1
line x loc=0.2 spac=0.006
line x loc=0.4 spac=0.006
line x loc=0.6 spac=0.01

# Define mesh for y-plane

line y loc=0.0 spac=0.002
line y loc=0.2 spac=0.005
Device Simulation Using Silvaco ATLAS Tool 221

line y loc=0.5 spac=0.05

line y loc=0.8 spac=0.15

# structure declaration
struct outfile=nmos_bulk.str

Step 2: Initialize silicon substrate of crystal orientation 100 with 1.0 ×

1015/cm3 boron dopant added. A space multiplier (Space.mult = 2) is
used to speed up the process. Decrease the space multiplier param-
eter to obtain a denser mesh with more accuracy.

init orientation=100 c.boron=1.0e15 space.mul=2

Step 3: Grow a smooth thin layer of SiO2 of depth 10 to 15 nm on the sub-

strate to reduce the channeling effect and to prevent contamination
of the substrate. The simplest deposit method in ATHENA is confor-
mal deposition. It is used when the exact shape of the deposited layer
is not critical. Dry oxidation is performed for 30 minutes at 1000°C.
Then etch to obtain a uniform blanket of oxide of 0.02 µm thick.

diffus time=30 temp=1000 dryo2 press=1.00 hcl=3

etch oxide thick=0.02

Step 4: Use the default dual Pearson model to choose a boron implant
with a dose of 8.0 × 1012 ions/cm2 with energy 100 keV. An n-channel
MOS transistor must be developed on p-type silicon as this material
under the gate must be inverted. Therefore, the next step is implanta-
tion of boron to create a p-well in the substrate. The nMOS fabrica-
tion could have started with an initial p-type substrate, but p-well
implantation reviewed here is common in industry. ATHENA offers
three different models for ion implantation [40]: (1) dual Pearson
(default), (2) single Pearson, and (3) Monte Carlo.

implant boron dose=3.0e13 energy=200 pearson

Step 5: Move and settle the boron atoms. As a result of the ion implan-
tation step, the net doping peaks at an average penetration depth
with a specific doping concentration. In order to enhance the doping
uniformity, the substrate is heated to high temperatures so that the
boron atoms are given enough energy to move and settle more uni-
formly in the substrate. As a result of this heating in the presence of
oxygen, an oxide is formed. Wet oxidation is used.

diffus temp=950 time=100 weto2 hcl=3

222 Technology Computer Aided Design: Simulation for VLSI MOSFET

Step 6: Further propel the p-well into the substrate and increase the
doping uniformity by performing more diffusion steps with vary-
ing temperatures, temperature change rates, and processing envi-
ronments known as welldrive.
diffus time=50 temp=1000 t.rate=4.000 dryo2 press=0.10 hcl=3
diffus time=220 temp=1200 nitro press=1
diffus time=90 temp=1200 t.rate=-4.444 nitro press=1

Step 7: Etch all present oxide layers in order to obtain a surface on which
to begin the process of defining physical MOSFET parameters.

etch oxide all

Step 8: Perform sacrificial cleaning in order to ensure that the surface is

free from damage due to previous fabrication steps. In this process,
a thin layer of silicon is sacrificed by first oxidation and then removal
of the oxide produced.

diffus time=20 temp=1000 dryo2 press=1 hcl=3

etch oxide all

Step 9: Perform deposition of gate oxide by dry oxidation, with the

thickness of the gate oxide playing a major role in determining the
MOSFET characteristics that can be altered by controlling time and
temperature.

diffus time=3 temp=895 dryo2 press=1.00 hcl=1

Step 10: Define the threshold voltage by implanting boron through the
gate oxide. A higher dose of boron implant will lead to higher thresh-
old voltage because it will be more difficult to invert the p-channel.

implant boron dose=1.5e13 energy=45 pearson

Step 11: Use conformal deposition of polysilicon to create the gate.

depo poly thick=0.2 divi=10

Step 12: Begin patterning of the polysilicon gate by etching 0.35 µm

from the left side.

etch poly left p1.x=0.51

Step 13: Perform implantation through the deposited gate oxide layer t
from the light drain/source.
Device Simulation Using Silvaco ATLAS Tool 223

method fermi compress

diffuse time=5 temp=900 weto press=0.8
implant arsenic dose=1.0e15 energy=30 pearson

Step 14: Implant p-doped halo (NMOS).

implant boron dose=3.0e13 energy=15 tilt=30 fullrotat

Step 15: Form an oxide spacer to provide a barrier of isolation and to

aide in patterning for the next implantation.

depo oxide thick=0.10 divisions=8

etch oxide dry thick=0.10

Step 16: Form the heavy drain/source region by implantation with arse-
nic instead of phosphorus as in the case of the light drain/source.

implant arsenic dose=5e15 energy=60 pearson

Step 17: Perform annealing in the presence of nitrogen to diffuse the

drain/source created.

method fermi compress

diffuse time=1 temp=1000 nitro press=1.0

Step 18: Etch the oxide layer above the drain/source region to pattern
the source/drain contact metal.

etch oxide left p1.x=0.35

Step 19: Deposit aluminum to create electrodes with a low ohmic contact.

deposit alumin thick=0.03 divi=2

Step 20: Etch away unwanted materials.

etch alumin right p1.x=0.33

Step 21: Mirror the structure to obtain the full symmetrical device.

structure mirror right

Step 22: Define the electrodes and save the obtained structure.

electrode name=gate x=0.59 y=0.1

electrode name=source x=0.2
224 Technology Computer Aided Design: Simulation for VLSI MOSFET

electrode name=drain x=1.0

electrode name=substrate backside
save outfile=nmos_bulk.str

Step 23: Extract different MOSFET parameters and plot the structure.

# to extract gate oxide thickness

extract name=“gateox” thickness oxide mat.occno=1 x.val=0.59

# extract final S/D junction depth Xj

extract name=“nxj” xj silicon mat.occno=1 x.val=0.2 junc.
occno=1

# extract the N++ regions sheet resistance...

extract name=“n++ sheet rho” sheet.res material=“Silicon” mat.
occno=1 x.val=0.2 region.occno=1

# extract the sheet rho under the spacer, of the LDD region...
extract name=“ldd sheet rho” sheet.res material=“Silicon” mat.
occno=1 x.val=0.49 region.occno=1

# extract the surface conc under the channel....

extract name=“chan surf conc” surf.conc impurity=“Net Doping”
material=“Silicon” mat.occno=1 x.val=0.6

# potting the structure

tonyplot nmos_bulk.str

The program to extract different parameters, threshold voltage, and Ids-Vgs

characterization using the structure generated with ATHENA code is described
above. The threshold voltage is extracted by finding the intersection of the maxi-
mum slope of the Ids-Vgs curve with the x-axis. The output of the extract com-
mand will appear in the lower DECKBUILD window after running the code.

go atlas
# IMPORT THE structure to use the auto-interface between
ATHENA and ATLAS
mesh inf=nmos_bulk.str

# model definition
models cvt srh numcarr=2

# method specifiatiion
method newton itlimit=25 trap atrap=0.5 maxtrap=4 autonr
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25

#solve for id-vgs by ramping gate voltage and store the answer
in the log file
Device Simulation Using Silvaco ATLAS Tool 225

solve init
solve vdrain=0.1
log outf=bulkHalo.log master
solve name=gate vgate=0.1 vfinal=1.5 vstep=0.1

# plot the log file

tonyplot bulkHalo.log

# extraction of threshold voltage

extract name=“vt” (xintercept(maxslope(curve(abs(v.”gate”),abs
(i.”drain”)))) - abs(ave(v.”drain”))/2.0)
quit

5.13.2  Simulation Results

Figure 5.12 shows the Ids-Vgs characteristics of an n-channel MOSFET simu-
lated using program 5.13.1 for two different devices. One of them is a pock-
eted device that considers the halo implantation process step, and the other
is a non-pocketed device that omits the halo implantation process step. A
process called pocket implant or halo implant is introduced in which the locally
high doping concentration in the channel near the source/drain junctions
is created. The technology has been given prominence to tailor the short-
channel performances of diminuend devices. Therefore, it is widely used to
reduce threshold voltage roll-off and punch-through [41–46].

0.00008
With halo implant
Drain Current Ids in [A] Shown in Linear Scale
Drain Current Ids in [A] Shown in Log Scale

Without halo implant

1E–6
0.00006

1E–9
0.00004

1E–12
0.00002

1E–15
0.00000

1E–18
0.2 0.4 0.6 0.8 1.0 1.2 1.4
Gate-to-source Voltage Vgs in [V]

FIGURE 5.12
Simulation data of the drain–current Ids versus the gate–source voltage Vgs for devices with and
without halo implantation.
226 Technology Computer Aided Design: Simulation for VLSI MOSFET

A highly doped halo surrounding either the source or drain proves to be

effective in increasing switching speed by more than a factor of two over the
conventional MOSFET [47]. It reduces leakage current and, hence, reduces
static power dissipation [48]. However, careful tuning of pocket implant
parameters in order to obtain desired electrical performance of nano-
MOSFETs is always necessary. Variations of pocket implant energy, implant
dosage, and tilt angle influence the characteristics of nano-n-MOSFETs
[49,51]. However, careful tradeoffs between minimum channel length and
other device electrical parameters are required.
Figure  5.12 demonstrates an increase of the subthreshold current due to
the drain-induced barrier lowering suffered by the non-pocketed device
compared to the pocketed device. At low gate voltages, the additional poten-
tial barriers created by the pockets are strong enough for controlling the cur-
rent, resulting in a comparative lower current for halo-doped MOSFETs in
the subthreshold region.

5.14 Example 4: Volume Inversion Double-Gate (DG) MOSFET

As CMOS scaling is approaching its limits, DG MOSFET is becoming a very
promising solution for the fabrication of high-performance devices for low-
power applications [35].
A DG MOSFET is considered electrostatically superior (channel is con-
trolled by the gate voltage, not by the drain to source voltage) compared
to single-gate MOSFET due to its strong coupling between the conduction
channel and gate electrodes.
The use of symmetric DG MOSFET allows the suppressing of short-chan-
nel effects like drain-induced barrier lowering (DIBL) and subthreshold
slope degradation, making unnecessary the conventional use of high chan-
nel doping densities and gradients compared to a bulk MOSFET [52,53].
Here symmetric means that the same voltage bias is applied to the two gates
having the same work function. The use of an undoped body [54,55] also
results in enhanced mobility by reducing charged-impurity scattering and
in reduced device parameter variation by eliminating the statistical fluctua-
tion of dopant concentration [56–58]. Therefore, doping of the DG MOSFET is
not desired and is usually not used, but there is always a small unintentional
doping density ~1015 cm–3 during fabrication [59]. Therefore, a lightly doped
DG MOSFET is considered in this simulation.
In this example, ATLAS is used to simulate 50 nm DG n-MOSFET having
abrupt source/drain junctions (i.e., L eff = Lmet = 50 nm [60]). The device param-
eters are as follows: channel width W = 50 nm, channel length L = 50 nm, sili-
con thickness tSi = 20 nm, equivalent gate oxide thickness tox = 2 nm, doping
concentration of the silicon channel NA = 1015 cm–3, doping concentration of
Device Simulation Using Silvaco ATLAS Tool 227

the source/drain contact regions ND = 1020 cm–3, and mid-gap metal gate with
workfunction 4.74 eV.

5.14.1  Program for Structure of DG MOSFET

# Program to generate the structure of DG MOSFET

go atlas
mesh space.mult=1.0

# mesh definition in x direction

x.mesh loc=0.00 spac=0.01
x.mesh loc=0.05 spac=0.001
x.mesh loc=0.075 spac=0.005
x.mesh loc=0.1 spac=0.001

x.mesh loc=0.15 spac=0.01

# mesh definition in y direction
y.mesh loc=-0.002 spac=0.001
y.mesh loc=0 spac=0.0004
y.mesh loc=0.01 spac=0.001
y.mesh loc=0.02 spac=0.0004
y.mesh loc=0.022 spac=0.001

# region definition
region num=1 y.min=0 y.max=0.02 silicon
region num=2 y.min=-0.002 y.max=0 oxide
region num=3 y.min=0.02 y.max=0.022 oxide

# electrode definition
electrode name=gate number=1 x.min=0.05 x.max=0.1 top
electrode name=gate1 number=2 x.min=0.05 x.max=0.1 bottom
electrode name=source number=3 left length=0.05 y.min=0
y.max=0
electrode name=drain number=4 right length=0.05 y.min=0
y.max=0

# doping specification
doping uniform conc=1e15 p.type region=1
doping uniform conc=1e20 n.type x.left=0 x.right=0.05 region=1
doping uniform conc=1e20 n.type x.left=0.1 x.right=0.15
region=1

# save and display the structure

save outfile=dgmos.str
tonyplot dgmos.str
quit

Quantum confinement effects will not be taken into account here, because
silicon film thickness greater than 10 nm [61] and length greater than 10 nm
228 Technology Computer Aided Design: Simulation for VLSI MOSFET

are being considered. Quantum mechanical tunneling from source to drain

(through the barrier) degrades device performance for extreme short length
devices, but for channel lengths longer than about 10 nm, MOSFETs behave
classically [62].
The surface potential ΨS is the most natural variable for the formulation of
MOS device physics. It is defined as the difference between the electrostatic
potential at the SiO2/Si interface and the potential in the neutral bulk region
due to band bending. Recently there has been wide consensus in the com-
pact modeling community that traditional threshold-voltage-based models
have reached the limit of their usefulness and need to be replaced with more
advanced models based on surface potential referred to as surface-potential-
based models, because an accurate physical description of MOSFET can be
easily obtained by the use of surface-potential-based models.

5.14.2  Program to Obtain Potential Variation of DG MOSFET

# Program for obtaining variation of surface and body center
potential

go atlas

# IMPORT THE MESH structure

mesh inf=dgmos.str

# contact specification
contact name=gate n.poly workfunction=4.74
# two separate electrodes gate and gate1 are shorted by
“common” parameter
contact name=gate1 n.poly workfunction=4.74 common=gate
contact name=source neutral
contact name=drain neutral

# model declaration
models auger srh conmob fldmob bgn temperature=300

# method definition
method newton itlimit=25 trap

# solution for specific gate and drain bias

solve init
solve vdrain=0.0
solve vgate=0.0

# saving the structure file

save outf=dg.str

# extraction of surface potential where y.val=0.0

(semiconductor front gate oxide interface) along the depth and
saving the curve in a file
Device Simulation Using Silvaco ATLAS Tool 229

extract name=“srp_profile1” curve(depth, potential

material=“Silicon” mat.occno=1 y.val=0.0) outfile=“extract1.
dat”

# extraction of channel center potential where

y.val=0.01(center of the SOI silicon semiconductor body
y=tSi/2) along the depth and saving the curve in a file
extract name=“srp_profile2” curve(depth, potential
material=“Silicon” mat.occno=1 y.val=0.01) outfile=“extract2.
dat”

# plot the files in the same window overlaid

tonyplot -overlay extract1.dat extract2.dat
quit

5.14.3  Simulation Results

Figure  5.14 shows the variation of surface and channel center potential of
DG MOSFET shown in Figure  5.13 using the simulation of codes listed in
Sections 5.14.1 and 5.14.2. Figure  5.14 portrays the potential with gate and
drain bias equal to zero. However, it is possible to obtain potentials for vari-
ous bias conditions by changing the gate and the drain bias in the program
listed in Section 5.14.2, subjected to convergence of the solution attained.
Figure 5.15 presents the surface potential ΨS and potential at the center of
the channel Ψ0, evaluated for gate voltage varying from 0 V to 1.5 V in steps
of 0.1 V by changing the program for every step change. It is observed that
below threshold, while the semiconductor charge is small, there is volume
inversion, and the potential remains essentially flat (ΨS = Ψ0) throughout the

Source Front gate Drain

2 nm
20 nm

50 nm n+
n+
50 nm 50 nm

2 nm

Back gate

FIGURE 5.13
A fully depleted thin-film DG SOI MOSFET.
230 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.6
Surface potential ΨS
0.5 Channel center potential Ψ0

Vds = 0.0 V, Vgs = 0.0 V

Surface Potential in [V]

0.4

0.3

0.2

0.1

0.0
0 5 10 15 20 25 30 35 40 45 50
Distance along the Channel from Source to Drain in [nm]

FIGURE 5.14
Plot of surface potential and channel center potential versus position along the channel from
source to drain for Vds = 0 V and Vgs = 0 V.

0.6 Vds = 0.0 V

0.5

0.4
Potential in [V]

Crossover
0.3 point

0.2
Surface potential ΨS
0.1 Channel center potential Ψ0

0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Gate-to-source Voltage Vgs in [V]

FIGURE 5.15
Variation of surface potential ΨS and channel center potential Ψ0 versus gate-to-source voltage
Vgs with x = L/2 for a fixed channel length L = 50 nm and Vds = 0.0 V.
Device Simulation Using Silvaco ATLAS Tool 231

entire silicon film thickness, with both ΨS and Ψ0 closely following the gate
voltage. As the gate voltage increases toward threshold, the electron den-
sity becomes significant. As a result, ΨS continues to increase slowly, and Ψ0
starts to depart from ΨS and later saturates after being pinned to a maximum
value. The mobile charge near the silicon surfaces screens the gate field from
the center of the silicon film, and ΨS and Ψ0 become de-coupled (i.e., there
is no volume inversion). The channel potential versus gate voltage charac-
teristics for the devices having equal lengths but different thicknesses pass
through a single common point termed the crossover point [63], which is also
shown in Figure 5.15.

5.14.4 Program to Obtain Ids -Vgs Characteristics of DG MOSFET

# Program to obtain Id-Vgs characteristics

go atlas
# IMPORT THE MESH
mesh inf=dgmos.str

# contact specification
contact name=gate n.poly workfunction=4.74
contact name=gate1 n.poly workfunction=4.74 common=gate
contact name=source neutral
contact name=drain neutral

# model declaration
models auger srh conmob fldmob bgn temperature=300

# method definition
method newton itlimit=25 trap

# initial solution and drain bias specification

solve init
solve vdrain=0.05
#solve vdrain=0.1
#solve vdrain=0.5
#solve vdrain=1.5

# output log file declaration

log outf=dg1.log

# solution to obtain solution for id-vgs characteristics by

ramping Vgs
solve name=gate vgate=0 vfinal=1.2 vstep=0.05

# plotting the structure

tonyplot dg1.log
quit
232 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.01

1E–3

1E–4 Vds = 1.5 V

1E–5 Vds = 0.05 V

Drain Current Ids in [A]

1E–6
DIBL (mV/V)
1E–7 = (0.2866 – 0.1994)*103/(1.5 – 0.05)
= (63.58)
1E–8

1E–9

1E–10 SS = 72.6 mV/decade

1E–11

1E–12
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Gate-to-source Voltage Vgs in [V]

FIGURE 5.16
Drain current as a function of gate-to-source voltage for two different values of Vds. Also shown
is the calculation of DIBL and the subthreshold slope.

5.14.5 Simulation Results

Figure  5.16 shows the horizontally translated Ids-Vgs characteristics for low
(Vds = 0.05 V) and high (Vds = 1.5 V). The translation is known as DIBL and is
characterized by the number of millivolts of translation per volt of change in
drain voltage. In this case the DIBL is equal to 63.58 mv/V, which is satisfac-
tory because well-designed MOSFETs typically exhibit DIBL < 100 mV/V.
Figure  5.16 also indicates subthreshold swing (SS) characterized by the
slope of the Ids-Vgs curve in the subthreshold region, which is the number
of millivolts of increase in gate voltage needed to increase the drain current
by a factor of 10. The theoretical lower limit of SS is 60 mV/decade at room
temperature, while for well-designed MOSFETs the tolerable value for SS is
less than 80 mV/decade in order to ensure a rapid transition between the off
and on states (i.e., a small SS).

5.15 Summary
This chapter presents a comprehensive overview about MOSFET simula-
tion using Silvaco TCAD tools. The strategy and methodology applied for
MOSFET device simulation using Silvaco are emphasized. An overview of
Device Simulation Using Silvaco ATLAS Tool 233

the software developed by Silvaco in order to meet the simulation needs

for researching conventional and advanced MOSFET structures is also pre-
sented. In addition, several examples with source codes are provided for
the task of simulating different types of MOSFETs that are in use today. It
was shown how it is possible to obtain unique insight into the behavior of
MOSFETs by performing device simulation using Silvaco TCAD tools.

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63. B. Ray and S. Mahapatra, Modeling of channel potential and subthreshold slope
of symmetric double-gate transistor, IEEE Trans. Electron Devices, vol. 56, no. 2,
February 2009, pp. 260–266.
6
Study of Deep Sub-Micron VLSI
MOSFETs through TCAD

Srabanti Pandit

CONTENTS
6.1 Introduction................................................................................................. 237
6.2 Synopsys Technology Computer Aided Design (TCAD) Tool Suite.....238
6.3 Device Architecture and Simulation Setup............................................ 240
6.4 Short Channel Effects (SCEs).................................................................... 242
6.4.1 Threshold Voltage Roll-Off............................................................ 242
6.4.2 Drain-Induced Barrier Lowering (DIBL)..................................... 246
6.5 Mobility Degradation................................................................................. 249
6.6 Drain Characteristics.................................................................................. 251
6.6.1 Velocity Saturation.......................................................................... 251
6.6.2 Output Resistance........................................................................... 252
6.7 Inverse Narrow Width Effects (INWEs)..................................................254
6.7.1 Gate Fringing Field Effect..............................................................254
6.7.2 Dopant Redistribution................................................................... 257
6.8 Advanced Device Structures..................................................................... 259
6.8.1 SOI Structures................................................................................. 260
6.8.2 Double Gate (DG) MOSFETs......................................................... 261
6.9 Conclusion................................................................................................... 264
References.............................................................................................................. 265

6.1 Introduction
The feature size of metal-oxide-semiconductor (MOS) transistors has been
scaled down for higher packing density, reduced cost, and better performance.
This reduction in the device dimensions has more or less followed Moore’s
law, according to which the complexity of device integration is approximately
doubled every 18 months. The scaling procedure has pushed the transistor
dimensions well below the micrometer scale and into the deep sub-micro-
meter range [1]. However, in this domain, several fundamental limitations
due to the physics of the device lead to the deviation of the scaling process
from Moore’s prediction. Several physical effects (short channel effects [SCEs],

237
238 Technology Computer Aided Design: Simulation for VLSI MOSFET

inverse narrow width effects [INWEs], and gate leakage current) critically
affect the performances of deep sub-micron MOS transistors [2,3].
The SCEs mainly arise from the increased field at the drain end. The gate
starts to lose its control over the channel due to the perturbations caused
by the lateral drain field. The INWEs in the narrow devices are primarily
caused due to the combined effect of gate fringing field and dopant redistri-
bution phenomena. Further, gate leakage currents arise due to tunneling of
carriers through the thin gate oxide layer. To summarize, the channel length
and width reduction are associated with physical phenomena that primarily
involve the roles of the vertical gate field and/or the lateral drain field. The
depletion depths and the electrostatic potentials get altered along the chan-
nel length and the channel width. This ultimately leads to an overall degra-
dation of the desired behavior or performance of the devices. The behavioral
study of devices includes the study of parameters like threshold voltage roll-
off, drain-induced barrier lowering (DIBL) effect, transconductance, sub-
threshold slope degradation, output resistance, etc.
Synopsys technology computer aided design (TCAD) device simulator is
used efficiently in order to study the device behavior. The simulations are
based on numerical computations that yield reasonably accurate results.
The rest of the chapter is divided as follows. Section 6.2 presents a brief
introduction to the tools of the TCAD simulator used in this chapter. Section 6.3
discusses the device architecture and simulation setup. Section 6.4 deals with
the study of SCEs. Section 6.5 covers mobility degradation. In Section 6.6 we
study the drain characteristics, and in Section 6.7 we deal with the INWEs.
This is followed by a study of an advanced device structure in Section 6.8.
Finally, a conclusion is given in Section 6.9.

6.2 Synopsys Technology Computer Aided

Design (TCAD) Tool Suite
Synopsys TCAD tool suite is used for the study of the deep sub-micron
devices in this chapter. This tool suite includes tools for creating device
structures, meshing of the created structure, its simulation, scientific visual-
ization and plotting of simulated data, curve display, and extraction of per-
formance parameters. The tools used here are briefly discussed. The details
of the tool suite have been described in Chapter 4, and the respective user
guides [4] should be consulted for detailed descriptions.

1.
Sentaurus Structure Editor (SSE): This tool is used for device structure
creation. The structures are generated or edited interactively using
the graphical user interface (GUI). The Synopsys meshing engines
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 239

may be configured and called by interfacing through SSE. In addi-

tion, SSE generates the necessary input files (the TDR boundary file
and mesh command file) for the meshing engines that generate the
TDR grid and data file for the device structure. Alternatively, devices
can be created in batch mode using scripts. This option is useful for
creating parameterized device structures.
2.
Mesh: This engine helps to mesh the structure created with SSE. The tool
produces finite-element meshes for use in semiconductor device simu-
lation. The mesher generates high-quality spatial discretizations for 1D,
2D, and 3D devices using a variety of mesh generation algorithms.
3.
Sentaurus device: This tool is used to simulate the electrical characteristics
of the device. Upon specification of necessary input files, the simulated
outputs are generated in separate files. Terminal currents, voltages, and
charges are computed based on a set of physical device equations that
describe the carrier distribution and the conduction mechanisms.
4.
Tecplot SV: This tool has extensive 2D and 3D capabilities and is used
for scientific visualization and plotting of simulated data.
5.
Inspect: The electrical characteristics are plotted with the help of this
tool. It is basically a curve display and analysis program. The curves
are specified at discrete points.

The basic tool flow is illustrated in Figure 6.1. The various files associated
with each tool are also shown.

*.scm *.sat *_msh.log *_des.cmd

*.bnd or *.tdr
Sentaurus *_msh.tdr
*.cmd Mesh Sentaurus Device
Structure Editor

*_des.tdr
Inspect Tecplot_SV *_des.log

FIGURE 6.1
Basic tool flow using Synopsys TCAD.
240 Technology Computer Aided Design: Simulation for VLSI MOSFET

6.3  Device Architecture and Simulation Setup

Figure  6.2 shows the schematic cross-section along the length of a typical
bulk metal-oxide-semiconductor field-effect transistor (MOSFET) structure
that is used for simulation. It consists of an n+ polysilicon gate, a gate oxide, a
uniformly doped channel, shallow n+ source-drain extension (SDE) regions,
and deep source-drain (DSD) regions.
Here, channel length is along the x-axis and depth of the device is along
the y-axis. Lg is the drawn gate length, Leff is the effective channel length, tox
is the gate oxide thickness, and xj is the depth of the SDE region. For sim-
ulation purposes, the real device is created using the Sentaurus Structure
Editor (SSE). The default width of the device along the z-axis is 1 µm. The
device has Leff = 65 nm , tox = 3 nm, x j = 40 nm and power supply VDD = 1.2V .
The SDE and DSD regions are doped with arsenic with concentrations of 2.5
× 1020 cm–3 and 3.7 × 1020 cm–3, respectively. The channel is doped with boron
with a uniform concentration of 1 × 1018 cm–3. The constructed structure as
obtained from TCAD Structure Editor is shown in Figure 6.3.
The structure is subsequently meshed using the tool ‘Mesh’. The meshing
strategy ensures that fine elements are generated for the important regions
of the device (active region), and coarse elements are generated for the bulk
regions. The meshed structure is shown in Figure 6.4 that shows the zoomed-
in view of the active region of the transistor. The meshing strategy keeps the
problem at a minimum of computer processor time with reasonable accu-
racy. In one of our devices, in the channel region, the meshing element sizes
are 0.00475 µm in x- and y-directions and 1 µm in the z-direction.
The meshed structure is then simulated using the tool ‘Sentaurus device’.
The hydrodynamic (or the energy-balance) transport model [4] is used as
the physical model for simulation purposes. This model serves to describe

Lg Spacer

Gate G
tox
xj SDE
DSD
Leff

x
Body

FIGURE 6.2
A typical bulk MOSFET structure.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 241

–0.05
Polysilicon gate Spacer

0 Gate oxide

SDE

0.05
Y[um]

DSD
Depletion Contour
Doping Concentration [cm–3]
1.0E+22
0.1
4.8E+18
2.3E+15
8.6E+11
0.15 –4.8E+14
p-sub –1.0E+18

–0.1 –0.05 0 0.05 0.1 0.15 0.2

X[um]

FIGURE 6.3 (See color insert)

Bulk MOSFET structure created using TCAD.

properly the characteristics of the devices in the deep sub-micron regime. The
hydrodynamic model consists of a basic set of partial differential equations
(Poisson equation and continuity equations) and energy-conservation equa-
tions that are solved by considering the carrier temperature to be different

0
Y[um]

0.05

0.1

–0.1 –0.05 0 0.05 0.1

X[um]

FIGURE 6.4 (See color insert)

A zoomed-in view of the active region of the meshed structure.
242 Technology Computer Aided Design: Simulation for VLSI MOSFET

from the lattice temperature. The eQCvanDort flag [4] is specified to take
into account the quantization effects in the classical device simulation. The
OldSlotboom model [4] that takes care of the lattice-temperature dependence
of the band gap and band-gap narrowing is used for the determination of
the silicon intrinsic carrier concentration. The following mobility models are
used: Masetti model [4] in silicon that explains the carrier mobility degrada-
tion due to scattering of carriers by the dopant impurity ions; Canali model
[4] that explains degradation due to high electric fields, thus taking care of
the velocity saturation effect; and Lombardi model that explains the mobility
degradation at interfaces due to a transverse electric field [4].

6.4  Short Channel Effects (SCEs)

The short channel effect is the decrease of the threshold voltage of a MOS
transistor as the channel length is reduced [5]. The SCE is pronounced under
high drain bias.

6.4.1  Threshold Voltage Roll-Off

Figure 6.5 shows the variation of the electrostatic potential along the depth
of the device at a particular position along the length of the channel. This
figure is obtained using the tool ‘Tecplot SV’ after the simulated files are

0.8

0.6
Electrostatic Potential (V)

0.4

0.2

–0.2

–0.4

–0.6
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14
Depth (um)

FIGURE 6.5
Electrostatic potential variation along the depth near the middle of the channel.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 243

loaded. The device is sliced using an x-cut tool [4]. It is to be noted that the
electrostatic potential values obtained through TCAD are all computed from
an arbitrarily defined reference potential. In particular, for silicon, the stan-
dard approach is to set the reference potential equal to the Fermi potential
of an intrinsic semiconductor. The figure illustrates that with a certain gate
bias, the electrostatic potential in the semiconductor is maximum at the
surface (y = 0) and gradually decreases to zero beyond the depletion depth
where the bulk material is neutral.
The field patterns (i.e., the electrostatic potential contours in the deple-
tion region of a long channel and a short channel bulk MOSFET) are shown
in Figures  6.6(a) and 6.6(b), respectively. These figures are obtained after
the respective structures are simulated using the tool ‘Sentaurus device’
of TCAD and then visualized using the tool ‘Tecplot SV’. The long device
(Figure  6.6a) has an effective channel length, Leff of 1 µm, and the short
device (Figure 6.6b) has an effective channel length of 65 nm. As seen from
Figure 6.6(a), the potential contours are almost parallel to the oxide-silicon
interface. The electric field is thus one-dimensional, being along the verti-
cal direction only for almost the entire length of the channel. However, in
Figure 6.6(b) the field is two-dimensional (i.e., the components of the electric
field along both directions are appreciable). It is also seen that for a given
gate bias, the electrostatic potential at a particular depth from the oxide-
silicon interface is higher for the shorter device. In other words, the surface
potential (electrostatic potential at the surface) of the shorter device is more,
with a greater band bending at the oxide-semiconductor interface. This is
the key difference between a short channel and a long channel MOS tran-
sistor. The depletion width is thus more for the shorter device, as seen from
Equation (6.1) [5]:

2 εSi ψ s
Wd = (6.1)
qN a

where Wd is the depletion width, and ψs is the surface potential.

The white colored contour in Figure 6.6(b) is the depletion width contour.
The greater depletion depth in the shorter device means that the depletion
charge is effectively reduced. This leads to a reduction in the threshold volt-
age of the shorter device. Equation (6.2) shows the dependence of the thresh-
old voltage on the depletion charge density [5]:

Qd
Vth = VFB + 2 ψ B + (6.2)
WLeff Cox

where Vth is the threshold voltage, VFB is the flat-band voltage, ψB is the dif-
ference between Fermi level and intrinsic level, Qd is the depletion charge
244 Technology Computer Aided Design: Simulation for VLSI MOSFET

0
Y[um]

0.5 Electrostatic Potential [V]

1.6E+00
1.2E+00
7.8E–01
3.7E–01
–3.6E–02
1 –4.5E–01

–1 –0.5 0 0.5 1
X[um]
(a)

–0.05

0
Y[um]

0.05
Electrostatic Potential [V]
1.6E+00
1.2E+00
7.8E–01

0.1 3.7E–01
–3.6E–02
–4.5E–02

–0.1 –0.05 0 0.05 0.1

X[um]
(b)
FIGURE 6.6 (See color insert)
Electrostatic potential contours in (a) long channel Leff = 1 µm and (b) short channel Leff = 65 nm
(Vgs = 1.0V , Vds = 0.05V ).

density, and Cox is the gate oxide capacitance per unit area. Thus, as Qd
decreases, Vth also decreases.
The two-dimensional field pattern in a short channel device is due to the
close proximity of the source and drain regions. In a short channel device,
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 245

the source-drain distance is comparable to the depletion width in the vertical

direction [6]. The source-drain potential exerts a strong influence on the gate
potential over a significant portion of the channel length. According to the
charge sharing model [5,6], when the drain bias is low, all of the depletion
charges beneath the gate are not imaged on the gate charges. Rather, some of
them are the terminating centers of the field lines originating near the source
and drain junctions. Thus there is an effective reduction in the depletion
charge density that ultimately leads to the threshold voltage roll-off. This
is in contrast to the long channel devices where almost all of the depletion
charges are imaged on all the gate charges.
The threshold voltage roll-off as obtained from the TCAD simulator is
shown in Figure 6.7. Different devices of varying effective lengths are simu-
lated. The threshold voltages of the different devices are then determined
using the tool ‘Inspect’ by the constant current (CC) technique [7]. The refer-
ence current is taken to be 10 –6 A/µm. It is seen that for long channel lengths
the threshold voltage remains almost constant. However, as the channel
length is decreased the threshold voltage falls from its long-channel value.
This is due to the gradual reduction of the gate control over the channel in
the shorter devices. The drain field starts to exert its influence over the gate
field in the shorter devices.
The simple assumptions of the charge sharing model, however, render it
invalid for high drain and substrate biases. It is therefore unable to explain
the drain-induced barrier lowering (DIBL) that is discussed next.

0.6

0.5
Threshold Voltage, Vth (V)

0.4

0.3

0.2

0.1 Vsb = 0.1 V

Vsb = 0.0 V
0
0 200 400 600 800 1000
Effective Gate Length, Leff (nm)

FIGURE 6.7
Threshold voltage roll-off for two different substrate biases (Vgs = 1.0 V , Vds = 0.05 V ) .
246 Technology Computer Aided Design: Simulation for VLSI MOSFET

6.4.2  Drain-Induced Barrier Lowering (DIBL)

For long channels, as seen in Figure 6.6(a), the surface potential is flat over
most of the channel region of the device. The surface potential is mainly
controlled by the gate voltage and acts as a barrier to the electrons (for
n-channel MOSFET). The electrons are not able to surmount this barrier
below the threshold condition. However, in case of short devices, the source
and the drain fields penetrate deeper into the middle of the channel. This
lowers the barrier between the source and the drain. The electrons are then
able to overcome the reduced barrier and move toward the drain end. This
increases the subthreshold current. The threshold voltage of the short chan-
nel device is thus lower than that of a long channel device. As the drain bias
is increased the barrier is lowered further, resulting in a further decrease
in the threshold voltage. This phenomenon is referred to as the DIBL effect.
The surface potential plots as obtained from TCAD simulation for the long
and the short channel devices are shown in Figure 6.8 to illustrate the DIBL
effect. The shorter device has been studied with two drain biases.
In the figure, the variation of surface potential along the length of the device
is obtained by using the y-cut tool of ‘Tecplot SV’ for each of the devices. The
surface potential is then plotted against normalized channel length where 0
is the center of the channel, –1 is the source end, and 1 is the drain end.
It is shown in Figure 6.8 that with a very small drain bias (Vds = 0.05V ), the
surface potential at the source end is nearly equal to the built-in potential

1.00
0.95 Leff = 1 µm, Vds = 0.05 V

0.90 Leff = 65 nm, Vds = 0.05 V

0.85 Leff = 65 nm, Vds = 0.5 V
0.80
Surface Potential (V)

0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
–1 0 1
Normalized Channel Length

FIGURE 6.8
Surface potential plots as obtained through device simulation.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 247

barrier, V bi of the source-substrate junction. As the drain bias is increased

(Vds = 0.5V ), the surface potential at the drain end rises to (Vbi + Vds ) . Thus the
surface potential at the drain end rises by 0.45 V (0.50–0.05 V). Keep in mind
that the surface potential values in TCAD are measured relative to a refer-
ence. The absolute values are to be calculated accordingly. The DIBL effect
for the 65 nm MOSFET as obtained from the simulation results is shown in
Figure 6.9. The DIBL coefficient obtained is –0.18.
The threshold voltage roll-off and DIBL can be minimized in three ways:
(1) reduction of the oxide thickness to achieve better gate control over the
channel, (2) reduction of the depletion width, and (3) reduction of the source-
drain junction depth. The depletion width is reduced by increasing the
doping concentration in the channel. The source-drain junction depth is
effectively reduced by introducing the source-drain extension structure.
Figure 6.10 shows the DIBL effect as obtained from the simulation results
of a MOSFET with a lower SDE depth. Leff = 65 nm, x j = 25 nm, tox = 2.2 nm ,
and power supply VDD = 1.2V . The threshold voltages are calculated using
the constant current technique. The DIBL coefficient in this case is calculated
to be –0.11.
Figure 6.11 shows the subthreshold characteristics of the 65 nm MOSFET
as obtained from TCAD simulation results. It shows plots of the drain cur-
rent (in log scale) against the gate voltage for two different drain voltages.
It is seen that with the increase in the drain bias, the subthreshold current
increases. For very short devices, the subthreshold slope degrades because
the surface potential is controlled more by the drain than the gate. Eventually,
the gate loses all its control, and punch-through takes place when a high

0.24
Threshold Voltage, Vth (V)

0.22

0.2
L = 65 nm
0.18

0.16

0.14
0 0.1 0.2 0.3 0.4 0.5
Drain-to-source Voltage, Vds (V)

FIGURE 6.9
The DIBL effect, Leff = 65nm, xj = 40nm, tox = 3 nm.
248 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.2

0.19

0.18 L = 65 nm
Threshold Voltage, Vth (V)

0.17

0.16

0.15

0.14

0.13

0.12

0.11

0.1
0 0.1 0.2 0.3 0.4 0.5 0.6
Drain-to-source Voltage, Vds (V)

FIGURE 6.10
The DIBL effect, Leff = 65 nm, xj = 25 nm, tox = 2.2 nm.

10–3
Vds = 0.5 V

10 –4 Vds = 0.05 V
Drain Current, Ids (A/um)

10–5

10–6

10–7

10–8

10–9
0 0.2 0.4 0.6 0.8 1
Vgs (V)

FIGURE 6.11
Subthreshold characteristics for two different drain biases (L eff = 65 nm).
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 249

drain current persists irrespective of the gate voltage. The subthreshold

swings (SSs) for the low and high drain biases as obtained from Figure 6.11
are 90 mV/decade and 95 mV/decade, respectively.

6.5  Mobility Degradation

The mobility of carriers in the MOSFET channel is significantly lower than
that in the bulk silicon [6]. At the surface boundary, lattice (or phonon) scat-
tering is increased due to the presence of crystalline discontinuity. At high
vertical fields, surface roughness scattering severely degrades the carrier
mobility. Channel mobility is also affected by the oxide and interface traps
at the Si-SiO2 interface [6].
Figure 6.12 shows the plot of transconductance, g m against Vgs for the 65-nm
device for two different substrate biases under low and high drain biases.
Figure 6.12(a) is for a small drain bias, with Vds = 0.05 V , and Figure 6.12(b) is
for a comparatively higher drain bias with Vds = 1.0 V . The transconductance
plots are obtained by differentiating the curves of the I ds − Vgs characteristics.
This is done by using the ‘diff’ command in the ‘Inspect’ tool. In Figure 6.12(a)
it is observed that when the drain bias is low, the transconductance starts to
fall off from a high value beyond a certain gate voltage. This is explained as
follows. When the vertical electric field is very high (in this case it is greater
than 1.6 × 106 V/cm for an oxide thickness of 3 nm and gate bias greater
than 0.5 V), the mobility decreases very rapidly due to reasons discussed
earlier. Thus, at low drain bias, the drain current and the transconductance
are degraded significantly at high gate voltages. Also note that at low Vds, the
parasitic source-drain resistance plays a significant role in determining the
drain current. The peak drain current and consequently the transconduc-
tance decrease in the linear region (low Vds ) due to this resistance.
However, if the drain bias is high as in Figure 6.12(b), the transconductance
does not fall off. This is due to velocity saturation. The mobility degradation
of the carriers is somewhat counterbalanced by the high drift velocity of the
carriers under high drain bias. For very short channel transistors, the drain
current I ds becomes limited by the velocity saturation effect. This saturated
drain current is given as [6]

I dsat = CoxWvsat (Vgs − Vth ) (6.3)

Consequently, the transconductance is also fixed at a constant value.

It is interesting to note from Figure  6.12 that the maximum value of the
transconductance at low Vds is much lower than that at high Vds . This is
explained as follows.
250 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.00016

0.00014

0.00012

0.0001
gm (S/um)

8E–05

6E–05

4E–05
Vsb = 0.5 V
2E–05 Vsb = 0 V

0
0 0.2 0.4 0.6 0.8 1
Gate-to-source Voltage, Vgs (V)

0.001

0.0008

0.0006
gm (S/um)

0.0004

0.0002
Vbs = 0.5 V
Vbs = 0 V

0 0.2 0.4 0.6 0.8

Gate-to-source Voltage, Vgs (V)

FIGURE 6.12
Transconductance versus Gate-to-source Voltage; (top)Vds = 0.05V and (bottom) Vds = 1.0V.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 251

The drain current, Ids may be written as

Vds
I ds = (6.4)
Rds + RCh

where RCh is the channel resistance, and Rds is the source-drain resistance
due to the lightly doped SDE regions, or,

Vds
RCh =
I ds Rds = 0

or Equation (6.4) may be written as
Vds
I ds Rds = 0 (6.5)
RCh
I ds = Rds =
1+ 1+
RCh
Rds = 0 Rds I ds

Vds

Therefore, when Vds is low, it is due to Rds , that I ds drops from its value,
I ds Rds =0. Thus the maximum value of the transconductance is lowered at low
drain bias.

6.6  Drain Characteristics

A significant effect that critically affects the I-V characteristics of a deep sub-
micron MOS transistor is velocity saturation.

6.6.1  Velocity Saturation

In a short channel device, the saturation of the drain current may take place
at a much lower Vds value than the Vds value of the longer device. This limits
the saturation current of the device. This is illustrated in Figure 6.13 where
two curves are drawn: the upper one is for the long channel, and the lower
one corresponds to the shorter device. It is seen that the shorter device expe-
riences an early saturation (i.e., the current saturates at a lower drain voltage).
This occurs due to velocity saturation and is explained as follows. In the
presence of velocity saturation,

1 m 1
= + (6.6)
Vdssat Vgs − Vth ξ sat Leff

where ξ sat is the critical electric field beyond which the velocity saturates,
and m is the bulk charge factor [8]. Equation (6.6) shows that the short chan-
nel Vdssat is an average of ξ sat Leff and long channel Vdssat (= VGSm−Vth ). Thus short
channel Vdssat is smaller than long channel Vdssat . Hence the drain current for
the shorter MOS transistor saturates earlier compared to the long channel
value.
252 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.0007
Leff = 1000 nm
Leff = 65 nm
0.0006
Drain Current, Ids (A/um)

0.0005

0.0004

0.0003

0.0002

0.0001

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Drain-to-Source Voltage, Vds (V)

FIGURE 6.13
Drain current versus drain-to-source voltage (Vgs = 1.1 V).

6.6.2  Output Resistance

Figure 6.14 shows the simulated drain characteristics of a 65 nm MOSFET. As
seen in Figure 6.14, for the short channel MOSFET, the drain current increases
beyond saturation. There are two reasons for this. First, due to the increase
of drain voltage, threshold voltage falls and hence the current increases. This
is the DIBL effect. Second, as Vds is increased beyond the saturation voltage,
the saturation point (the point along the channel length where carriers attain
the saturation velocity) where the surface channel collapses moves slightly
toward the source [6]. That is, the conducting channel length deceases. As a
result, the current increases beyond the saturation point. This is the channel
length modulation effect.
The increase in the current beyond the saturation point implies that the
output conductance is finite. A plot of the output resistance against the
drain-to-source voltage is shown in Figure  6.15. It is seen from the curves
that in the subthreshold region, the drain current is low so that the output
resistance is high. In the strong inversion region, the drain current is high so
that output resistance is low. In weak inversion, with the increase of drain
bias, the drain current increases due to various second-order effects such
as channel length modulation, DIBL effect, etc. Thus the output resistance
value falls. However, in strong inversion, the increase of drain current with
the increase of drain bias due to the above effects is somewhat counterbal-
anced by the carrier mobility degradation effect due to the applied gate bias.
Therefore the overall increase of drain current is small. Hence the output
resistance remains nearly constant.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 253

0.0008

0.0007 Vgs = 1.1 V

0.0006
Drain Current, Ids (A/um)

0.0005
Vgs = 0.8 V
0.0004

0.0003
Vgs = 0.6 V
0.0002
Vgs = 0.4 V
0.0001
Vgs = 0.2 V
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Drain-to-source Voltage, Vds (V)

FIGURE 6.14
Drain characteristics of a 65 nm MOSFET.

16000

14000
Output Resistance, Rout (ohm/um)

12000
Vgs = 1.1 V
10000
Vgs = 0.8 V
Vgs = 0.4 V
8000

6000

4000

2000

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Drain-to-source Voltage, Vds (V)

FIGURE 6.15
Output resistance versus drain voltage (Leff = 65 nm).
254 Technology Computer Aided Design: Simulation for VLSI MOSFET

6.7  Inverse Narrow Width Effects (INWEs)

As the device dimension is reduced along its width, we come across effects
known as the narrow width effects. In LOCOS isolated devices, threshold
voltage increases with a decrease in the width of the device. The deep sub-
micron devices isolated using the shallow trench isolation (STI) process are
associated with a decrease in the threshold voltage with a reduction in the
channel width. This effect associated with the STI MOSFETs is known as
the inverse narrow width effect (INWE) [5]. Narrowing the channel width
of a transistor affects its performance to an extent comparable to the effects
caused by shortening the channel length [9,10]. Hence the study of MOS tran-
sistor performances along the width dimension becomes important for the
design of low power complementary metal-oxide-semiconductor (CMOS)
circuits and memory cells [11,12].
The INWE is primarily caused due to two reasons. First is the combined
effect of gate fringing fields through trench oxide and dopant redistribution
phenomenon [13,14]. Second is the effect of STI stress [15]. The effect of the lat-
ter is dominant for comparatively larger widths, while the former is dominant
for narrower widths [15]. STIMOS transistors with channel widths below 1 µm
exhibit threshold voltage roll-off where the INWE effect is the dominant cause.

6.7.1  Gate Fringing Field Effect

Figure  6.16 shows the schematic of the cross-section along the width of
the STIMOS device. The field lines originating from the gate terminate on
charges under the gate through the thin gate oxide. Some of the field lines
also terminate on charges along the trench oxide sidewalls. These are the
fringing field lines.
Figure 6.17 shows the cross-section along the width of a typical STIMOS
device as obtained by using the appropriate slicing tool of ‘Tecplot SV’. The
electrostatic potential contours are shown in the figure. It is seen in the figure
that the depletion depth (the white contour is the depletion contour) is non-
uniform and varies along the width of the device. In wide MOS devices, the
enhanced depletion region near the sidewalls caused due to the gate fringing
field is a small percentage of the total depletion volume and can be neglected.
The depletion depth may then be considered to be uniform throughout the
width without resulting in too much of an error in the analysis of the device
performances. For devices with small widths, the depletion volume near the
sidewalls becomes a large percentage of the total depletion volume. This is
referred to as the gate fringing field effect and is illustrated in Figure 6.18.
MOS devices with varying channel widths are created using the Sentaurus
Structure Editor and are then simulated using the tool ‘Sentaurus device’.
The simulated devices are then visualized using the tool ‘Tecplot SV’. The
depletion depths along the width are noted and then plotted as in Figure 6.18.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 255

Gate

Poly gate
Normal field lines through
gate oxide (SiO2)
Width, W
Fringing field lines through
trench oxide (SiO2)

Depletion region contour

y
z
p-substrate

FIGURE 6.16
Cross-section along the width of a trench-isolated MOSFET including gate fringing fields.

It is observed from Figure 6.18 that as the device becomes narrower, the gate
fringing increases.
The effect of gate fringing is modeled by a parasitic fringe capacitance. The
higher depletion depths at the trench oxide sidewalls are associated with a
higher surface potential. Figure 6.19 shows the schematic representation of

0.05

Polysilicon gate
Depth (um)

0 Gate oxide (SiO2)

STI oxide

Electrostatic Potential [V]

5.3E–01
–0.05 Depletion Width Contour 3.4E–01
1.4E–01
–5.5E–02
–2.5E–01
p-sub –4.5E–01
–0.1
–0.0.5 0 0.05 0.1 0.15
Width (um)

FIGURE 6.17 (See color insert)

Cross-section along the width of a trench-isolated MOSFET.
256 Technology Computer Aided Design: Simulation for VLSI MOSFET

–0.014
W1 = 40 nm
–0.016 W2 = 200 nm
W3 = 400 nm
–0.018 W4 = 2000 nm
Depletion Depth (um)

–0.02

–0.022

–0.024

–0.026

–0.028

–1 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1

Width (normalized)

FIGURE 6.18
Gate fringing field effect for STI MOSFETs.

the variation of the depletion depth and the corresponding surface potential
along the width of the device.
In Figure 6.19(a) the depletion depth at the trench-oxide sidewall is dw max ,
decreases to a value dw, remains constant at dw beyond a critical point zb,
and then finally increases again to dw max at the other sidewall. Figure 6.19(b)
shows the variation of the surface potential ψ S along the width of the device.
ψ SM is the surface potential in the middle of the device; ψ ST is the surface
potential at the trench oxide sidewall edges.
Figure 6.20 shows the surface potential profile along the width of a typical
simulated device. The gate fringing field through the trench oxide causes the
surface potential at the sidewall edges to increase in comparison to that at
the middle of the channel width.
The sidewall surface potential ψ ST varies with Vgs in a similar fashion
as the surface potential at the middle ψ SM does with Vgs. A typical device
has been simulated for different gate biases, and the results are as shown in
Figure 6.21.
The surface potential at the center of the device is related to that at the
trench-oxide sidewalls by the relation [13,16]

ψ ST = lψ SM + d (6.7)

where l is close to unity, and d is a numerical constant expressed as

nkT
d=
q

Study of Deep Sub-Micron VLSI MOSFETs through TCAD 257

Channel width
zb W x
0 z
Depletion depth

dw
ΨST

Surface potential
dwmax ΨSM

x 0 Channel width z
W

(a) (b)

FIGURE 6.19
(a) Variation of depletion depth along the channel width. (b) Variation of surface potential
along the channel width.

where kTq is the volt equivalent of temperature. The value of n lies between 1.2
and 2.3 for devices with largely varying dimensions like 200 nm gate length
to 40 nm gate length having substrate doping ranging from 1017/cc to 1019/cc.

6.7.2  Dopant Redistribution

The depletion charge density does not remain constant along the entire width
of the channel. This is due to the non-uniformity of the doping concentration

0.45
Electrostatic Potential (V)

0.4

0.35

–0.06 –0.04 –0.02 0 0.02 0.04 0.06

Width (um)

FIGURE 6.20
Plot of surface potential against the width of the device.
258 Technology Computer Aided Design: Simulation for VLSI MOSFET

1.5
ΨSM
ΨST

1
Ψs (V)

0.5

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Gate-to-source Voltage, Vgs (V)

FIGURE 6.21
Simulation results showing variation of ψST and ψSM with Vgs (Vsb = 0V).

along the width of the channel which is caused by dopant redistribution

(comprised of dopant segregation [17–19] and transient-enhanced diffusion,
TED [20]). After the gate oxidation processing step, dopant atoms in the
active channel regions of the transistors start to diffuse out to the adjacent
trench oxide/Si interface. This is referred to as the dopant segregation effect
[21]. In particular, boron in NMOS transistors gets depleted at the STI edges
and segregates to the oxide/Si interface [17]. Boron segregation reduces the
B-concentration near the STI edges. If the active area of the device is nar-
row enough, boron segregation would reduce the boron concentration sig-
nificantly even at the center of the channel [19]. Further, during the silicon
processing step, ion implantation of the dopant impurities dislodges silicon
atoms from their lattice sites, which are known as interstitial silicon atoms.
A subsequent annealing step repairs some of these lattice damages. The
remaining interstitial silicon atoms play an active role in the diffusion of
the dopant impurities. High concentrations of these silicon atoms enhance
boron diffusion. This phenomenon is known as transient-enhanced diffu-
sion (TED). The TED process leads to a substantial decrease of the boron
concentration in proximity to the STI edge relative to the center of the chan-
nel [20]. Again if the device is narrow enough, the decrease in the boron
concentration may take place significantly even at the center of the channel.
The doping profile along the channel width is expressed as [22]

  z+W   W 
 N − Nt 
N ( z) =  a  erf  2  − erf  z − 2   + N (6.8)
 
   2 Dt  t
2   2 Dt  

Study of Deep Sub-Micron VLSI MOSFETs through TCAD 259

× 1018
Peak Doping Concentration, Nc (/cu.cm)

3.4

3.2

2.8

2.6

2.4

2.2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Width, W (micron)

FIGURE 6.22
Variation of the peak channel doping concentration with the channel width.

where Nt is the doping concentration at the trench oxide sidewalls, Na is the

substrate doping concentration, and 2 Dt is the diffusion length.
Figure 6.22 shows the plot of the peak concentration against channel width.
The figure shows that for large widths, the doping concentration of the chan-
nel is equal to Na. However, as the width decreases, the peak concentration in
the channel is reduced due to dopant redistribution.
Figure 6.23 shows the plot of the INWE on the threshold voltage of bulk STI
MOSFETs with Leff = 40 nm. Different devices with varying channel widths
are created using Sentaurus Structure Editor. The source and drain regions
are doped with arsenic. A Gaussian doping profile is considered with a peak
concentration of 1 × 1019 cm–3. The peak concentration, peak position, and con-
centration value at the junction depth are specified to the simulator. The chan-
nel is doped with boron with a maximum concentration of 3 × 1018 cm–3. An
analytical doping profile, identical to that described by Equation (6.8) has been
defined to incorporate the phenomenon of dopant redistribution. The specified
parameters are maximum concentration and inflection point. The constructed
structure is subsequently meshed and simulated using the respective tools.
The meshing strategy ensures that fine elements are generated for the critical
parts of the device (active region) and coarse elements for the bulk regions.

6.8  Advanced Device Structures

Scaling of MOSFETs has led to several serious limitations; for example,
(1) device performance compromised due to undesirable effects such as
threshold voltage roll-off, drain-induced barrier lowering (DIBL), degraded
260 Technology Computer Aided Design: Simulation for VLSI MOSFET
Threshold Voltage Change, ∆VthINWE (mV)

–20

–40

–60

–80 Vsb = 0 V
Vsb = 0.5 V

–100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Width, W (log scale)

FIGURE 6.23
Inverse narrow width effect (INWE) on the threshold voltage versus channel width (Vgs = 1.0V,
Vds = 0.05 V, Vsb = 0.5 V).

subthreshold slope; (2) technological barriers like the manufacturing of

optical equipment required for the reduction in the wavelength of light for
lithography procedures; (3) gate-oxide thickness reduction leading to quan-
tum mechanical tunneling, which in turn necessitates the introduction of
gate dielectric materials with high dielectric constants so that the physical
thickness of the dielectric can be increased; and (4) high doping between
the source and drain which increases the parasitic capacitance between the
source, drain, and the substrate.
All of the above led to the development of the silicon-on-insulator (SOI)
technology.

6.8.1  SOI Structures

SOI structures are of two types. These are partially depleted SOI (PDSOI)
and fully depleted SOI (FDSOI). In PDSOI, the silicon film is larger than
the sum of the gate depletion widths from the front and back ends. These
devices exhibit a floating body effect (kink effect). This occurs when carriers
of the same type as the body, generated by impact ionization near the drain,
are stored in the floating body. This alters the body potential and hence the
threshold voltage. A way to minimize this is to use body contacts. However,
the body effect advantage is lost in that case. In FDSOI, the silicon film is
thin enough that the entire film is depleted before the threshold condition
is attained. These devices exhibit a steeper subthreshold slope as compared
to the bulk devices. The FDSOI devices were found to perform better than
the PDSOI.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 261

Gate

Source Drain

Buried oxide (BOX)

Silicon substrate
(Back gate)

FIGURE 6.24
Conventional thin film SOI MOSFET.

Figure 6.24 shows the schematic of a conventional thin film SOI MOSFET

structure. Most of the electric field lines as shown in Figure  6.24 from the
source and drain propagate through the buried oxide (BOX) layer before
reaching the channel layer. The SOI structures exhibited lower leakage, low
junction capacitance, low latch-up, and better subthreshold swing [23–25].
The performance of these devices in regard to SCEs depends on the silicon
film thickness, BOX layer thickness, and doping concentrations [26].
In the deep sub-micron regime, the merits offered by the FDSOI devices
diminished, and then double gate structures were found to be more promising.

6.8.2  Double Gate (DG) MOSFETs

The DG-MOSFETs are very attractive to improve the performance of CMOS
devices and to overcome some of the difficulties faced in the downscaling of
MOSFETs into the deep sub-micron regime. Threshold voltage roll-off, DIBL,
off-state leakage, etc., are significantly reduced; hence, these devices are pre-
ferred in nanoscale circuits [27–29].
Figure 6.25 shows the schematic diagram of a typical DG-MOSFET. It con-
sists of a silicon slab sandwiched between two oxide layers. A metal or a poly-
silicon film contacts the two oxide layers [26]. These act as the front and back
gate electrodes that create inversion layers near the two Si-SiO2 interfaces

Gate

Source Drain

Gate

FIGURE 6.25
A typical DG-MOSFET.
262 Technology Computer Aided Design: Simulation for VLSI MOSFET

upon the application of a suitable bias. Thus there are two MOSFETs that
share the same source, drain, and substrate.
The salient features of a DG-MOSFET are control of the SCEs by device
geometry and not by doping (channel doping or halo doping) as done in
bulk MOSFETs. The two gate electrodes jointly control the carriers, thereby
screening the effect of drain field from the channel. Additionally, the thin
silicon channel leads to a stronger coupling of the gate potential with the
channel potential. The reduced SCEs lead to greater scalability than bulk
MOSFETs. The undoped body (intrinsic channel) reduces mobility degrada-
tion by eliminating impurity scattering, thereby improving the carrier trans-
port. The random microscopic dopant fluctuations are also avoided [30]. The
current drive (or gate capacitance) per unit area is increased [31].
The DG-MOSFETs are again of two types, symmetric DG-MOS and asym-
metric DG-MOS [23]. In the former, the two oxide thicknesses are the same,
the two gates have the same flat-band voltage, and the gates are connected
together. In the latter, the two oxide thicknesses are different.
Figure  6.26 shows the cross-section along the length of a DG-MOSFET
structure as seen in the tool ‘Tecplot SV’ of TCAD.
Figure  6.27 shows the subthreshold characteristics of the simu-
lated DG-MOSFET for two drain biases. The lower curve corresponds
to Vds = 0.05 V , and the upper one corresponds to Vds = 0.5 V. The subthresh-
old swing for Vds = 0.05 V is calculated to be 75 mV/decade, and that for
Vds = 0.5 V is 80 mV/decade.

Front gate

Front oxide
0
Y[um]

0.02 Source Drain

0.04
Back oxide
Back gate

–0.04 –0.02 0 0.02 0.04

X[um]

FIGURE 6.26 (See color insert)

A typical DG-MOSFET structure as simulated in TCAD.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 263

10–2

10–3
Drain Current, Ids (A/µm)

10–4

10–5

10–6

10–7
Vds = 0.05 V
Vds = 0.50 V
10–8
0.0 0.2 0.4 0.6 0.8 1.0
Gate-to-source Voltage, Vgs (V)

FIGURE 6.27
Subthreshold characteristics of DG-MOSFETs for two different drain biases (Leff = 65 nm).

Figure  6.28 shows the DIBL effect as obtained from TCAD results. The
DIBL coefficient is calculated to be –0.10. It is seen that the DG-MOSFETs
show a steep subthreshold swing and a high drive current. However, the
limitations of DG-MOSFETs in relation to how far it can be scaled come from
the SCEs, such as threshold voltage roll-off and DIBL.
The DG-MOSFETS are associated with the following phenomena:

1. The SOI-based DG-FinFETs exhibit self-heating effects [8] because the

device is thermally insulated from the substrate by the BOX layer.
This consequently alters the output characteristics of the device,
especially in the sub-micron regime.
2. Quantum mechanical effects: Due to the ultra thin nature of the silicon
channels, quantization effects are seen. This affects the distribution
and mobility of carriers [32].
3. Volume inversion: As the silicon film is reduced, the inversion layer
is formed not only near the two oxide interfaces, but the entire
silicon film gets inverted. The carriers are no longer confined to
the interfaces but are distributed throughout the entire silicon
volume [26]. This phenomenon is found to increase the mobility
of the carriers by reducing their scattering at the oxide and inter-
face traps.
264 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.08

0.07

0.06
Threshold Voltage, Vth (V)

0.05 DG-FinFET, L = 65 nm

0.04

0.03

0.02

0.01

0
0 0.1 0.2 0.3 0.4 0.5 0.6
Drain-to-source Voltage Vds (V)

FIGURE 6.28
The DIBL effect (L = 65 nm).

4.
Misalignment of top and bottom gates: The DG-MOSFETs are difficult
to fabricate; in particular, the achievement of a perfect vertical align-
ment of the top and the bottom gates poses a serious problem. Any
misalignment between the gates leads to device performance degra-
dation due to overlap capacitance and loss in current drive [3].

6.9 Conclusion
The performances of MOSFETs in the sub-micron regime are limited
by several physical phenomena such as the short channel effects along
the channel length that mainly consist of the threshold voltage roll-off,
drain-induced barrier lowering, and subthreshold slope degradation.
Apart from these, mobility degradation, transconductance, and output
resistance are also affected. The inverse narrow width effect along the
channel width consists of the combined effect of gate fringing and dopant
redistribution that leads to a threshold voltage roll-off. All of these effects
have been studied for a typical bulk MOSFET with the help of the TCAD
device simulator. Additionally, a typical double gate (DG) MOSFET has
also been studied with TCAD. The TCAD studies reveal the device behav-
ior accurately.
Study of Deep Sub-Micron VLSI MOSFETs through TCAD 265

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7
MOSFET Characterization for
VLSI Circuit Simulation

Soumya Pandit

CONTENTS
7.1 Introduction................................................................................................. 269
7.2 Device Models for Circuit Simulation..................................................... 270
7.2.1 Necessity of Device Models.......................................................... 270
7.2.2 Definition and Categories of Device Models.............................. 271
7.2.3 Commercially Used Compact Models......................................... 272
7.3 Threshold Voltage Characterization........................................................ 273
7.3.1 Threshold Voltage Characterization for Long Channel
MOS Transistor............................................................................... 273
7.3.1.1 Uniform Channel Doping............................................... 273
7.3.1.2 Vertical Channel Engineering........................................ 275
7.3.1.3 Halo/Pocket Implantation.............................................. 277
7.3.2 Threshold Voltage Characterization for Short Channel
MOS Transistor............................................................................... 278
7.3.2.1 Short Channel Effect Reduction..................................... 281
7.3.3 Techniques for Threshold Voltage Extraction............................. 282
7.3.3.1 Constant Current Method............................................... 282
7.3.3.2 Extrapolation in the Linear Region Method................ 282
7.3.3.3 Second Derivative Method............................................. 282
7.3.4 Simulation Results and Discussion.............................................. 282
7.3.4.1 Simulation Setup.............................................................. 283
7.3.4.2 Threshold Voltage Characterization with
Substrate Bias Effect......................................................... 283
7.3.4.3 Threshold Voltage Characterization for Short
Channel Transistors......................................................... 283
7.3.4.4 Threshold Voltage Extraction......................................... 286
7.4 I-V Characterization................................................................................... 288
7.4.1 Current Density Equations............................................................ 288
7.4.2 Channel Inversion Charge Density.............................................. 290
7.4.3 Carrier Mobility Degradation Model........................................... 291
7.4.4 Carrier Velocity Saturation Model............................................... 293

267
268 Technology Computer Aided Design: Simulation for VLSI MOSFET

7.4.5 Basic MOSFET I-V Model............................................................... 294

7.4.6 MOSFET I-V Model with Velocity Saturation............................. 295
7.4.7 Parasitic Source Drain Resistance................................................ 297
7.4.8 Output Resistance........................................................................... 298
7.4.9 Subthreshold I-V Model.................................................................300
7.4.10 Characterization of Poly-Silicon Gate Depletion Effect............. 303
7.4.10.1 Reduction of Gate-Source Voltage................................. 303
7.4.10.2 Effect on Threshold Voltage...........................................304
7.4.10.3 Effect on Oxide Thickness..............................................305
7.4.10.4 Electrical Oxide Thickness.............................................306
7.4.11 Simulation Results and Discussion.............................................. 306
7.4.11.1 Variation of Drain Current, Transconductance,
and Output Resistance with Gate Voltage.................... 306
7.4.11.2 Subthreshold Characteristics......................................... 309
7.4.11.3 Variation of Transconductance Generation
Efficiency, Intrinsic Gain, Linearity, and Cutoff
Frequency..........................................................................309
7.4.11.4 Variation of Drain Current and Output Resistance
with Drain Bias................................................................. 315
7.5 Hot Carrier Effects Due to Impact Ionization......................................... 317
7.5.1 Hot Carrier Injection (HCI)........................................................... 319
7.6 Characterization of Gate Dielectric.......................................................... 320
7.7 Capacitance Characterization................................................................... 321
7.7.1 Capacitance Components in a MOS Transistor.......................... 321
7.7.2 Characterization of Intrinsic Capacitances (Meyer’s
Approach)........................................................................................ 322
7.7.2.1 Intrinsic Capacitances in the Linear Region................ 323
7.7.2.2 Intrinsic Capacitances in the Saturation Region......... 324
7.7.2.3 Intrinsic Capacitances in the Subthreshold Region.... 324
7.7.2.4 Intrinsic Capacitances in the Accumulation Region....325
7.7.2.5 Charge-Based Approach................................................. 325
7.7.2.6 Effect of Poly-Silicon Gate Depletion Effect and
Finite Inversion Charge Layer Thickness..................... 326
7.7.3 Characterization of Extrinsic Capacitances................................ 326
7.7.3.1 Characterization of Fringing and Overlap
Capacitances..................................................................... 326
7.7.3.2 Characterization of Junction Capacitances.................. 328
7.7.4 Simulation Results and Discussion.............................................. 329
7.8 Noise Characterization.............................................................................. 331
7.8.1 Characterization of Thermal Noise in MOS Transistor............ 332
7.8.2 Characterization of Flicker Noise in MOS Transistor...............334
7.8.2.1 Physical Mechanisms of Flicker Noise.........................334
7.8.2.2 Empirical Approach for Characterization of
Flicker Noise..................................................................... 335
MOSFET Characterization for VLSI Circuit Simulation 269

7.8.2.3 Characterization of Flicker Noise through

Physics-Based Model....................................................... 335
7.8.3 Simulation Results and Discussion.............................................. 339
7.9 Statistical Characterization.......................................................................343
7.9.1 Classification of Process Variability.............................................344
7.9.2 Sources of Random Intra-Die Process Variations and Their
Effects...............................................................................................344
7.9.2.1 Random Discrete Dopant (RDD)...................................344
7.9.2.2 Line Edge Roughness (LER)...........................................345
7.9.2.3 Oxide Thickness Variation (OTV).................................346
7.9.3 Characterization of Process Variability.......................................346
7.9.3.1 Design Corner Approach................................................346
7.9.3.2 Monte Carlo Simulation Approach...............................348
7.9.3.3 Statistical Corner Approach...........................................348
7.9.4 Simulation Results and Discussion..............................................348
7.9.4.1 Statistical Characterization of RDD.............................. 349
7.9.4.2 Statistical Characterization of Line Edge
Roughness (LER).............................................................. 349
7.9.4.3 Statistical Characterization of OTV...............................354
7.9.4.4 Statistical Characterization of Simultaneous
Variations..........................................................................354
7.10 Summary and Conclusion......................................................................... 360
References.............................................................................................................. 360

7.1 Introduction
With the continual downscaling of metal-oxide-semiconductor (MOS) tran-
sistors to the sub-90 nm regime, several secondary issues related to the tran-
sistor device physics, hitherto considered to be insignificant, are found to
play significant roles in circuit performances. The circuit designers therefore
need proper understanding of the various parameters related to geometry
as well as performances of a single MOS transistor and the effect of these on
the performances of an overall very large scale integrated (VLSI) circuit. A
detailed characterization of the MOS transistor device to be used by them
for the design is therefore an essential requirement prior to the design task,
especially in sub-90 nm design domain. The objective of this chapter is to
present a comprehensive discussion on the characterization of sub-90 nm
MOS transistor for VLSI circuit simulation purpose. The discussion is lim-
ited to conventional bulk MOS transistor only, because this has been the
most widely used device for VLSI circuit simulation, considering the cost
and expertise required for fabrication.
The pedagogical approach used in this chapter is that initially the various
characteristics are discussed qualitatively. This is followed by introduction
270 Technology Computer Aided Design: Simulation for VLSI MOSFET

of standard mathematical models. The use of these models in a BSIM4 com-

pact model (which is one of the most widely used industry standard compact
models) is thereafter discussed briefly. The purpose of this chapter is to pres-
ent the primary important characteristics of VLSI metal-oxide-semiconductor
field-effect transistor (MOSFET) to the integrated circuit (IC) designers in a
manner such that they are aware of the internal workings of the SPICE simu-
lation tool. The readers are encouraged to refer to appropriate BSIM manuals
and SPICE model user guides for the exact mathematical formulations and
the complete modeling works. SPICE simulation results are provided to sup-
port the theoretical discussion, as required.
The rest of the chapter is organized as follows. Section 7.2 emphasizes the
importance of the use of device models for VLSI circuit simulation. The vari-
ous categories of device models and the publicly available device models
are also discussed. Section 7.3 presents the detailed characterization of the
threshold voltage of an n-channel enhancement mode transistor. Section
7.4 discusses the I-V characteristics, supported with results. Sections 7.5
and 7.6 discuss the impact ionization process and the gate dielectric model.
Characterizations of MOS capacitances are discussed in Section 7.7. Noise
and statistical characterization are discussed in Sections 7.8 and 7.9, respec-
tively. Finally, Section 7.10 presents a summary and conclusion of the chapter.

7.2 Device Models for Circuit Simulation

7.2.1 Necessity of Device Models
An outline of the IC simulation procedure is illustrated in Figure 7.1. The pro-
cedure starts with a set of desired specifications for the circuit to be designed.
This acts as the input to the procedure. A particular topology of the circuit
(transistor-level topology) is then selected by the designer. This choice is pri-
marily based upon the designer’s experience. The circuit is described either
schematically or through a textual description, referred to as the netlist of
the circuit. The circuit is subsequently analyzed through SPICE simulation
tool. The SPICE simulation tool internally uses a set of device models for
the components of the circuits and solves a set of network theory equations
through standard numerical algorithms [1].
The performance parameters of the circuit are extracted and compared with
the desired specifications. If the extracted parameters satisfy the desired specifi-
cations, the design is completed. Otherwise the simulation procedure is carried
out iteratively either by changing the circuit description or circuit parameters
and conducting further analyses until the specifications are satisfied.
From 1970 onward, SPICE has been the sole tool used by IC designers for
circuit simulation. The development of this tool started at the University
MOSFET Characterization for VLSI Circuit Simulation 271

Desired Specifications

Circuit Description

Circuit Analysis

Not OK
Device Models

Circuit Simulation Process

Design Verification

OK

Designed Circuit

FIGURE 7.1
Outline of the IC simulation flow.

of California, Berkeley, in the late 1960s and continued until the 1990s. The
commercial SPICE simulation tools used today by designers (e.g., HSPICE
[Synopsys], SPECTRE [Cadence], ELDO [Mentor Graphics]) are all based upon
the original SPICE simulation tool developed at the University of California.
All of these simulators internally use appropriate device models for faithful
description of behaviors of the devices used in the circuit. Thus the use of
appropriate device models, not the internal algorithms, is responsible for the
success of a circuit simulation program [2]. The accuracy and reliability of a
circuit simulation process in predicting the device performances accurately
depend upon the accuracy of the internal device models.

7.2.2 Definition and Categories of Device Models

Device models are defined as the link between the physical world (technol-
ogy, manufacturing, etc.) and the design world (device simulation, timing
272 Technology Computer Aided Design: Simulation for VLSI MOSFET

simulation, etc.) of the semiconductor industry [3]. There are three categories
of device models: numerical models, look-up table models, and analytical or
compact models. The numerical models are based upon numerical solutions
of carrier transport equations, device geometry, and doping profile-related
equations. Although these techniques provide accurate results, they are
computationally very intensive. Therefore these techniques are not suitable
for simulation of large circuits. However, these may be used for exploration
of novel device structures and associated performances. The TCAD device
simulation tools as discussed in the earlier chapters are based upon this
approach. The look-up table approach, on the other hand, uses measured
device current and capacitances (and in some cases small signal parame-
ters) as functions of bias voltages and device sizes for characterizing device
performances that are subsequently used for circuit simulation purposes.
This approach is used when good physical models of any device are not
available and is sometimes used in fast circuit simulators. The most popular
approach that is used for circuit simulation purpose is the third approach
(i.e., the use of analytical or compact models). A compact model is charac-
terized by a set of mathematical equations whose parameters are used as
inputs to a SPICE-like circuit simulation program [3]. The physical compact
model equations are derived based upon the physics of the device. These
equations are expected to reproduce the device characteristics for differ-
ent device dimensions, range of temperature, process variations, etc. Good
physical compact models are usually complex because they consider several
physical phenomena. In order to make the equations simple so as to avoid
the convergence problem of the circuit simulator, some approximations are
sometimes judiciously made keeping the physics intact. Fitting parameters
are often introduced to improve the accuracy of the model. Apart from
accuracy, a desirable requirement from a compact model is some prediction
capability. This helps the designers to predict any statistical behavior of the
circuit and to explore circuit performances under migrated technology.

7.2.3 Commercially Used Compact Models

The development of a physical compact model for a MOS transistor began in
the 1970s. Since then, more than 100 models, including MOS 1, MOS 2, MOS 3,
MOS 9, PCIM, Level 28, ISIM, BSIM1 (Berkeley Short Channel IGFET Model),
BSIM2 and BSIM 3, BSIM 4, PSP (Pennsylvania State University’s Surface
Potential Model), HiSIM (Hiroshima University STARC IGFET Model), and
EKV (Enz-Krummenacher-Vittoz) have been reported. Out of them, BSIM3,
BSIM 4 PSP, HiSIM, and EKV are mostly used in commercial circuit simulators.
The basic idea behind the development of all of these models is to include exact
physics-based analytical equations in the model structure and then use fitting
parameters to calibrate the equations with measured results. The generations of
compact models have evolved to include more and more physical effects of the
transistor device and thus to make the models more and more accurate.
MOSFET Characterization for VLSI Circuit Simulation 273

In order to ease the task of circuit designers for predicting the circuit per-
formances with technology generation, predictive technology model (PTM)
has been developed by Zhao and Cao [4] based on physical models and early
stage silicon data. The PTM of bulk CMOS is successfully generated for 130 nm
to 32 nm technology nodes, with effective channel length as low as 13 nm.
These have been used in the present chapter for device characterization.

7.3 Threshold Voltage Characterization

Accurate characterization of threshold voltage is one of the most important
requirements for precise description of transistor behavior and the effect of
such behavior on circuit performances. It may be noted that all the commer-
cially available compact models mentioned earlier accurately characterize this
important quantity. Consequently, the SPICE simulation tool by using such
models properly takes care of the effects of threshold voltages of the indi-
vidual MOS transistors on the circuit performances. However, it is essential
for the designers to properly understand the behavior of this quantity under
varying bias conditions and geometry of the device, at least in general, in
order to intuitively justify the SPICE simulated performances of the circuits.

7.3.1 Threshold Voltage Characterization for

Long Channel MOS Transistor
Throughout this chapter, the discussion is centered on n-channel enhance-
ment mode transistor. In general, the conclusion drawn for an n-channel
MOS transistor equally holds true for p-channel MOS transistor, with rever-
sal of polarity of the bias voltages. Historically the source terminal is the con-
ventional voltage reference mostly due to the dominance of digital circuits
where source is considered as the reference voltage terminal.

7.3.1.1 Uniform Channel Doping

The schematic diagram of a long channel MOS transistor with uniformly
doped substrate is shown in Figure 7.2. The theoretical definition of thresh-
old voltage is based on the strong inversion condition. The threshold voltage
is defined as the gate voltage when the surface potential or band bending
reaches 2 Φ F and the silicon charge (the square root) is equal to the bulk
depletion charge for that potential [5]. This definition is valid for long chan-
nel MOS transistors. Based on the threshold voltage value, the operating
region of a MOS transistor is broadly divided into three parts: First, if the
applied gate bias is greater than the threshold voltage (VGS > V T), the inver-
sion charge density is larger than the substrate doping concentration and the
274 Technology Computer Aided Design: Simulation for VLSI MOSFET

SiO2

G Induced n-type channel

S D
n+ n+

Depletion
region B
Channel length L
p-substrate

FIGURE 7.2
Cross-sectional view of n-channel MOSFET.

transistor operates in a strong inversion region. In this region, drift current is

the dominant carrier transport mechanism. Second, if the applied gate bias
is much smaller than the threshold voltage (VGS > V T), the inversion charge
density is smaller than the substrate doping concentration and the transis-
tor operates in a weak inversion or sub threshold region. In this region, the
diffusion current is the dominant carrier transport mechanism. Last, if the
applied gate bias is very close to the threshold voltage, the inversion charge
density is close to the substrate doping concentration and the region of oper-
ation is called a moderate inversion region. In this region, both diffusion and
drift currents are equally important.
The threshold voltage of a long and wide channel MOS transistor with
uniform doping is given as [5]

QB
VT = VFB + 2 Φ F − (7.1a)
Cox

4εSi qN A Φ F
VT = VFB + 2 Φ F + (7.1b)
Cox

In (7.1a) and (7.1b), VFB is the flat band voltage, Φ F = kTq ln( NnAi ) is the Fermi
potential, NA is the uniform p-type substrate doping concentration, and Cox is
the oxide capacitance per unit area. QB is the depletion charge per unit area.
For NMOS transistor QB is negative, and for PMOS transistor QB is positive.
With the application of substrate bias VBS (<0 for NMOS and >0 for PMOS),
the bulk depletion charge region is widened and the threshold voltage is
increased as given as [5]:

2 ε Si qN A ( 2 Φ F − VBS )
VT = VFB + 2 Φ F + (7.2a)
COx
MOSFET Characterization for VLSI Circuit Simulation 275

This can be alternatively written as follows:

VT = VT 0 + γ ( 2 Φ F − VBS − 2 Φ F ) (7.2b)

Here the quantity V T0 is referred to as the zero substrate bias large geometry
threshold voltage. The factor

2 εSi qN A
γ= (7.3)
Cox

is referred to as the body-effect parameter. The substrate sensitivity is

defined as
dVT γ 2 qεSi N A
=− =− (7.4a)
dVBS 2 2 Φ F − VBS 2Cox 2 Φ F − VBS

At VBS = 0 , this is equal to

dVT 1 qεSi N A 1 εSi C

=− =− = − dm = −(m − 1) (7.4b)
dVBS Cox 4Φ F Cox Wdm Cox

In (7.4b), m is referred to as the body-effect coefficient, Wdm is the width of the

depletion region, and Cdm is the depletion capacitance.
This model is derived based on the assumption that the transistor is of
long channel length and width and the substrate doping concentration is
uniform. However, in current VLSI MOS transistors, the channel is doped
non-uniformly in both vertical and lateral directions. These are collectively
referred to as channel engineering. In addition, the channel lengths are
very short. Therefore, the basic model needs to be modified. The follow-
ing sub-sections describe how the vertical and lateral channel non-uniform
doping effects are incorporated in industry standard compact models.

7.3.1.2 Vertical Channel Engineering

In the process of making a VLSI MOS transistor, several ion implantation
doping process steps are required to adjust the threshold voltage and to sup-
press the punch-through and hot-carrier effects. The regions underneath
the interface are doped with various concentrations along the vertical direc-
tions. The schematic diagram of a VLSI MOS transistor using vertical chan-
nel engineering is shown in Figure 7.3(a).
A shallow implantation of channel dopants of the same type as substrate is
designed to obtain the desired threshold voltage value, and another deep implan-
tation of channel dopants of the same type as substrate is designed to suppress
the punch-through and drain-induced barrier lowering (DIBL) effect. A typical
high-to-low doping profile in the vertical direction and the corresponding step
276 Technology Computer Aided Design: Simulation for VLSI MOSFET

Lg
Spacer

G 1: Channel
2: Threshold voltage adjust
Lext TOX 3: SCE adjust
1 4: Punch through control
S 2 D
3
4

(a)

NCH
Substrate Doping Concentration

Step
approximation

Doping profile
NSUB

XT Depth

(b)

FIGURE 7.3
(a) A MOS transistor illustrating vertical channel engineering. (b) High-to-low channel doping
profile.

function approximation are shown in Figure 7.3(b). With non-uniform vertical

doping, the body bias coefficient γ becomes dependent on substrate bias.
Contrary to the uniform doping concentration NA, the doping concentra-
tion in the channel region is denoted by NCH and that in the deep substrate
region is NSUB. Two body-effect parameters γ1 and γ2 are to be defined by
substituting appropriate concentrations in (7.3). However, this makes the
expression for threshold voltage difficult to compute. Therefore, a compact
representation of threshold voltage in the presence of a non-uniform vertical
doping profile as used in BSIM4 is given by [6]

VT = VT 0 + K1 ( )
2 Φ F − VBS − 2 Φ F − K 2VBS (7.5)

In (7.5), K1 and K 2 are the two key parameters responsible for characterizing
the vertical non-uniform channel doping effects. The values of these coef-
ficients are determined by fitting (7.5) to measured threshold voltage data.
MOSFET Characterization for VLSI Circuit Simulation 277

7.3.1.3 Halo/Pocket Implantation
For suppression of short channel effects, local high doping concentration
regions near the source and drain junction edges are generally employed.
This is known as lateral channel engineering or halo/pocket implanta-
tion. With this type of channel engineering, the doping concentration in
the channel along the channel length becomes non-uniform. The schematic
diagram of a VLSI MOS transistor using lateral channel engineering is
shown in Figure 7.4(a). The lateral non-uniform doping with higher doping

Lg Spacer

Gate G
Lext TOX

Xj SDE
Xjd
Halo DSD

Body B

(a)

NP NP
N (x)

NCH
Lx Lx

Position Along the Channel

(b)

FIGURE 7.4
(a) A MOS transistor illustrating lateral channel engineering. (b) Step doping profile approxi-
mating the variation of the channel concentration from source to drain side.
278 Technology Computer Aided Design: Simulation for VLSI MOSFET

concentration near the source/drain regions results in an increase in the aver-

age doping concentration in the channel and in turn results in an increase in
the threshold voltage. This is sometimes referred to as reverse short channel
effect (RSCE), because it helps to compensate charge sharing effects from the
source/drain fields [7].
The lateral non-uniform doping concentration is approximated by a step
doping profile along the channel, as shown in Figure  7.4(b). The average
channel doping is given by [7,8]

N CH ( L − 2 Lx ) + N P 2 Lx  L N − N CH   L 
N eff = = N CH  1 + 2 X P ≅ N CH  1 + PE0 
L  L N CH   L 

(7.6)

In (7.6), NP is the pocket concentration. LPE0 is a fitting parameter extracted,

whose value is to be extracted from the measured data. With the introduction
of lateral doping, the threshold voltage model in (7.5) is modified as follows [8]:

VT = VT 0 + K1 ( 2 Φ F − VBS − 2 Φ F ) 1+
LPEB
L
− K 2VBS

 L 
+ K1  1 + PE 0 − 1 2 Φ F (7.7)
 L 

In (7.7) the following BSIM4 model parameters are identified:

• K1 and K 2 model the effects of a non-uniform vertical channel dop-

ing profile on threshold voltage.
• LPE0 and LPEB model effects of non-uniform lateral channel doping
profile on threshold voltage. LPEB models V T(VBS) dependence.
• At zero substrate bias, only the term LPE0 represents lateral non-unifor-
mity, and as the channel length is reduced, due to the fourth term, the
threshold voltage increases. This is significant for a short channel MOS
transistor.

7.3.2 Threshold Voltage Characterization for

Short Channel MOS Transistor
The threshold voltage of a long channel device is found to be independent
of the channel length and the applied drain voltage. However, in short chan-
nel devices, it has been experimentally found that the threshold voltage of a
MOS transistor decreases as the channel length is reduced or the drain bias
is increased. This effect is known as the short channel effect [5,7]. In addi-
tion, the dependence of the threshold voltage on the body bias becomes weak
as the channel length is reduced.
MOSFET Characterization for VLSI Circuit Simulation 279

The long channel theory of MOS transistor is based upon the assumption
that the depletion charge underneath the gate is controlled by the vertical
electric field due to the applied gate bias. However, in a short channel device
the channel length is comparable to the MOS depletion width in the vertical
direction, and the source-drain potential has a significant effect on the band
bending over a major portion of the device. The earlier assumption related
to long channel device does not remain valid for short channel devices. The
depletion charge under the gate is actually induced by the gate together with
the source and the drain. Therefore, the channel charge may be considered
to be shared by the gate as well as the source and drain. This is illustrated in
Figure 7.5(a). Consequently, smaller gate voltage is required to induce inver-
sion in short channel MOS transistors compared to long channel transistors.

Lg

Gate
L
Gate oxide

n+ source n+ drain

Depleted by source Depleted by drain

Body
(a)

Curve A: L = 6 µm
Vds = 0.5 V
Surface Potential

Curve B: L = 1 µm
Vds = 0.5 V

Curve C: L = 1 µm
Vds = 5 V

25 mV
y/L
0.25 0.5 0.75 0.9

(b)

FIGURE 7.5
(a) Sharing of gate depletion charge by source and drain. (b) Variation of surface potential to
lateral distance (normalized to the channel length L) for three different cases highlighting the
reduction of the source-drain potential barrier for lower channel length and higher drain bias.
280 Technology Computer Aided Design: Simulation for VLSI MOSFET

This leads to a smaller value of threshold voltage in short channel transis-

tors compared to long channel transistors. This approach of explaining short
channel effect is referred to as the charge sharing approach [7].
The decrease in the threshold voltage due to the reduction of channel length
and increase in the drain bias can be explained by considering the surface
potential. As the channel length decreases and the drain bias increases, the
potential barrier (p-type region) between the source and the drain for the
carriers (electrons) is lowered. Hence, less gate voltage is required to bring
the surface potential to 2 Φ F .
In effect the threshold voltage is lowered. This is called DIBL [5,7]. The con-
cept of DIBL is explained in Figure 7.5(b), illustrating the surface potential
plots along the channel for three different (long and short channel) devices
[5]. It is observed that with small channel length and high drain bias, the
potential barrier between the source and the drain is the lowest.
The short channel effect in threshold voltage is incorporated in a BSIM4
compact model as follows [8]:

VT = VT 0 + K1 ( 2 Φ F − VBS − 2 Φ F ) 1+
LPEB
L
− K 2VBS

 L 
+ K1  1 + PE 0 − 1 2 Φ F + VT (7.8)
 L 

In (7.8), ΔV T represents the reduction of threshold voltage due to short chan-
nel effect. A simple and accurate model, derived in [9] is

[2(Vbi − ψ s ) + VDS ]
VT = −

L
2 cosh lefft − 1 (
(7.9a)
)
Through several approximations, (7.9a) reduces to [7]
−L
VT = −[3(Vbi − ψ s ) + VDS ]e lt (7.9b)

In (7.9a) and (7.9b), Vbi is built-in potential of the source/drain (S/D) junction.
This is given by
kT  N DEP N SD 
Vbi = ln   (7.10)
q  ni2

In (7.10), NDEP is the channel concentration at the edge of the depletion bound-
ary, and NSD is the source-drain doping concentration. In (7.9a), lt represents
the characteristic length given as

εSi toxWdm
lt = (7.11)
ε ox η

MOSFET Characterization for VLSI Circuit Simulation 281

In (7.11), Wdm/η represents the average depletion width in the channel. In

order to improve the flexibility of the model equations over different tech-
nology generations, several fitting parameters are introduced. The following
equations are used in BSIM4 to represent SCE and DIBL, respectively [8]

0.5DVT 0
VT ( SCE ) = − L [Vbi − ψ s ] (7.12)
cosh(DVT 1 ⋅ lefft ) − 1

The characteristic length is given by

εSi toxWdm
lt = ( 1 + DVT 2 ⋅ VBS ) (7.13)
ε ox

The DIBL effect is modeled in BSIM as follows [8]:

0.5
VT ( DIBL ) = − ( ETA0 + ETAB ⋅ VBS ) VDS (7.14)
cosh(DSUB ⋅ Leff /lt 0 ) − 1

εSi toxWdm
lt 0 = (7.15)
ε ox

2 ε Si ψ s
Wdm = (7.16)
qN DEP

In these, DVT0, DVT1, DVT2, DSUB, ETA0, and ETAB are the SPICE BSIM4
model parameters whose values are to be extracted from measured data.
DVT2 and ETAB account for the body bias effect on short channel effect and
DIBL, respectively.

7.3.2.1 Short Channel Effect Reduction

It is observed that the threshold voltage roll-off is dependent upon the
characteristic length lt as defined in (7.11). It is well known that the roll-off
decreases with reduction in S/D junction depth Xj. However, this term has
not been included in the model. Following Brews’ approach [10], the charac-
teristic length is redefined as

( )
1/3
2
lt ∝ X j toxWdm (7.17)

Therefore, in order to have V T less sensitive to charge sharing and DIBL

effect, X j, tox, and Wdm should be reduced.
282 Technology Computer Aided Design: Simulation for VLSI MOSFET

7.3.3 Techniques for Threshold Voltage Extraction

This sub-section outlines three commonly used approaches for extraction
of the threshold voltage value from the measured drain current versus gate
voltage transfer characteristics. A good review of these techniques including
the background theory and others is provided in [11].

7.3.3.1 Constant Current Method

In the constant current method, the threshold voltage is evaluated as the
value of the gate voltage, corresponding to a given arbitrary constant drain
current IDS and drain voltage VDS < 100 mV . A typical value for this arbitrary
constant drain current is (Wm/Lm ) × 10−7 A, where Wm and Lm are the mask
channel width and length, respectively. Because of its simplicity, this is the
most widely used method in industry. However, this method has a serious
drawback of being totally dependent on the arbitrary chosen value of the
drain current.

7.3.3.2 Extrapolation in the Linear Region Method

The extrapolation in the linear region method is another very popular
method for extracting the threshold voltage from the measured transfer
characteristics of a MOS transistor. Both the drain current and the linear
transconductance are degraded significantly at high gate voltages because
of the decrease of mobility with the increasing normal field. The technique
consists of determining the gate voltage intercept (i.e., I DS = 0 ) of the linear
extrapolation of the I DS − VGS curve at its maximum first derivative point (i.e.,
the point of maximum transconductance). This is referred to as the linearly
extrapolated threshold voltage VON . VON is obtained by subtracting VDS/2
from the intercept. The main drawback of this method is that the maximum
slope point is often slightly greater (∼2 kT/q − 4 kT/q) than the threshold volt-
age V T at ψ s (inv) = 2 Φ F due to mobility degradation effects and the presence
of significant source and drain series parasitic resistances.

7.3.3.3 Second Derivative Method

In this method, the threshold voltage is determined as the gate voltage at which
the derivative of the transconductance (dg m/dVGS = d 2 I D/dVGS
2
) is maximum.

7.3.4 Simulation Results and Discussion

In this sub-section the discussion on characterization of threshold voltage
for VLSI MOS transistors is reviewed through SPICE simulation results. In
the subsequent discussion considerably long channel width is considered
so as to avoid the narrow channel width effect on the threshold voltage.
MOSFET Characterization for VLSI Circuit Simulation 283

7.3.4.1 Simulation Setup
For all the simulation results provided in this chapter, conventional bulk
NMOS transistor has been selected. A 45-nm technology node has been
selected, and the drawn channel length of the transistor is taken to be 65
nm, if not mentioned otherwise. The supply voltage is taken to be 1 V. The
physical oxide thickness is 1.1 nm and the electrical oxide thickness is 1.75
nm, considering poly-depletion effect and inversion layer thickness. The
substrate is uniformly doped with concentration equal to 3.24E18/cm3. The
source/drain concentration is 2E20/cm3. The source/drain junction depth
is 14 nm. The HSPICE simulation tool has been used to obtain all the simu-
lation results, with BSIM4 as the compact model. The model parameters
of the corresponding predictive technology model [4] have been taken for
simulation purposes.

7.3.4.2 Threshold Voltage Characterization with Substrate Bias Effect

The variation of threshold voltage of a large geometry MOS transistor
(W = L = 10 µm) is shown in Figure  7.6(a). It is observed that the threshold
voltage increases from its zero substrate bias value as the substrate voltage is
increased. The value of zero substrate bias long geometry threshold voltage
VT 0 as observed from Figure 7.6(a) is 0.466 V. The threshold voltage variation
with substrate bias follows (7.5). Noting the values of the necessary model
parameters from the model file, the theoretical curve is drawn and com-
pared with the simulation results. It is observed that the theoretical curve
closely follows the simulation results.
The variation of the substrate sensitivity of threshold voltage with the sub-
strate bias is shown in Figure 7.6(b). The sensitivity obtained from theoretical
formulation is also shown in Figure 7.6(b).

7.3.4.3 Threshold Voltage Characterization for Short Channel Transistors

The variation of threshold voltage with channel lengths of a MOS transistor
is shown in Figure 7.7(a). It is observed that as the channel length is reduced
from 100 nm onwards, the threshold voltage reduces. This is referred to
as the threshold voltage roll-off. The effect is more pronounced when the
applied drain bias is high. This is demonstrated in Figure 7.7(b). The amount
of threshold voltage roll-off as observed from the simulation results for dif-
ferent substrate bias and drain bias are summarized in Table 7.1. It is observed
that with the increase in substrate bias, the short channel effect increases.
This is easy to understand considering the fact that with the increase in sub-
strate bias, the depletion width increases and consequently the short channel
effect increases as suggested in Brew’s relation.
The DIBL effect is shown in Figure 7.8. The DIBL coefficient η is defined as
the slope of the curve ( η = T ( DS ) 0.9T ( DS
V V = 1V − V V = 0.1V )
). From simulation results, its
284 Technology Computer Aided Design: Simulation for VLSI MOSFET

0.66
VDS = 50 mV Theoretical
0.64 VGS = 1 V Simulation

0.62

0.60

0.58
VT (V)

0.56

0.54

0.52

0.50

0.48

0.46

0.0 –0.2 –0.4 –0.6 –0.8 –1.0

VBS (V)

(a)

–0.14
VDS = 50 mV Theoretical
VGS = 1 V Simulation
–0.15

–0.16
dVT /dVBS

–0.17

–0.18

–0.19

–0.20

0.0 –0.2 –0.4 –0.6 –0.8 –1.0

VBS (V)

(b)

FIGURE 7.6
(a) Variation of threshold voltage with substrate bias for n-channel MOS transistor. (b) Substrate
sensitivity of threshold voltage.
MOSFET Characterization for VLSI Circuit Simulation 285

VBS = 0 V
VDS = 50 mV
VBS = –0.5 V
660
VBS = –1 V
640

620

600

580
VT (mV)

560

540

520

500

480

460
0.0 –0.2 –0.4 –0.6 –0.8 –1.0
L (µm)
(a)

VDS = 1 V
470 VBS = 0 V
VDS = 50 mV
465
VBS = 0V
460

455
VT (mV)

450

445

440

435

430

0.0 0.2 0.4 0.6 0.8 1.0

L (µm)
(b)

FIGURE 7.7
(a) Threshold voltage roll-off for low drain bias. (b) Simulation results showing that the thresh-
old voltage roll-off increases with increased drain bias.
286 Technology Computer Aided Design: Simulation for VLSI MOSFET

TABLE 7.1
Amount of Threshold Voltage Roll-Off at Low and High Drain Bias
for Different Substrate Bias
VDS = 50 mV VDS = 1V
Roll-Off VBS = 0 V VBS = –0.5 V VBS = –1 V VBS = 0 V
ΔVT(mV) 1.55 1.70 1.86 32.16

value is found to be 0.0342, and the theoretical value as calculated from the
model discussed earlier is 0.0346.

7.3.4.4 Threshold Voltage Extraction

The threshold voltage extraction method through extrapolation in the linear
region method is shown in Figure 7.9 and that through the second derivative
method is shown in Figure 7.10. The threshold voltage as extracted from the
constant current method, linear extrapolation method, and second deriva-
tive method for low drain bias and different substrate bias are summarized

L = 65 nm (VBS = 0 V)
VGS = 1 V
L = 65 nm (VBS = –0.5 V)
L = 65 nm (VBS = –1 V)
640 L = 1 um (VBS = 0 V)
620
600
580
560
VT (mV)

540
520
500
480
460
440
420
0.0 –0.2 –0.4 –0.6 –0.8 –1.0
VDS (V)

FIGURE 7.8
Simulation results illustrating the DIBL effect.
MOSFET Characterization for VLSI Circuit Simulation 287

VDS = 50 mV VBS = –1 V
2.0 m
VBS = –0.5 V
1.8 m VBS = 0 V
1.6 m

1.4 m

1.2 m

1.0 m
ID (A)

800.0 µ

600.0 µ

400.0 µ

200.0 µ

0.0

–200.0 µ
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.9
Threshold voltage extraction: extrapolation in the linear region method.

VBS = –1 V
VDS = 50 mV VBS = –0.5 V
25.0 m VBS = 0 V

20.0 m

15.0 m
dgm/dvGS (s/v)

10.0 m

5.0 m

0.0

–5.0 m

–10.0 m

0.0 0.2 0.4 0.6 0.8 1.0

VGS (V)

FIGURE 7.10
Threshold voltage extraction: second derivative method, evaluated at VDS = 50 mV.
288 Technology Computer Aided Design: Simulation for VLSI MOSFET

TABLE 7.2
Threshold Voltage Value Extracted through Different Methods
Extracted Value of the Threshold Voltage at
VDS = 50 mV. W = 10 μm L = 65 nm
Method VBS = 0 V VBS = –0.5 V VBS = –1 V
Constant current 0.457 V 0.559 V 0.645 V
Linear extrapolation 0.409 V 0.502 V 0.583 V
Second derivative 0.462 0.558 0.636

in Table 7.2. For the constant current method, the constant current is taken to
1 μA, the channel width is 10 μm and the channel length is 65 nm.

7.4 I-V Characterization
Precise knowledge of the I-V characteristics of a MOS transistor is a basic
requirement for a good VLSI designer. The fundamental current transport
equations are introduced, followed by channel charge, mobility, and veloc-
ity saturation effects. The I-V models for long and short channel devices are
derived, followed by some advanced issues.

7.4.1 Current Density Equations

The total current density is the sum of the drift current density and the dif-
fusion current density, written as

dn
J n = qnµ n ξ + qDn (7.18a)
dx
dp
J p = qpµ p ξ − qDp (7.18b)
dx

The total conduction current density is thus J = J n + J p . The diffusion coef-

ficients Dn and Dp for electrons and holes are related to the corresponding
mobilities µ n and µ p through Einstein’s relationship [5]. Thus the current
densities are written as follows:

dn
J n = qnµ n ξ + kT µ n (7.18c)
dx

dp
J p = qpµ p ξ − kT µ p (7.18d)
dx
MOSFET Characterization for VLSI Circuit Simulation 289

The electric field ξ, which is defined as the electrostatic force per unit charge,
is written as ξ = − dψ i/dx. It may be noted that gradual channel approximation
has been assumed, according to which the variation of the electric field in the
y-direction (along the channel) is much less than that in the x-direction (perpen-
dicular to the channel). With this the conduction current densities are written as

dφn
J n = − qnµ n (7.19a)
dx

dφ p
J p = − qpµ p (7.19b)
dx

The quasi-Fermi potentials φn and φ p are defined as [5]

kT  n 
φn ≡ ψ i − ln   (7.20a)
q  ni 

kT  p 
φp ≡ ψ i + ln   (7.20b)
q  ni 

The electron current density at a point (x,y) in the channel is

dVCS ( y )
J n ( x , y ) = − qµ n n( x , y ) (7.21)
dy

Here VCS(y) is the quasi-Fermi potential. The total current at any point y
along the channel is
xi
dVCS
∫
I DS ( y ) = qW µ n n( x , y )
dy
dx (7.22)
0

The integration is carried out from x = 0 to x = xi, the bottom of the inversion
layer where ψ = Φ F . There is a sign change as the drain current flows in the
negative y direction. The inversion charge density is defined as
xi

∫
Qinv ( y ) = − q n( x , y ) dx (7.23)
0

With this the drain to source current is given as

VDS
W
I DS = µn
L ∫ [ −Q inv (V )] ⋅ dVCS (7.24)
0
290 Technology Computer Aided Design: Simulation for VLSI MOSFET

Inversion layer xt tox

– – – – – – y
n+ S n+ D
xb
x
Wdm

B
Depletion layer

FIGURE 7.11
Inversion layer forms one capacitor with the gate and another capacitor with the body. Surface
mobility is a function of the average electric fields at the top and the bottom of the inversion
charge layers.

The quasi-Fermi potential VCS ( y ) = 0 at y = 0(source) and VCS ( y ) = VDS at y =

L(drain).

7.4.2 Channel Inversion Charge Density

With reference to Figure 7.11, the following assumption is made. The inver-
sion layer in the channel of a MOS transistor is a sheet of charge and there is
no potential drop or band bending across the inversion layer. This is referred
to as the charge sheet approximation [5]. This inversion layer forms a capaci-
tor with the gate, the oxide being the dielectric. Also it forms another capaci-
tor with the body, the depletion layer being the dielectric. Thus the inversion
layer is coupled with both gate and substrate of the transistor. The inversion
charge density in strong inversion is given by

Qinv = −[Cox (VGS − VCS ( y ) − VT 0 ) + Cdm (VBS − VCS ( y ))] (7.25)

Simplification of (7.25) leads to the following expression for inversion

charge density:

Qinv = −Cox (VGS − mVCS ( y ) − VT ) (7.26)

where

Cdm 3t
m ≡ 1+ α = 1+ = 1 + ox (7.27)
Cox Wdm

Cdm
In (7.26), VT = VT 0 − Cox VBS = VT 0 − αVBS = VT 0 − (m − 1)VBS has been taken
using (7.4b).
MOSFET Characterization for VLSI Circuit Simulation 291

As defined earlier, m is referred to as the body-effect coefficient.* The value

of m is typically 1.2, however, it can be taken to be unity for simplified cal-
culations. Clearly the bulk charge factor is closely related to the body-effect
parameter, as observed also from (7.4b).
The inversion charge density in the weak inversion region is given by [7]

qεSi N CH  ψ − 2 Φ F − VCS 
Qinv  − UT exp  s  (7.28)
4Φ F  UT

In (7.28), UT = kT/q is the thermal voltage, and N CH is the effective channel

concentration.

7.4.3 Carrier Mobility Degradation Model

In the inversion layer of a MOS transistor, the current flow is determined by
the surface mobility, whose value is much lower than the bulk mobility of the
carriers. This is because of several mechanisms of scattering, primarily the
phonon or the lattice scattering, the coulombic scattering, and the surface
roughness scattering [5]. For good quality interfaces, phonon scattering is
the dominant mechanism at room temperature.
The surface mobility is a function of the average of the electric fields at the
top and the bottom of the inversion charge layer. These fields are shown in
Figure 7.11.
From Gauss’s law using the depletion layer as the Gaussian box, it is pos-
sible to write

QB Cox (VT − VFB − 2 Φ F )

ξ xb = = (7.29a)
εSi εSi

Considering the Gaussian box to be a box that encloses both the depletion
and the inversion layer, we have

QB + Qinv
ξ xt = (7.29b)
εSi

From (7.29a) and (7.26), we have, after substitutions,

Cox
ξ xt = (VGS − VFB − 2Φ F ) (7.29c)
ε Si

It is to be noted that the effect of the lateral field is ignored and m = 1 for simplicity.
* Some authors refer to this as the bulk-charge factor.
292 Technology Computer Aided Design: Simulation for VLSI MOSFET

The average electric field is defined as

1
ξ eff = (ξ xb + ξ xt ) (7.30)
2

Substituting from (7.29a) and (7.29c), and after some simplifications for n+
poly-gate n-channel MOS transistor

VGS + VT + 0.2V
ξ eff = (7.31)
6tox

Physically, ξeff means the average electric field experienced by the carriers in
the inversion layer. The dependence of the surface mobility of the carriers on
this average electric field and hence on the gate bias is given by the following
empirical relationship [3]:

µ0
µs =
( ) (7.32)
υ
ξ eff
1+ ξ0

In (7.32), µ0 is the low field surface mobility, ν is a constant whose value is

~1.85 for electrons at the surface, and ~1.0 for holes at the surface. ξ0 is the
critical electric field (~0.9 MV/cm for electrons at surface and ~0.45 MV/cm
for holes at the surface). The model proposed in (7.32) fits experimental data
well, but because it involves a power function, it is difficult to integrate the
model in a circuit simulation program. A Taylor series expansion of (7.32)
and retaining only up to three terms, the following expression for the verti-
cal field mobility degradation model is derived:

µ0
µs = (7.33)

1 + UA ( VGS + VT
tox )+U ( B tox )
VGS + VT 2

In (7.33), UA and UB are two parameters, whose values are to be extracted

from the experimental I-V data. The substrate bias dependence of the mobil-
ity is incorporated by introducing another parameter UC in (7.33). With this,
the model becomes [6]

µ0
µs = (7.34)

1 + (U A + U C .VBS ) ( VGS + VT
tox )+U (B tox )
VGS + VT 2

µ0
µs =

1 + U A ( VGS + VT
tox )+U ( B
VGS + VT 2
tox )  (1 + U VC BS )
(7.35)
MOSFET Characterization for VLSI Circuit Simulation 293

These two different models are incorporated in SPICE simulator by using suit-
able mobility selector flags. It may be noted that all the mobility degradation
models discussed above include the effect of vertical electric field only. It is
observed that the mobility in a strong inversion region is a function of the
gate bias. In the subthreshold region, the variation of Qinv with VGS cannot
be modeled accurately. Therefore, μs becomes constant in the subthreshold
region.

7.4.4 Carrier Velocity Saturation Model

Carrier velocity is another important physical phenomenon that critically
affects the I-V characteristics of a short channel VLSI MOS transistor. If the
lateral electric field is small, the drift velocity of the carriers is given by

vd = µ s ξ y (7.36)

In (7.36), µs is the surface mobility and is independent of the lateral field ξy.
However, as the lateral field ξy becomes high, the carrier velocity no longer
follows (7.36). With the increase of the lateral field, the kinetic energy of the
carrier increases. When the energy of the carrier exceeds the optical phonon
energy, an optical phonon is generated by the carrier, and in this process
the carrier loses its velocity significantly. Consequently, the kinetic energy
and therefore the drift velocity of the carriers cannot exceed a certain value.
This limiting velocity is called the saturation velocity. The vd-ξy relationship
is illustrated in Figure 7.12. An accurate model for the drift velocity is given
by [3]

µsξy
vd =
( ) 
1/α
1 + ξy α (7.37)
 ξ sat
Carrier Velocity (cm/s)

Lateral Field (×104 V/cm)

FIGURE 7.12
Carrier velocity saturation.
294 Technology Computer Aided Design: Simulation for VLSI MOSFET

In (7.37), α = 2 for electrons and α = 1 for holes. ξsat is the critical electric field
at which the carrier velocity becomes saturated and is linked with the satu-
ration drift velocity of the carrier as ξsat = 2vdsat/µs. For electrons, vdsat varies
between ~6–10 × 104 m/s and that for holes between ~4–8 × 104 m/s. The model
presented in (7.37) fits experimental data well but suffers from the drawback
that it is computationally difficult to be incorporated in any circuit simulation
program. In BSIM, a piece-wise velocity-field relationship is thus suggested.
This is as follows [6]:

µsξy 2 vdsat
vd = ξy
ξ y < ξ sat ξ sat =
1+ ξ sat
µs
(7.38)
vd = vdsat ξ y ≥ ξ sat

This model is in accordance with the experimental data.

7.4.5 Basic MOSFET I-V Model

Substituting (7.26) in (7.24) and carrying out the simple integration, we get
the following expression as the basic MOSFET I-V model:

W m 2 
I DS = µ ns Cox (VGS − VT )VDS − VDS  (7.39)
L  2

The following observations are made from (7.39):

• The drain current is proportional to the channel width W, surface

electron mobility µ ns , lateral electric field VDS/L, and the average
inversion charge density   Cox (VGS − VT − mVDS/2) .
2
• When the applied drain bias is small, the term VDS /2 can be
neglected so that the drain current is linearly proportional to
the drain bias VDS , which means that the transistor is acting as
a resistor.
• As the drain bias increases, the average inversion charge density
dI DS
decreases and dV DS
decreases. By differentiating (7.39) w.r.t VDS and
putting equal to 0, we get

dI DS W
= µ ns Cox [(VGS − VT ) − mVDS ] = 0 at VDS = VDSsat
dVDS L
(7.40)
V − VT
VDSsat = GS
m
MOSFET Characterization for VLSI Circuit Simulation 295

• The drain current that flows when the drain bias is saturated is
referred to as the drain source saturation current. This is given as

W
Cox µ ns (VGS − VT )
2
I DSsat = VDS > VDSsat (7.41)
2 mL

V −V
• Substituting VDSsat = GSm T for VCS ( y ) in (7.26), it is found that the
inversion charge disappears at the drain side. This phenomenon is
referred to as pinch-off. After the pinch-off region in the channel,
there exists a depletion region. The electrons after reaching the
pinch-off region are swept down by the drain bias and thus constant
current flows, which is given by (7.41).
• Equations (7.39) and (7.41) form the basic I-V model for a long channel
MOS transistor. Because of its simplicity, these equations are widely
used by the designers for hand calculations. In addition, these are
used in first-generation SPICE models [3].
• The transconductance parameter is defined as

dI DS W
gm = = 2µ ns Cox I DS (7.42)
dVGS VDS
L

It is observed that when a MOS transistor operates in the strong

inversion region, the transconductance is proportional to the square
root of the drain current.

7.4.6 MOSFET I-V Model with Velocity Saturation

Assuming the inversion charge density to be given by (7.26), the drain cur-
rent from (7.24) is

VDS dVCS
W
∫ (VGS − mVCS − VT ) dy
I DS = µ ns Cox 1 dVCS (7.43)
L 1+ ξ sat dy
0

In (7.43), the velocity saturation effect given by (7.38) has been assumed and
ξ y = dVdyCS . Performing the simple integration, we arrive at the following
model for the I-V characteristics:

W 1 (V − V )V − m V 2 
I DS = µ ns Cox  GS T DS DS  (7.44)
L 1 + ξVsatDSL 2 

296 Technology Computer Aided Design: Simulation for VLSI MOSFET

Comparing (7.44) and (7.39), we see that

long channel I DS ( 7.39 )

I DS = (7.45)
1 + ξVsatDSL

Thus the effect of velocity saturation is to reduce the long channel drain cur-
rent by the factor 1 + ξVsatDSL . When VDS is small or L is large, this factor reduces
to 1 (i.e., velocity saturation becomes negligible). The drain current model in
(7.44) is valid before the carrier velocity saturates (i.e., in the linear or triode
region).
If the drain voltage (and hence the lateral electric field ξy) is sufficiently
high, the carrier velocity near the drain saturates. At this stage, the channel
may be considered to be split into two portions: one adjacent to the source
where the carrier velocity is field dependent, and the other near the drain
where the carrier velocity is saturated to vdsat. At the junction between these
two portions, the channel voltage is VDSsat , and the lateral electric field is ξsat.
Therefore, the saturation drain current is given as

I DSsat = WCox (VGS − VT − mVDSsat )vdsat (7.46)

Comparing (7.46) with (7.44), we arrive at the following expression for satura-
tion drain voltage:

1 m 1
= + (7.47)
VDSsat VGS − VT ξ sat L

The following observations are made from (7.46) and (7.47):

• When the channel length is large or the gate overdrive voltage

(VGS − VT ) is low, ξ sat L >> (VGS − VT ) , VDSsat ≈ (VGS − VT )/m, we arrive
at (7.40) (i.e., the long channel saturation drain voltage).
• For the very short channel transistor, ξ sat L << (VGS − VT ) , VDSsat ≈ ξ sat L
the drain current becomes

I DSsat = WCox vdsat (VGS − VT − mξ sat L) (7.48)

• Thus, I DSsat is linearly proportional to (VGS − VT ), instead of the long

channel quadratic dependence. In addition, I DSsat is proportional to
W but less sensitive to L.
MOSFET Characterization for VLSI Circuit Simulation 297

• The classical long channel model suggests that drain current satu-
rates when the inversion charge density becomes zero, a phenomenon
referred to as pinch-off. However, a more accurate description of the
cause of drain current saturation is that the carrier velocity reaches
its maximum value vdsat at the drain. Thus instead of the pinch-off
region, there is a velocity saturation region next to the drain where
the inversion charge density given as Qinv = Cox (VGS − VT − mVDSsat )
does not vanish.
• In order to increase I DSsat, there must be an increase in Cox (VGS − VT ).
This is achieved by reducing tox, minimizing V T, and increasing VGS.
The limit of tox is determined by oxide tunneling leakage and reli-
ability. On the other hand, the lower limit of V T is determined by the
leakage current in the OFF state. The maximum value of VGS is the
supply voltage VDD, which is determined by concerns over power
consumption and reliability.
• It may be noted that for low power analog circuit operations, gate
overdrive voltage (VGS − VT ) is often taken to be nearly 0.1 V and
assuming ξ sat = 6 × 10 4 V/cm and L = 50 nm, ξ sat L > (VGS − VT ), so that
the transistor exhibits some long channel characteristics and conse-
quently the long channel model may be used.

7.4.7 Parasitic Source Drain Resistance

It follows from (7.17) that for short channel effect immunity, the source/
drain junction depth must be reduced. Therefore, as shown in Figure 7.13,
extra processing steps are performed to produce the shallow S/D junction
extension between the deep junction and the channel. To further minimize
dopant diffusion, the doping concentration in the shallow S/D extension

Contact metal Silicide

Gate G
Lext TOX

DSD G
Silicide SDE SDE

S D
Body B
RS RD

FIGURE 7.13
Source/drain series resistance in the SDE region.
298 Technology Computer Aided Design: Simulation for VLSI MOSFET

is kept much lower compared to that in the deep S/D region. The shallow
S/D extension along with light doping leads to parasitic S/D resistance.
This is shown in Figure  7.13. The parasitic source and drain resistances
are important device parameters that critically affect the MOS transistor
performances. The drain current in the linear region with high gate bias
is severely degraded due to this resistance, because channel resistance is
lowest under such a bias condition. This is modeled in the presence of this
resistance as follows:

I DS0
I DS = (7.49)
1 + RSVIDS
DS 0

In (7.49), IDS0 is the intrinsic current expression given by (7.44). RS is the para-
sitic source resistance. It appears from (7.49) that the effect of the series resis-
tance is lowest in the saturation region, where VDS is high. A second effect of
this resistance is the increase of VDSsat, as follows:

VDSsat = VDSsat 0 + I DSsat (RS + RD ) (7.50)

In (7.50), RS and RD are the parasitic source and drain resistances, respectively.
Reducing the value of these resistances is thus an important task for both
circuit and device designers. A popular option is to cover the drain and
source regions with a low resistivity material such as titanium or tungsten.
This process is called silicidation and it effectively reduces the sheet resistance
of the S/D regions by a factor of 10. Another option to be used by the circuit
designer is to make the transistor wide. With a process that includes silicida-
tion and proper attention to layout, parasitic resistance may be reduced.

7.4.8 Output Resistance
A typical I-V curve and its output resistance are shown in Figure 7.14. The
drain current in the output I-V curve is divided into two parts: (1) the linear
region, in which the drain current increases with the drain voltage, and (2)
the saturation region, in which the drain current weakly depends upon the
drain voltage. However, the output resistance curve reveals more detailed
information about the various physical mechanisms involved in the satura-
tion region. The output resistance is the reciprocal of the derivative of the I-V
curve, and it is shown in Figure 7.14. The physical causes of such variation
of the output resistance are the influences of drain voltage on the threshold
voltage and a phenomenon called channel length modulation. The output
resistance is divided into four regions.
The first region is the linear or triode region. In this region, the output
resistance is very small because of the strong dependence of drain current
on drain voltage. The other three regions belong to the saturation region,
MOSFET Characterization for VLSI Circuit Simulation 299

Triode CLM DIBL SCBE

12
3.0
IDS (mA)

RO (kΩ)
1.5

0 1 2 4
VDS (V)

FIGURE 7.14
Typical behavior of MOSFET output resistance.

namely channel length modulation (CLM) region, DIBL region, and sub-
strate current induced body effect (SCBE) region. The SCBE results in a dra-
matic decrease in output resistance in the high drain bias region.
The drain current has a weak dependence on the drain voltage in the satura-
tion region. Therefore, by Taylor series expansion of I DS at VDS = VDSsat, we have

∂ I DS (VGS , VDS )
I DS (VGS , VDS ) = I DS (VGS , VDSsat ) + (VDS − VDSsat )
∂VDS

 V − VDSsat 
≡ I DSsat  1 + DS  (7.51)
 VA

In (7.51) we have

I DSsat = I DS (VGS , VDSsat ) = Wvdsat Cox (VGS − VT − mVDSsat ) (7.52)

−1
 ∂I 
VA = I DSsat  DS  (7.53)
 ∂VDS 

Here VA is called the Early voltage and is introduced for the analysis of out-
put resistance in the saturation region only. It is assumed that a specific Early
voltage parameter can be computed independently for each of the different
regions of the output characteristics, namely the CLM region, DIBL region,
and SCBE region. These can be calculated analytically; however for accuracy
it is better to determine them from measurement results.
300 Technology Computer Aided Design: Simulation for VLSI MOSFET

It is instructive for IC designers to use the following set of equations for all
sorts of hand analysis works.

W 1  m 2 
I DS = µ ns Cox (VGS − VT ) VDS − VDS VDS < VDSsat
L 1 + ξVsatDSL  2 

 V − VDSsat 
I DS = Wvdsat Cox (VGS − VT − mVDSsat )  1 + DS  VDS > VDSsat
 VA
ξ sat L (VGS − VT )
VDSsat =
mξ sat L + (VGS − VT )

(7.54)

The parameters VT and VA are to be extracted from measurements. For simplic-

ity, the value of the body-effect coefficient m may be considered to be unity.

7.4.9 Subthreshold I-V Model

When the applied gate voltage is smaller than the threshold voltage V T,
ideally the drain current is zero. However, this does not happen in real
devices and the drain current remains at a non-negligible level for several
tenths of a volt below V T. This occurs because the inversion charge density
does not drop to zero abruptly. Subthreshold characteristics are significant
in scaled CMOS digital applications, because they describe how a transis-
tor switches OFF. Thus, the subthreshold region, immediately below V T, in
which Φ F < ψ s < 2 Φ F is referred to as the weak inversion region. Contrary
to the strong inversion region, in which the drift current dominates,
subthreshold conduction is dominated by the diffusion current, arising
due to a gradient in minority carrier concentration. In weak inversion, an
n-channel MOS transistor operates as an n-p-n bipolar transistor, where
the source acts as the emitter, the substrate as the base, and the drain as
the collector.
The inversion charge density is repeated here from (7.28)

qεSi N CH  ψ − 2 Φ F − VCS 
Qinv  − UT exp  s  (7.55)
4Φ F  UT

In order to derive a relationship between ψ s and VGS , the following expan-

sion is made [12]:

∂VGS
VGS ≈ VGS ψ s = 1.5 ΦF + (ψ s − 1.5Φ F ) (7.56a)
∂ψ s
ψ s = 1.5 Φ F
MOSFET Characterization for VLSI Circuit Simulation 301

It is known that VGS = VT when ψ s = 2 Φ F . Therefore, from (7.56a), we have

∂VGS
VT = VGS ψ s = 1.5 ΦF + 0.5Φ F (7.56b)
∂ψ s ψ s = 1.5 Φ F

Therefore, from (7.56a) and (7.56b), we have

∂VGS
VGS = VT + (ψ s − 2 Φ F ) (7.56c)
∂ψ s ψ s = 1.5 Φ F

In addition, we have the following relationship:

VGS = VFB + ψ s + γ ψ s (7.57)

From (7.57),

∂VGS γ
= 1+ (7.58)
∂ψ s 2 ψs ψ s = 1.5 Φ F

Substituting the value of γ from (7.3) and considering,

εSi
Cdm = (7.59)
Wdm

with Wdm as given in (7.16), the following relationship is achieved:

∂VGS C
≈ 1 + dm ≡ n (7.60)
∂ψ s Cox

From (7.56c), (7.58), and (7.60), we get

VGS = VT + n(ψ s − 2 Φ F ) (7.61)

(7.61) is widely used for developing compact models in the subthreshold
region. Here n is referred to as subthreshold swing factor. It may be noted
that the subthreshold swing factor n is not equal to the body-effect coeffient m,
although very closely related. Substituting (7.61) in (7.55), we get

qεSi N CH  V − VT − nVCS 
Qinv  − UT exp  GS  (7.62)
4Φ F  nUT
302 Technology Computer Aided Design: Simulation for VLSI MOSFET

Substituting this in (7.24) and performing the simple integration, the follow-
ing expression for the subthreshold drain current is obtained:

W qεSi N CH 2  V − VT    −V  
I DS = µ n UT exp  GS 1 − exp  DS   (7.63)
L 4Φ F  nUT    UT  

This can be alternatively written as

 V − VT    −V  
I DS = I 0 exp  GS 1 − exp  DS   (7.64)
 nUT    UT  

In (7.64), I 0 is defined as

W qεSi N CH 2
I0 = µ 0 UT (7.65)
L 4Φ F

In (7.64), n is referred to as the subthreshold swing factor. From experimental

data it has been found that the subthreshold swing factor is a function of
channel length and the interface state density. The interface traps located
at the oxide-silicon interface exchange carriers with the silicon. The charge
trapped in them depends on the value of the surface potential ψ s. This is
modeled by an incremental capacitance in parallel with the depletion capaci-
tor. In addition, there are coupling capacitors between the drain/source and
channel. With these considerations, the subthreshold swing factor as defined
in (7.60) is modified in the BSIM compact model as follows [5,8]:

Cdm Cit + CDSC

m = 1 + NFACTOR + (7.66)
Cox Cox

The parameter NFACTOR as introduced in (7.66) is for compensating any

error while calculating the depletion width capacitance. The value of this
parameter is close to unity. Cit is the interface trap capacitance per unit area.
The capacitance CDSC is sensitive to the body bias as well as to the drain bias
that is incorporated in the model as follows:

0.5
CDSC = (CDSC + CDSCDVDS + CDSCBVBS ) (7.67)
cosh(DVT 1 ⋅ lLt ) − 1

This should be included in (7.66) for computing the exact value of the sub-
threshold swing factor. The various capacitance parameters in (7.67) are to
be extracted.
MOSFET Characterization for VLSI Circuit Simulation 303

7.4.10 Characterization of Poly-Silicon Gate Depletion Effect

The use of poly-silicon gates is considered as an advantage in modern CMOS
technology. This is because the source and drain regions can be self-aligned
to the gate, thus eliminating parasitic from overlay errors. The poly-silicon
is usually heavily doped to behave almost similar to that of metal. However,
in many process technologies, it is not possible to dope the poly-silicon gate
to arbitrarily high concentrations. Therefore, a thin depletion layer is formed
at the interface between the poly-silicon and the gate oxide, with the applica-
tion of gate voltage.

7.4.10.1 Reduction of Gate-Source Voltage

Although the depletion region is very thin, its effect cannot be ignored in
the deca-nanometer MOSFETs, because the gate oxide thickness is also very
small. This is especially critical with the dual n+-p+ poly-silicon gate process
in which the gates are doped by ion implantation. The effect of the presence
of such a depletion region is that the voltage drop across the gate oxide and
the substrate is reduced, because part of the gate voltage will be dropped
across the depletion region in the gate. Consequently, the effective gate volt-
age is reduced.
Figure 7.15 shows an n-channel MOS transistor with a depletion region in
the n+ poly-silicon gate. Let us assume that the doping concentration in the
poly gate near the interface is Np, and the potential drop across the depletion
region in the poly-silicon gate is ψ p . From the depletion approximation, the
depletion charge density in poly-silicon is

Qp = 2 qεSi N p ⋅ ψ p = Cox γ p ψ p (7.68)

Lg
Np
Poly gate depletion (width Wdp) n+ G
+ + + + + + + + +
TOX
+
S n – – – – – – – – – n+ D

Inversion layer Depletion in substrate (width Wdm)

FIGURE 7.15
Poly gate depletion phenomenon.
304 Technology Computer Aided Design: Simulation for VLSI MOSFET

In (7.68), ψp is the potential drop across the poly-silicon gate, and γp is given by

2 qεSi N p
γp = (7.69)
Cox

The potential balance equation is given by

VGS = VFB + ψ p + ψ ox + ψ s (7.70)

The potential drop across the oxide ψ ox in (7.70) is given by

Qp
ψ ox = = γ p ψ p (7.71)
Cox

While writing (7.71), it has been considered that the normal component of
electrical displacement is continuous across the interface. From (7.70) and
(7.71), the following quadratic equation can be derived:

1
(VGS − VFB − ψ s − ψ p )2 − ψ p = 0 (7.72)
γ 2p

Solving (7.72), and taking the positive root, the effective gate voltage is found
to be

γ 2p  4(VGS − VFB − ψ s ) 
VGS _ eff = VGS − ψ p = VFB + ψ s +  1+ 2
− 1 (7.73)
2  γp 

Substituting the value of γ p from (7.69) in (7.73),

2
qεSi N p tox  2 ε 2ox (VGS − VFB − ψ s ) 
VGS _ eff = VFB + ψ s +  1+ − 1 (7.74)
ε 2ox  2
qεSi N p tox 

It is observed that if tox = 30 A 0, the effective gate voltage can be reduced by

up to 10% due to the poly-silicon gate depletion effect. In a BSIM compact
model, N p is denoted by NGATE and is considered as a model parameter.

7.4.10.2 Effect on Threshold Voltage

Let us now investigate the effect of poly-silicon gate depletion on the thresh-
old voltage of a MOS transistor. The condition for charge balance is

QG = −(QB + Qinv ) (7.75)

MOSFET Characterization for VLSI Circuit Simulation 305

When the gate is positively biased, the positive charge on the gate is sup-
ported by the depletion charge due to the donor ions at the poly-Si/SiO2
interface of an n+ poly-silicon gate. From (7.68),

Qp2 QG2 (QB + Qinv )2

ψp = = = (7.76a)
γ 2p Cox
2
γ 2p Cox
2
γ 2p Cox
2

The potential drop across the oxide is
QG
ψ ox = (7.76b)
Cox

Substituting the values of ψ p and ψ ox from (7.76a) and (7.76b) in (7.70),

(QB + Qinv )2 (QB + Qinv )

VGS = VFB + ψ s + − (7.77)
γ 2p Cox
2
Cox

Considering the fact that at threshold, ψ s = 2 Φ F and Qinv → 0, the threshold
voltage in the presence of the poly depletion effect is given by

QB2
VT 0 p = VT 0 + 2 (7.78)
γ 2p Cox

Thus it is observed that due to the poly-silicon gate depletion effect, the
threshold voltage is increased by an amount

QB2 γ2
~ 2ΦF
γ 2p Cox
2
γ 2p

7.4.10.3 Effect on Oxide Thickness

Because a depletion layer is present in the gate, it may be thought that a poly-
silicon gate capacitor is added in series with the oxide capacitor. The effect of
this is that the oxide dielectric thickness is increased, such that the effective
oxide thickness is

tox = tox + ε ox Wdp = tox + Wdp (7.79)

εSi 3

In (7.79), Wdp is the poly-silicon gate depletion width that is related to the
potential drop in the depletion region through

2 εSi ψ p
Wdp = (7.80)
qN p

306 Technology Computer Aided Design: Simulation for VLSI MOSFET

7.4.10.4 Electrical Oxide Thickness

It may be noted in this connection that the charge sheet approximation con-
sidered in all calculations presented so far is not true in a fine sense. The
assumption that the inversion layer is infinitely thin therefore needs rigor-
ous consideration. To properly calculate the shape of the inversion region,
Poisson’s equation has to be solved simultaneously with Schrödinger’s equa-
tion, which governs the behavior of tightly confined particles. The average
location of the inversion charge below the Si-SiO2 interface is called the inver-
sion layer thickness tinv . Then the effective (often called the electrical oxide
thickness, in compact model terminology) that determines the capacitive
coupling between the gate and the channel charge becomes

t ox = tox + ε ox (Wdp + tinv ) = tox + Wdp + tinv (7.81)

εSi 3 3

The solution to the poly-silicon depletion effect is to dope the poly-silicon

heavily. However, very heavy doping may cause dopant penetration from the
gate through the oxide into the substrate. Poly-silicon gate depletion effect is
eliminated in advanced MOS technology by replacing the gate material with
a pure metal. NMOS and PMOS transistors may require two different metals
(with metal work functions close to those of n+ and p+ poly-silicon) in order to
achieve the optimal threshold voltage [13].

7.4.11 Simulation Results and Discussion

7.4.11.1 Variation of Drain Current, Transconductance,
and Output Resistance with Gate Voltage
The variations of drain current with applied gate bias and low drain bias
for three different substrate biases are shown in Figure 7.16. It is observed
from the figure when the gate bias is just above threshold voltage, the cur-
rent increases at a faster rate, compared to high gate bias. This is because
of the carrier mobility degradation phenomenon occurring at higher gate
bias. This is also demonstrated through Figure 7.17, which shows the varia-
tion of the transconductance with applied gate bias for low drain bias. The
same graphs plotted for high drain bias are shown in Figures 7.18 and 7.19,
respectively. It is observed that with high drain bias, the mobility degra-
dation phenomenon affecting the drain current is somewhat counterbal-
anced due to the high drift velocity of the carriers. The variation of output
resistance with applied gate bias is shown in Figure 7.20. It is observed that
when the transistor operates in the subthreshold region, the output resis-
tance is very high. This is simple to explain by considering the fact that in
the subthreshold region, a very small amount of drain current flows. On
the other hand, in a strong inversion region, the output resistance drops
and the value remains fairly constant with increase of gate bias.
MOSFET Characterization for VLSI Circuit Simulation 307

VDS = 50 mV VBS = –1 V
2.0 m
VBS = –0.5 V
1.8 m VBS = 0 V
1.6 m

1.4 m

1.2 m

1.0 m
ID (A)

800.0 µ

600.0 µ

400.0 µ

200.0 µ

0.0

–200.0 µ
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.16
Variation of drain current with applied gate bias for three different substrate biases and low
drain bias.

5.0 m
VDS = 50 mV VBS = –1 V
4.5 m VBS = –0.5 V
4.0 m VBS = 0 V

3.5 m

3.0 m

2.5 m
gm (s)

2.0 m

1.5 m

1.0 m

500.0 µ

0.0

–500.0 µ
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.17
Variation of transconductance with applied gate bias for three different substrate biases and
low drain bias.
308 Technology Computer Aided Design: Simulation for VLSI MOSFET

9.0 m
VDS = 1 V VBS = –1 V
8.0 m VBS = –0.5 V
7.0 m VBS = 0 V

6.0 m

5.0 m
ID (A)

4.0 m

3.0 m

2.0 m

1.0 m

0.0

–1.0 m
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.18
Variation of drain current with applied gate bias for three different substrate biases and high
drain bias.

20.0 m VDS = 1 V VBS = –1 V

18.0 m VBS = –0.5 V
VBS = 0 V
16.0 m

14.0 m

12.0 m

10.0 m
gm (s)

8.0 m

6.0 m

4.0 m

2.0 m

0.0

–2.0 m
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.19
Variation of transconductance with applied gate bias for three different substrate biases and
high drain bias.
MOSFET Characterization for VLSI Circuit Simulation 309

VDS = 0.8 V VBS = 0 V

600

500

400
Ro (kΩ)

300

200

100

0.2 0.4 0.6 0.8 1.0

VGS (V)

FIGURE 7.20
Variation of output resistance with gate bias.

7.4.11.2 Subthreshold Characteristics
The subthreshold characteristics for low drain bias and high drain bias
are shown in Figures  7.21 and 7.22, respectively. The three important per-
formance parameters, related to switching behavior of a MOS transistor,
extracted from the subthreshold characteristics are ION, IOFF, and subthres­hold
slope S, respectively. The ON and OFF currents are defined as the drain-
source current flowing through the transistor when the applied gate bias is
either high or zero, respectively. The subthreshold slope is determined as
S = (d(log 10 I DS )/dVGS )−1 = 2.3nkT/q (i.e., the amount of gate voltage required
to change the drain current by an order of magnitude). The values of these
three parameters are summarized in Table 7.3. From the results, the value of
the subthreshold swing factor n for the two drain biases are calculated and
shown in Table 7.3. Thus, the simulation results clearly demonstrate that high
drain bias (i.e., DIBL effect) deteriorates the subthreshold characteristics of a
MOS transistor.

7.4.11.3 Variation of Transconductance Generation Efficiency,

Intrinsic Gain, Linearity, and Cutoff Frequency
An important analog performance parameter of MOS transistor is the
transconductance generation efficiency that is measured as g m/I DS , which
310 Technology Computer Aided Design: Simulation for VLSI MOSFET

VDS = 50 mV VBS = –1 V
VBS = –0.5 V
VBS = –0 V
–2

–4
log (IDS) (A)

–6

–8

–10

–12
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.21
Subthreshold characteristics for low drain bias.

VDS = 1 V VBS = –1 V
VBS = –0.5 V
VBS = 0 V
–2

–4
log (IDS) (A)

–6

–8

–10

0.0 0.2 0.4 0.6 0.8 1.0

VGS (V)

FIGURE 7.22
Subthreshold characteristics for high drain bias.
MOSFET Characterization for VLSI Circuit Simulation 311

TABLE 7.3
ION, IOFF, and Subthreshold Slope S for an NMOS Transistor of L = 65 nm
and W = 10 μm
Drain Bias ION @VGS = 1V IOFF@VGS = 0V S m
VDS = 50 mV 1.56 mA 6.52 nA 94 mV/decade 1.596
VDS = 1 V 7.74 mA 18.4 nA 95.3 mV/decade 1.618

measures the amount of transconductance generated per unit drain cur-

rent. The variation of this parameter with applied gate bias is shown in
Figure 7.23. It is observed that the transconductance generation efficiency
is highest when the transistor works in a weak inversion region. As the
gate bias increases, such that the transistor moves on to a strong inver-
sion region, the value of this parameter reduces. This is because in the
weak inversion region, a very small amount of current flows through the
transistor so that the ratio of transconductance to drain current is high.
In a strong inversion region, the drain current increases so that the ratio
falls. Theoretically, the maximum value of this factor is found to be 1/nUT ,

VBS = –1 V (VT = 0.637 V)

VDS = 1 V
VBS = –0.5 V (VT = 0.558 V)
VBS = 0 V (VT = 0.465 V)
30

25

20
gm/ID (s/A)

15

10

–10
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.23
Variation of transconductance generation efficiency with gate bias for high drain bias and
different substrate biases.
312 Technology Computer Aided Design: Simulation for VLSI MOSFET

and from simulation results, this is 24.41 V–1 at VBS = 0 V. The effect of sub-
strate bias on the transconductance generation efficiency is also observed.
As the substrate bias increases (i.e., as the substrate becomes more reverse
biased), the depletion depth increases. Therefore, the depletion capacitance
reduces and hence the subthreshold swing factor also reduces. Thus the
ratio ( g m/I DS ) increases.
The intrinsic voltage gain of a MOS transistor is defined as g m R0 , where
R0 is the output resistance. The variation of output resistance and transcon-
ductance with applied gate bias is recalled in Figure 7.24(a). It is observed
that at low VGS, when the transistor operates in weak inversion, the trans-
conductance is low, but the output resistance is very high. The variation
of the intrinsic gain with the applied gate bias is shown in Figure 7.24(b).
Consequently, the intrinsic gain is high at the weak inversion region. As
the gate bias is increased, so that the transistor starts to operate in the
strong inversion region, the output resistance falls. Thus although the
transconductance increases, the intrinsic gain falls. The effect of output
resistance plays a significant role in determining the intrinsic gain of a
MOS transistor.
Non-linearity of a device is manifested by the presence of higher-order
harmonics at the output signal. The linearity of a MOS transistor is quanti-
fied in this work through the parameter VIP3. This is the extrapolated gate
voltage amplitude, at which the third harmonics of the drain current become
equal to the fundamental tone of the drain current [14]. This is mathemati-
cally defined as

gm
VIP3 = 24
|g m3|

Here

∂3 I DS
gm3 = 3
∂VGS

The variation of g m3 with applied gate bias is shown in Figure 7.25(a). The

VIP3 peak shown in Figure 7.25(b) is due to the second-order interaction
effect and can be explained as a cancellation of the third non-linearity
coefficient (i.e., g m3) (see Figure 7.25a) by device internal feedback around
a second-order non-linearity [14]. It is observed that the linearity of the
device is poor when it operates in a weak inversion region. Therefore, for
better linearity performance, the device must work in a strong inversion
region.
MOSFET Characterization for VLSI Circuit Simulation 313

VBS = 0 V Ro
VDS = 0.8 V gm
700 18

16
600
14
500
12

400 10
Ro (kΩ)

gm(mS)
8
300
6
200
4

100 2

0
0
–2
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

(a)

VDS = 0.8 V VBS = 0 V

28 VBS = –0.5 V
VBS = –1 V
26

24

22
gm*(Ro)

20

18

16

14

12
0.2 0.4 0.6 0.8 1.0
VGS (V)

(b)

FIGURE 7.24
(a) Variation of transconductance and output resistance with gate bias. (b) Variation of intrinsic
gain with applied gate bias for different substrate biases.
314 Technology Computer Aided Design: Simulation for VLSI MOSFET

VBS = –1 V (VT = 0.637 V)

VDS = 1 V VBS = –0.5 V (VT = 0.558 V)
0.5
VBS = 0 V (VT = 0.465 V)
0.4

0.3

0.2
d2gm/dvgs2 (s/v2)

0.1

0.0

–0.1

–0.2

–0.3

–0.4

0.0 0.2 0.4 0.6 0.8 1.0

VGS (V)

(a)

9 VDS = 1 V VBS = –1 V
VBS = –0.5 V
8 VBS = 0 V

5
VIP3 (V)

–1
0.0 0.2 0.4 0.6 0.8
VGS (V)

(b)

FIGURE 7.25
(a) Variation of second derivative of transconductance with applied gate bias. (b) Variation of
linearity parameter with applied gate bias.
MOSFET Characterization for VLSI Circuit Simulation 315

VDS = 1 V VBS = 0 V VT = 0.432 V

200.0 VBS = –0.5 V VT = 0.526 V
VBS = –1 V VT = 0.604 V
180.0

160.0

140.0

120.0
fT (GHz)

100.0

80.0

60.0

40.0

20.0

0.0

–20.0
0.0 0.2 0.4 0.6 0.8 1.0
VGS (V)

FIGURE 7.26
Variation of cutoff frequency parameter with applied gate bias.

The variation of the cutoff frequency with the applied gate bias is shown
in Figure 7.26. The cutoff frequency is also referred to as the unity current
gain frequency. This frequency determines the bandwidth of the circuit. It
is observed that the value of the cutoff frequency is very small when the
device operates in a weak inversion region, and it increases as the gate bias
increases so that it operates in a strong inversion region. It may be noted that
in a weak inversion region, the intrinsic gain of a MOS transistor is high but
the bandwidth is low. Therefore, operation in a moderate inversion region is
often preferred for low-power, high-performance analog applications.

7.4.11.4 Variation of Drain Current and Output Resistance with Drain Bias

Variations of the drain current and output resistance with applied drain
bias for three different gate biases are shown in Figure 7.27 and Figure 7.28,
respectively. It is observed from the graphs that in the subthreshold region,
the drain current is small so that the output resistance is high. On the other
hand, in the strong inversion region, the amount of drain current is high so
that the output resistance is low. For the weak inversion case, with the increase
of drain bias, the drain current increases due to various second-order effects
such as channel length modulation, DIBL effect, etc. Therefore, the output
316 Technology Computer Aided Design: Simulation for VLSI MOSFET

Vgs = 0.4
5.0 m Vgs = 0.6
Vgs = 0.8

4.0 m

3.0 m
IDS (A)

2.0 m

1.0 m

0.0

0.0 0.2 0.4 0.6 0.8 1.0

VDS (V)

FIGURE 7.27
Variation of drain current with applied drain bias for three different gate biases.

18.0 k
Vgs = 0.4
Vgs = 0.6
16.0 k
Vgs = 0.8
14.0 k

12.0 k

10.0 k
Ro (Ω)

8.0 k

6.0 k

4.0 k

2.0 k

0.0

0.0 0.2 0.4 0.6 0.8 1.0

VDS (V)

FIGURE 7.28
Variation of output resistance with applied drain bias.
MOSFET Characterization for VLSI Circuit Simulation 317

resistance value falls. However, for strong inversion, the increase of drain
current with the increase of drain bias due to the above effects is counterbal-
anced somewhat due to better gate control at high gate bias. Therefore, the
resultant rate of increase of drain current is small. Consequently, the output
resistance remains nearly constant.

7.5 Hot Carrier Effects Due to Impact Ionization

If the drain voltage (and hence the lateral electric field ξ y ) is sufficiently high,
the carrier velocity near the drain saturates. The length of the high field
region is a function of channel length, oxide thickness, and gate and drain
bias. Even by considering the scaling of supply voltage, the electric field in
the high field region is strong enough (10 4 V/cm). Consequently, the electrons
gain enough energy and collide with the bound electrons in the valence band
to create impact ionization of silicon lattice atoms in scaled MOS transistors.
These highly energetic electrons are referred to as hot electrons because if their
kinetic energy is expressed as kTe, then Te becomes as high as 1000 K, which is
much higher than the lattice temperature. As a result of the impact ionization
process, electron-hole pairs are generated. Among these pairs, the electrons
are collected by the drain which increases the drain current. On the other
hand, the holes are pushed toward the source, which in turn are directed
toward the substrate due to the action of the vertical electric field. This results
in an impact ionization induced substrate current as illustrated schematically
in Figure 7.29.

+VGS

+VDS
G

tox

n+S n+D

Depletion layer boundary

Substrate current
B

FIGURE 7.29
Substrate current due to impact ionization.
318 Technology Computer Aided Design: Simulation for VLSI MOSFET

The empirical relationship describing the impact ionization rate is given as [5]

 −B 
α i ( y ) = Ai exp  i  (7.82)
 ξy 

In (7.82), αi(y) is the number of ionization events per unit length, and Ai and
Bi are ionization constants. Thus the substrate current is given by
L L − Bi

∫ ∫
I sub = I DS α i ( y ) dy = Ai I DS e
ξy
dy (7.83)
0 0

The velocity saturation region is bounded by y = 0(saturation point) to y =

ΔL(drain). Also along the surface, the quasi-Fermi level V(y) increases from
VDSat at y = 0 to VDS at y = ΔL. From pseudo-two-dimensional analysis, an
exponential relationship between the lateral field ξ y and the lateral channel
distance can be derived [5], which is given below

 y
ξ y ( y ) = ξ sat cosh   (7.84)
 lt 

In (7.84), ξ sat is the critical field for velocity saturation, and lt is the character-
istic length of the exponentially rising electric field and is given as [5]

εSi
lt = tox X j ≈ 3tox X j (7.85)
ε ox

The peak electric field is reached at the drain [5], where

2
 V − VDSsat 
ξ max = ξ y ( y = L) =  DS 2
 + ξ sat (7.86)
 lt

In the saturation region, generally ξ max >> ξ sat, so that ξ max can be approxi-
mated as
V − VDSsat
ξ max = DS (7.87)
lt

This field can be as high as mid-105 to 106 V/cm and leads to impact ioniza-
tion and other hot carrier effects. From (7.84), we find after using necessary
trigonometric identity,

dξ y ( y ) 1 2
= ξ y ( y ) − ξ 2sat (7.88)
dy lt

MOSFET Characterization for VLSI Circuit Simulation 319

Substituting (7.88) in (7.83), with appropriate change of limits, we get

− Bi
ξ max
e ξy Ai lt I DS ξ max  B 
I sub = Ai lt I DS
∫
ξ sat
2
ξ −ξ
y
2
sat
dξ y =
Bi
exp  − i  (7.89)
 ξ max 

From (7.87) and (7.89), we get

Ai  Bi lt 
I sub = (VDS − VDSsat ) exp  − I DS (7.90)
Bi  VDS − VDSsat 

This is used to calculate the substrate current in MOS transistors. It may

be noted that Isub strongly depends on the effective channel length because
the drain saturation current strongly depends on the effective channel
length. In addition, the drain current IDS depends on the source-drain series
resistance.
The substrate current causes an ohmic potential drop in the substrate. This
leads to substrate bias that causes the threshold voltage to drop. This triggers
a positive feedback effect that further enhances the drain current. The sub-
strate current induced body bias effect (SCBE) results in a current increase
that is much larger than Isub.

7.5.1 Hot Carrier Injection (HCI)

For high enough electric field, some of the electrons or holes gain sufficient
energy from the electric field to cross the interface barrier and enter the
SiO2 layer. The electrons thus trapped in the oxide change the threshold
voltage, typically the threshold voltage for NMOS transistors increases and
that for the PMOS transistor decreases. The probability of carrier injec-
tion is more for hot electrons compared to hot holes. This is because of the
smaller effective mass of electrons and because the Si-SiO2 interface energy
barrier is larger for holes (~4–6 eV) than for electrons (~3.1 eV). This hot
carrier injection phenomenon leads to a long-term reliability problem, or
aging problem, where a circuit might degrade or fail after being in use for
some time.
Present-day CMOS technologies use specially engineered lightly doped
drain and source regions which introduces additional series resistance and
reduces the peak electric field in the transistor. This prevents carriers from
reaching the critical values necessary to become hot. However, drain current
and thus device performances are traded off as a result. Therefore, an impor-
tant design consideration is to operate the circuit at a voltage far enough
below the breakdown condition.
320 Technology Computer Aided Design: Simulation for VLSI MOSFET

7.6 Characterization of Gate Dielectric

The thickness of the gate dielectric (SiO2 is the preferred gate insulator in the
semiconductor industry because of the excellent compatibility of SiO2 with
silicon and established performance record) is reduced from 300 nm for the
10 µm technology to 1.2 nm for the 65 nm technology. Scaling down of SiO2
thickness is essential for two reasons. First, with the scaling down of the
oxide thickness, the gate capacitance Cox increases. This increases the transis-
tor ON-current which leads to an increase of the circuit speed. The second
reason is short channel effect immunity, as discussed earlier.
However, if the oxide becomes too thin, the electric field in the oxide
becomes so high that it may cause dielectric breakdown. For oxide thick-
ness less than 1.5 nm, tunneling leakage current becomes the most serious
limiting factor that prevents the use of such thin film. The reduction of gate
oxide thickness (has reached only a few atomic layers) results in an increase
in field across the oxide. The high electric field leads to tunneling of elec-
trons from the strongly inverted surface to gate and also from gate to the
inverted surface through the gate oxide, resulting in gate oxide tunneling.
When the electrons tunnel into the conduction band of the oxide layer, the
resulting tunneling is referred to as Fowler-Nordheim tunneling [5]. On the
other hand, if the electrons tunnel directly through the forbidden energy gap
of the SiO2 layer, the resulting tunneling is referred to as direct tunneling.
In order to avoid the tunneling problem, there is an intense search of alter-
native dielectrics with high-κ (permittivity) which has properties very close
to SiO2 but offers the opportunity to use a higher thickness for the gate insu-
lator. The gate capacitance of a MOS transistor using an arbitrary dielectric
material with thickness Td is given by

ε0κ d A
CG = (7.91)
Td

In (7.92), ε 0 is the permittivity of free space, κ d is the relative permittivity

of dielectric material, A is the area of the conducting plates, and Td is the
gate dielectric thickness. The thickness of the high-κ dielectric insulator is
derived from the relation

κ SiO2
Tox = Effective oxide thickness (EOT) = Td (7.92)
κd

HfO2 has a relative permittivity (κ) of ~24, six times larger than that of
SiO2(κ SiO2 ~ 3.9). Therefore, a 6-nm HfO2 film has effective oxide thickness
(EOT) of 1 nm, in the sense both films produce the same oxide capacitance.
However, the HfO2 film is physically much thicker compared to SiO2 film.
Therefore the leakage current in the HfO2 film is several orders of magnitude
MOSFET Characterization for VLSI Circuit Simulation 321

smaller than that through SiO2. Some other popular high-κ dielectric insula-
tor materials are ZrO2 and Al2O3. However, the uses of high-κ dielectric insu-
lator materials pose several problems in IC manufacturing. These include
chemical reactions between these materials and the silicon substrate, lower
surface mobility, and more oxide trapped charges. In order to reduce these
problems to some extent, a thin SiO2 interfacial layer is inserted between the
silicon substrate and the high-κ dielectric insulator.
In SPICE simulation, high-κ gate dielectric can be modeled as SiO2 with
an equivalent oxide thickness. Alternatively, the value of the gate dielectric
constant parameter (EPSROX) can be specified.

7.7 Capacitance Characterization
A VLSI circuit operates both under DC conditions (when the terminal volt-
ages do not change with time) and time-varying conditions. The time-varying
operation of the circuit is largely influenced by the various capacitors present
in a MOS transistor. Therefore, proper characterization of the various capaci-
tances of a MOS transistor is an essential task for IC designers. The capaci-
tance model is based on the quasi-static approximation, which implies that
the potential and charge density at any given point in the channel of the tran-
sistor follow the time-varying terminal voltages immediately without any
delay. In other words, under quasi-static approximation, it is assumed that the
time-varying terminal voltages do not change appreciably within the “transit
time” duration of the device. The various intrinsic and extrinsic capacitors
present within a MOS transistor are identified in the following sub-section.

7.7.1 Capacitance Components in a MOS Transistor

The various capacitors present within an n-channel MOS transistor are iden-
tified in Figure  7.30. For characterizing the various capacitances, the MOS
transistor capacitors are divided into two types: intrinsic and extrinsic. The
intrinsic region is identified as the region between the metallurgical source
and the drain junction where the gate to S/D region is at flat band voltage.
The capacitances involved within the intrinsic region are referred to as the
intrinsic capacitances. The extrinsic capacitances that are basically the para-
sitic capacitances are further divided into five components: (1) the outer fring-
ing capacitances between the poly-silicon gate and the S/D region: CFO; (2) the
inner fringing capacitances between the poly-silicon gate and the S/D region:
CFI; (3) the overlap capacitances between the gate and the heavily doped S/D
regions (as well as the bulk region), CGSO, CGDO (CGBO); (4) the overlap capaci-
tances between the gate and the lightly doped S/D regions CGSOL, CGDOL; and (5)
the source/drain junction capacitances CJS and CJD. The intrinsic capacitances
322 Technology Computer Aided Design: Simulation for VLSI MOSFET

Gate G

CGSI CGBI CGDI

CFO CFI CFO
CFI

CGDOL D
CGSO CGSOL CGDO
n+ n+ Xjd
S

CJS CJD

CGBC
p-substrate

FIGURE 7.30
Identification of intrinsic and extrinsic capacitors present in an n-channel MOS transistor.

are shown bold in Figure 7.29. These are gate-to-source capacitance CGSI, gate-
to-bulk capacitance CGBI, and gate-to-drain capacitance CGDI.

7.7.2 Characterization of Intrinsic Capacitances (Meyer’s Approach)

The simplest approach for characterizing the gate capacitances was devel-
oped by Meyer [15,16]. The simplified intrinsic capacitance model treats the
intrinsic MOS capacitances as three lumped capacitances, gate-to-source
capacitance CGS, gate-to-drain capacitance CGD, and gate-to-bulk capacitance
CGB. The gate capacitances are attributed entirely to the changes in the gate
charge, which is written in the following compact formulation:
∂QG
CGZ = (7.93)
∂VGZ
In (7.93), CGZ represents the capacitance between the gate and the terminal
Z (S/D), while VGZ represents the corresponding voltage difference. It is also
assumed that all capacitances are reciprocal (e.g., CGD = CDG). From charge
neutrality condition, we have
QG = −(Qinv + QB ) (7.94)

Here Qinv is the inversion charge density, and QB is the bulk charge density.
In strong inversion, the channel charge density along the channel is given by
(7.26) which is repeated here for convenience:

Qinv = −Cox (VGS − VT − VCS ( y )) (7.95)

MOSFET Characterization for VLSI Circuit Simulation 323

Here m is taken to be unity for simplicity. The drain-to-source current is

given by (7.24) which is repeated here for convenience:
VDS
W
I DS = µs
L ∫ [ −Q inv (VCS )] dVCS (7.96)
0

The drain-to-source current IDS is obtained by integration (7.96) and is writ-

ten as
µ sWCox  1 
I DS =  VGS − VT − VDS  VDS (7.97)
L 2

Using VGD = VGS − VDS, (7.97) is transformed to

µ sWCox
I DS = [(VGS − VT )2 − (VGD − VT )2 ] (7.98)
2L

Considering the variation of the charges along the channel length, (7.94) is
transformed to

L L L

∫ ∫ ∫
QG = −W Qinv ( y ) dy − W Qb ( y ) dy = −W Qinv ( y ) dy − QB (7.99)
0 0 0

Using (7.96), (7.97), and (7.99) and performing the integration, we get

2  (VGD − VT )3 − (VGS − VT )3 
QG = WLCox  2  − QB (7.100)
 (VGD − VT ) − (VGS − VT ) 
2
3

7.7.2.1 Intrinsic Capacitances in the Linear Region

The intrinsic capacitances CGS, CGD, and CGB in the linear region are deter-
mined by using the following relationships:

∂QG
CGS = (7.101)
∂VGS VGD ,VGB

∂QG
CGD = (7.102)
∂VGD VGS ,VGB

∂QG
CGB = (7.103)
∂VGB VGS ,VGD

324 Technology Computer Aided Design: Simulation for VLSI MOSFET

Therefore, by differentiating (7.100) as per the relationships (7.101) through

(7.103), the various gate capacitances are determined as follows:

CGS =
2 
WLCox 1 −
(VGD − VT )2 
2  (7.104)
3  (VGS − 2VT + VGD ) 

CGD =
2 
WLCox 1 −
(VGS − VT )2 
2  (7.105)
3  (VGS − 2VT + VGD ) 

CGB = 0 (7.106)

The fact that the capacitance CGB is zero at the strong inversion region may be
explained by the fact that the inversion layer in the channel from the source
to the drain screens the silicon bulk from the gate charge.

7.7.2.2 Intrinsic Capacitances in the Saturation Region

In the saturation region, the drain voltage is VDSsat, which is given by
VDSsat = VGS − VT , assuming long channel MOS transistor. Thus the gate-to-
drain voltage becomes
VGD = VGS − VDSsat = VT (7.107)

Substituting (7.108) in (7.101), we get

2
QG = WLCox (VGS − VT ) − QB (7.108)
3
Therefore, the various intrinsic gate capacitances in the saturation region are
obtained as follows:
2
CGS = WLCox (7.109)
3

CGD = 0 (7.110)

CGB = 0 (7.111)

The physical explanation for (7.111) is the same as that provided for (7.106).
The physical explanation for (7.110) is that in the saturation region the chan-
nel is pinched off, thereby the channel is electrically isolated from the drain.
The gate charge is not influenced by the change in drain voltage, and thus
the capacitance CGD vanishes.

7.7.2.3 Intrinsic Capacitances in the Subthreshold Region

In the subthreshold region, the inversion charge is negligible compared to
the bulk depletion charge, so that the charge neutrality condition is given by

QG = −QB = Cox γ ψ sa (7.112)

MOSFET Characterization for VLSI Circuit Simulation 325

In (7.112), ψsa is the surface potential in the subthreshold region, which is

given as [7]
2
 γ γ2 
ψ sa =  − + + VGB − VFB  (7.113)
 2 4 

Substituting (7.113) in (7.112) and performing an integration as done in (7.100),

the total gate charge in the subthreshold region is given by

1  4 
QG = − WLCox γ 2 1 − 1 + 2 (VGB − VFB )  (7.114)
2  γ 

Therefore, by differentiating (7.114) as per the relationships (7.101) through

(7.103), the various gate capacitances are determined as follows:

CGS = 0 (7.115)

CGD = 0 (7.116)

WLCox
CGB =
1+ (VGB − VFB ) (7.117)
4
γ2

7.7.2.4 Intrinsic Capacitances in the Accumulation Region

In the accumulation region, VGS < VFB , the MOS structure behaves like a sim-
ple parallel plate capacitor and the capacitances are as follows:

CGS = 0 (7.118)

CGD = 0 (7.119)

CGB = Cox (7.120)

7.7.2.5 Charge-Based Approach
It may be noted that Meyer’s approach for characterizing the intrin-
sic capacitances of a MOS transistor is simple and is widely used by the
IC designers for first-hand estimation of the various MOS capacitances.
However, this approach for characterization does not provide good results
for some circuits such as MOS charge pump, static RAM, and switched
capacitor circuits. Therefore, an alternative approach is used for character-
izing the MOS capacitances in today’s compact models. This is the charge-
based approach for capacitance characterization. In this approach, the
326 Technology Computer Aided Design: Simulation for VLSI MOSFET

emphasis is put on the accurate characterization of charges of each termi-

nals (QD , QS , QG , QB ) of the MOS transistor. The calculation of total inver-
sion charge in the channel is fairly easy. However, it is difficult to precisely
characterize the charges on the source and the drain terminals. The inver-
sion charge must be partitioned to the source and drain in a suitable man-
ner. Several charge partitioning approaches have been suggested for the
saturation region. They are 50/50, 40/60, and 0/100 and are distinguished
in the compact models through a model parameter X PART = QD/QS as the
charge partitioning ratio. The simplest way is to partition the channel
charge and assign 50% of the inversion charge to the source and the rest
to the drain, which corresponds to (X PART = 0.5), which can be written as
QS = QD = 0.5Qinv. When X PART > 0.5 , the 0/100 charge partitioning scheme
is chosen which implies that QS = Qinv , QD = 0 . When X PART < 0.5 , the 40/60
charge partitioning scheme is chosen. The 40/60 partition scheme, also
known as the Ward Dutton partitioning scheme [17], is physically correct
as demonstrated through 2D device simulation results and experiments.

7.7.2.6 Effect of Poly-Silicon Gate Depletion Effect and

Finite Inversion Charge Layer Thickness
The poly-silicon gate depletion effect as discussed earlier needs to be consid-
ered while characterizing the intrinsic capacitances. This is implemented by
replacing VGS in all model equations by VGS _ eff as defined in (7.74). The effect
of finite inversion charge thickness can be characterized by a capacitance in
series with the gate oxide capacitance Cox. This results in reduced effective
gate oxide capacitance:
Cox CC
Cox _ eff = (7.121)
Cox + CC

In (7.121), CC is the correction term added due to the inversion layer of thick-
ness tinv.

7.7.3 Characterization of Extrinsic Capacitances

The extrinsic components of MOS transistor capacitances are categorized
broadly into three types: (1) gate overlap capacitances in source/drain and
bulk region (CGSO/CGDO, CGSOL/CGDOL, CGBO); (2) inner and outer fringing
capacitances (CFI and CFO); and (3) source/drain junction capacitances (CJS
and CJD). These capacitances at a given operating bias condition are required
to be characterized.

7.7.3.1 Characterization of Fringing and Overlap Capacitances

Characterization of overlap capacitance in a MOS transistor device is espe-
cially important when the amount of overlap becomes significant compared
MOSFET Characterization for VLSI Circuit Simulation 327

G WP
COV

CFO tox

CFI
Xj S D

FIGURE 7.31
Overlap and fringing capacitances.

to the electrical channel length. As a crude estimate, the overlap capacitance

is determined as follows [3]:
ε ox d
COV = (7.122)
tox

Here d is the amount of gate-to-drain/source overlap. However, when d is

small, the fringing effect is significant. Let us consider the approximate
structure, shown in Figure  7.31 for precise characterization of the overlap
and fringing capacitances [18].
The overlap capacitance consists of the following three components: (1)
outer fringing capacitance CFO between the gate and the source/drain, (2)
direct overlap capacitance COV between the gate and the source/drain, and
(3) inner fringing capacitance CFI on the channel side between the gate and
the side wall of the source/drain junction. These capacitances are calculated
using conformal technique with appropriate boundary conditions [18]. These
capacitances for unit width of the device are given as follows:

ε ox  Wp 
CFO = ln  1 + (7.123)
θ  tox 

ε ox  X j sin β 
CFI = ln  1 + (7.124)
β  tox 

ε ox (d + )
COV = (7.125)
tox

In (7.123), θ is the slope angle for the poly-silicon gate. For the vertical edge of
the poly-silicon gate, θ = π/2. In (7.124), β is given by

πε ox
β= (7.126)
2 εSi
328 Technology Computer Aided Design: Simulation for VLSI MOSFET

In (7.125), Δ is a correction factor to account for some higher-order effects and

is given as follows:

tox  1 − cos θ 1 − cos β 

=  sin θ + sin β  (7.127)
2

The total overlap capacitance per unit width of the device is thus given by the
sum of (7.123), (7.124), and (7.125).
In addition to the above overlap capacitances, there is another overlap
capacitance in the channel width direction, which results in an overlap
capacitance between the gate and the substrate. This is given as

CCGBO = CCBO
′ ⋅ L (7.128)

′ is the gate-to-bulk overlap capacitance per unit length.

Here in (7.128), CGBO

7.7.3.2 Characterization of Junction Capacitances

The junction capacitances arise from the depletion charge between the source
or drain and the substrate. These are usually reverse-biased. Therefore, with
the variation of source or drain voltages, the depletion charge increases or
decreases accordingly. The depletion capacitance per unit area of an abrupt
p-n junction is [5]

m
ε Si ε Si qN A  εSi qN A 
Cj = = =  (7.129)
Wdj 2 (Vbi + VR )  2 (Vbi + VR ) 

In (7.129), Wdj is the depletion layer width, N A is the impurity concentration

of the lightly doped side, ψ bi is the built-in potential, and VR is the reverse
bias voltage across the junction. In (7.129), m is the grading coefficient and its
value is ½ for abrupt p-n junction. For zero bias, C j0 is defined as

m
 qεSi N A 
Cj0 =   (7.130)
 2Vbi 

With this, (7.129) can be algebraically manipulated as [3]

−m
 V 
Cj = Cj0  1 + R  (7.131)
 Vbi 

MOSFET Characterization for VLSI Circuit Simulation 329

The junction capacitance has two components: bottom component and side-
wall/perimeter component. The total junction capacitance is thus written as [3]

C j = C jb A + C jsw P (7.132)

In (7.132), Cjb is the bottom component of the junction capacitance per unit
area, A is the total junction area, Cjsw is the sidewall component of the junction
capacitance per unit length, and P is the total junction perimeter. Using (7.131),
the bottom component and perimeter component are defined as follows:
− mb
 V 
C jb = C j 0b  1 + R  (7.133)
 Vbi 

− msw
 V 
C jsw = C j 0 sw  1 + R  (7.134)
 Vbisw 

In (7.133), C j 0b is the zero-bias sidewall capacitance per unit area, and mb is
the grading coefficient for the bottom component. In (7.134), C j 0 sw is the zero-
bias sidewall capacitance per unit length, and msw is the grading coefficient
for the sidewall.

7.7.4 Simulation Results and Discussion

The channel length is taken to be 65 nm and channel width is 10 μm. The
oxide capacitance per unit area is 0.0197 F/m2. The simulation results include
all sorts of extrinsic capacitances and intrinsic capacitances, which are cal-
culated as per the charge-based approach. The charge partitioning ratio is
taken to be 0, which means that 40/60 charge partitioning scheme has been
considered. Here, we present an intuitive understanding of the graphs. This
is important for VLSI designers.
The variations of gate-to-source capacitor CGS with VDS for three different
values of VGS are shown in Figure 7.32. It is observed that in the subthreshold
region, the gate-to-source capacitance value is very low. This can be explained
by the fact that in the subthreshold region, the inversion charge is negligibly
small. According to Meyer’s approach, CGS = 0 in the subthreshold region.
However, there will be extrinsic components that contribute to this capaci-
tance. In the linear region, with small VDS, as VGS increases, the inversion
charge increases. Therefore, the capacitance value increases. In the satura-
tion region, because of the pinch-off phenomenon, the inversion charge is
solely due to the gate-source voltage and the capacitance value is maximum.
This behavior is followed by the simulation results.
The variations of gate-to-drain capacitor CGD with VDS for three differ-
ent values of VGS are shown in Figure 7.33. In the subthreshold region, the
inversion charge is negligibly small so that CGD is ideally zero. In the satura-
tion region, due to the pinch-off phenomenon, there is no capacitive coupling
330 Technology Computer Aided Design: Simulation for VLSI MOSFET

14

12 VGS = 0 V
VGS = 0.4 V
VGS = 1 V
10
VBS = 0 V
VT (VDS = 50 mV)= 432.36 mV
CGS (fF)

VT (VDS = 1 V)= 465.13 mV

8

2
0.0 0.2 0.4 0.6 0.8 1.0
VDS (V)

FIGURE 7.32
Variation of gate-to-source capacitance with applied drain bias for three different gate biases.

10
VGS = 0 V
VGS = 0.4 V
9 VGS = 1 V

8 VBS = 0 V
VT (VDS = 50 mV)= 432.36 mV
VT (VDS = 1 V)= 465.13 mV
7
CGD (fF)

2
0.0 0.2 0.4 0.6 0.8 1.0
VDS (V)

FIGURE 7.33
Variation of gate-to-drain capacitance with applied drain bias for three different gate biases.
MOSFET Characterization for VLSI Circuit Simulation 331

14
VDS = 0 V
VDS = 0.4 V
12 VDS = 1 V

VBS = 0 V
10 VT (VDS = 50 mV) = 432.36 mV
VT (VDS = 1 V) = 465.13 mV

8
CGB (fF)

–3 –2 –1 0 1 2 3
VGS (V)

FIGURE 7.34
Variation of gate-to-body capacitance with applied gate bias for three different drain biases.

between the drain and the gate so that CGD is very small. In the linear region,
as VDS reduces, the inversion charge increases so that the CGD increases.
This behavior is followed by the simulation results.
The variations of the gate-to-bulk capacitance CGB with gate bias for three
different drain biases are shown in Figure 7.34. This capacitance has a non-
zero value only in the subthreshold region. This is because in this region, the
inversion charge is very small. The capacitance is determined by the series
combination of oxide capacitance and the depletion capacitance. In the accu-
mulation region, the intrinsic gate-to-bulk capacitance is determined solely
by oxide capacitance.
Therefore, Meyer’s approach [15] of characterizing the intrinsic capacitance
qualitatively explains the variations of the capacitances with bias conditions.

7.8 Noise Characterization
Noise in a MOS transistor is caused by small random fluctuations in sig-
nals (currents and voltages), caused due to phenomena generated within the
device. Proper characterization of noise in a MOS transistor is essential for
332 Technology Computer Aided Design: Simulation for VLSI MOSFET

analog and RF IC design. The two most important noise components of a

MOS transistor are thermal noise and flicker noise. The following subsec-
tions deal with each of them individually.

7.8.1 Characterization of Thermal Noise in MOS Transistor

In conventional resistors, the thermal noise is generated due to the random
thermal motion of the electrons. This motion does not depend upon the pres-
ence or absence of direct current, because the drift velocities of electrons in
a conductor are much less than the thermal velocities of the electrons. In a
resistor R, the thermal noise is represented by a series voltage generator or a
shunt current generator to a noiseless ideal resistor. The noise spectral density
is given by [3,5]

vn2 = 4 kTR f (7.135)

1
in2 = 4 kT f (7.136)
R

In (7.135) and (7.136), k represents Boltzmann’s constant. From (7.135) and

(7.136), it is observed that the noise spectral density is independent of fre-
quency f. This characteristic is called white noise.
The intrinsic thermal noise of a MOS transistor originates from the chan-
nel resistance due to random thermal motion of the carriers. The channel
of a MOS transistor may be considered to be divided into several resistive
segments, and each of these segments contributes to thermal noise. The
corresponding noise spectral density thus follows (7.135). The resistor R is
replaced by (2/3) g m, in a saturation region where gm is the gate transconduc-
tance of the device. It follows, therefore, from (7.135) that

8 kT
vn2 = g m f (7.137)
3

However, (7.137) is inadequate, especially in the linear region VDS ≈ 0 where

the transconductance is zero, so that the calculated noise spectral density
becomes zero, which however is not true in practice. Thus (7.137) is modified
as follows:
8 kT
vn2 = ( g m + g ds + g mb ) f (7.138)
3

In (7.138), gds and gmb are output conductance and body transconductance,
respectively. However, a more rigorous approach for characterizing thermal
noise is given below which is widely used in SPICE compact models [3,6,7].
MOSFET Characterization for VLSI Circuit Simulation 333

Consider an infinitesimally small section of the noiseless channel of a MOS

transistor of length dy. Let the resistance of this small section be dR and the
channel voltage produced by this resistance is dVCS. For a channel current
IDS, these are related as

dVCS
dVCS = I DS dR = −W µ sQinv dR (7.139)
dy

From (7.139) it follows that

dy
dR = − (7.140)
W µ sQinv

The noise spectral density due to the thermal noise generated by this small
resistance dR is given by

dy
vn2 = 4 kTdR f = −4 kT f (7.141)
W µ sQinv

The power spectral density for the elemental noise voltage is from (7.141)

dy
dSVC = 4 kTdR = −4 kT (7.142)
W µ sQinv

From this elemental noise voltage, the elemental noise current power spec-
tral density is

dSID = gC2 dSVC (7.143)

The conductance for the elemental channel segment is determined as follows:

dI d  W VDS 
 µ s Qinv (VCS ) dVCS  = −µ s W Qinv (7.144)
gC = DS = −
dVCS dVCS L

∫ 

L
0

Substituting gc from (7.144) and dSVC from (7.142) into (7.143), we get

2
 W  dy µ
dSID = −  −µ s Qinv  4 kT = −4kT 2s WQinv dy (7.145)
 L  µ sWQinv L

334 Technology Computer Aided Design: Simulation for VLSI MOSFET

Integrating over the entire channel length, the total noise current power
spectral density is given by

L
µ µs
SID = −4 kT 2s
L ∫Q inv W dy = − 4 kT
L2
QINV (7.146)
0

In (7.146), QINV = QinvWL represents the total inversion charge under the
gate. The thermal noise power spectral density is often expressed in the
following manner, referred to as the Klaassen-Prins equation for thermal
noise [19]:

4 kT

SID =
L2 I DS ∫ g (V
2
CS ) dVCS (7.147)

It is to be noted that (7.146) is used in a BSIM compact model with appropriate

substitution of QINV .

7.8.2 Characterization of Flicker Noise in MOS Transistor

The flicker noise in the drain current or gate voltage of a MOS transistor is
important to characterize precisely because it deteriorates the signal-to-noise
ratio of several analog circuits. It also increases the phase noise of oscillators
in RF applications. For proper characterization of flicker noise, the under-
lying physical mechanism of the flicker noise must be understood. This is
briefly discussed below.

7.8.2.1 Physical Mechanisms of Flicker Noise

The conductivity of a conductor due to drift motion of the carriers is given by

σ = qnμ (7.148)

In (7.148), n represents the carrier concentration, and μ represents the carrier

mobility. It appears from (7.148) that any fluctuation in the carrier density
or mobility leads to fluctuation of the current flowing through the conduc-
tor. There are several different theories for explaining the physical cause of
flicker noise. These are broadly classified into three different categories [20]:
(1) carrier density fluctuation model, (2) mobility fluctuation model, and (3)
correlated carrier and mobility fluctuation model.
According to the carrier density fluctuation model [20], the flicker noise is
caused by random trapping and de-trapping of mobile carriers by the inter-
face traps at the Si-SiO2 interface. The interface traps dynamically exchange
MOSFET Characterization for VLSI Circuit Simulation 335

carriers with the channel causing fluctuation in the surface potentials, giving
rise to fluctuation in the inversion charge density. The carrier density fluc-
tuation model is observed to successfully explain the flicker noise spectrum
in n-channel MOS transistors. According to the mobility fluctuation model
[20], on the other hand, the flicker noise is caused due to fluctuation in the
carrier mobility, caused due to phonon scattering. The mobility fluctuation
model successfully explains the flicker noise spectrum in p-channel MOS
transistor. According to the correlated carrier and mobility fluctuation model
[21,22], also referred to as the unified flicker noise model, when an interface
trap captures an electron from the inversion layer, it becomes charged and
reduces the carrier mobility due to Coulombic scattering. Thus according to
this model, both the carrier number and the carrier mobility fluctuate due to
trapping and de-trapping of the carriers by the interface traps. The unified
model shows good matching with experimental results.

7.8.2.2 Empirical Approach for Characterization of Flicker Noise

The power spectral density of the flicker noise spectrum is given by [21]

KF ⋅ I DS
AF
SID = (7.149)
f ⋅ Cox ⋅ WL

In (7.149), KF is the flicker noise coefficient, and AF is the flicker noise expo-
nent. The value of the parameter AF lies in the range of 0.5 to 2. The constant
KF is proportional to the interface trap density, which is technology-specific.
The lack of systematic approach in determining the empirical parameters
limits the use of this model. However, two significant observations are made.
First, the flicker noise is dominant at low frequency. Because of its depen-
dence on frequency as (1/f), flicker noise is sometimes referred to as the (1/f)
noise. At frequencies above 100 MHz, the flicker noise spectrum becomes
negligible compared to that of the thermal noise. Second, the flicker noise
spectrum reduces as the gate area is increased. Third, for PMOS transistors,
it has been found that the value of the flicker noise coefficient is smaller com-
pared to NMOS transistors; therefore, PMOS transistors are used in design-
ing low noise circuits, at least at the first stage.

7.8.2.3 Characterization of Flicker Noise through Physics-Based Model

Consider a section of the channel with width W and length Δy. The drain
current is given by

I DS = W µ s qN ξ y (7.150)

336 Technology Computer Aided Design: Simulation for VLSI MOSFET

In (7.150), μs is the carrier mobility, q is the electron charge, N is the number of

channel carriers per unit area, and ξ y is the lateral channel field. Fluctuation
of local drain current is given by [21,22]

δI DS  1 δ N 1 δµ s 
= − ±  δ N t (7.151)
I DS  N δ N t µ s δ Nt 

In (7.151), ΔN = NWΔy, N t = N tW y, where N t is the number of occupied

traps per unit area, and N is the inversion carrier density. The ± sign in
the mobility term of (7.151) denotes whether the trap is neutral or charged
when filled.
Let us first evaluate the first term on the right-hand side of Equation (7.151).
The ratio of fluctuations in carrier number to fluctuations in occupied trap
number R = δ N/δ N t is close to unity in strong inversion but assumes a
smaller value in other bias conditions. A general expression of R is therefore
written as follows:

δ N Cinv
R= =− (7.152a)
δ Nt Cox + Cinv + Cdm + Cit

In (7.152a), Cinv , Cdm , and Cit are inversion layer, depletion layer, and inter-
face trap capacitances, respectively. A more concise form of R is as follows:

N
R=− (7.152b)
N+N*

In (7.152b), N * = ( kT/q 2 )(Cox + Cdm + Cit ) and the typical value of this quantity
is 1–5E10/cm–2.
Let us now evaluate the first term on the right-hand side of Equation (7.151).
The carrier mobility is related to the oxide trap density as follows:

1 1 1 1 1 1
= + + + = + α sc N t (7.153)
µ s µ B µ SR µ Ph µ Cit µ n

In (7.153), µ Cit = 1/α sc N t is the mobility limited by Coulombic scattering of the

mobile carriers at trapped charges near the Si-SiO2 interface, and µ B , µ SR , µ Ph
represents the mobility limited by ionized impurity scattering, surface
roughness scattering, and phonon scattering, respectively. The scattering
coefficient α sc is a function of the local carrier density due to the screening
effect as well as the distance of the trap from the interface. From experimental
MOSFET Characterization for VLSI Circuit Simulation 337

results, it has been found that μCit increases with the inversion carrier density
due to the screening effect. The relationship is given as follows [23]:

N
µ Cit = µ CO (7.154a)
Nt

1
α sc = (7.154b)
µ CO N

However, in the original unified mobility model [21,22], the scattering

parameter is considered to be independent of the inversion carrier density.
The reduction of α sc with an increase of N is understood as follows. As the
inversion carrier density increases, the screening length and the scattering
cross section due to the screening by minority carriers reduce and hence the
scattering parameter increases. In a weak inversion region, screening due to
minority carriers becomes less significant compared to that by majority car-
riers. Because the majority carrier concentration does not change much in the
weak inversion region, the scattering cross section remains almost constant
with inversion carrier density. Consequently, in the weak inversion region,
α sc saturates to a particular value and (7.153b) is no longer valid [23]. By dif-
ferentiating (7.153) and substituting in (7.151), we arrive at

δI DS R δ Nt
= −  ± α sc µ s  (7.155a)

I DS N W y

This can be written as

R I
δI DS = −  ± α sc µ s  DS δ N t (7.155b)
 N  W y

The power spectrum density of the local current fluctuation is obtained from
(7.155b) as follows:

2
 I DS   R 
2
S I DS ( y , f ) =  W y   N ± α µ
sc s  S Nt ( y , f ) (7.156)


In (7.156), S Nt ( y , f ) is the power spectrum density of the fluctuations in the

number of occupied traps over the area WΔy and is given by

kTW y
S Nt ( y , f ) = N t (E fn ) (7.157)
γf

338 Technology Computer Aided Design: Simulation for VLSI MOSFET

In (7.157), Efn is the electron quasi-Fermi level, and γ is the attenuation coeffi-
cient of the electron wave function in the oxide. Substituting (7.157) in (7.156),
we get
2
 I  R 
2
kTW y
S IDS ( y , f ) =  DS   ± α sc µ s  N t (E fn ) (7.158)
W y N  γf

The total drain current noise power spectral density is given as

L
1

SIDS ( f ) =
L2 ∫S
0
I DS ( y , f ) ydy (7.159)

Substituting (7.158) in (7.159) and changing the variables of integration by

using (7.150), we write
VDS 2
qkTI DSµ s  N  R2
SIDS ( f ) =
γ f L2 ∫ ( )
N t E fn  1 ± α sc µ s 
 R N
dV (7.160a)
0

This can be written in a compact way as follows:

VDS
qkTI DSµ s 2
SIDS ( f ) =
γ fL2 ∫ ( ) RN dV (7.160b)
N t* E fn
0

In (7.160b), N t* (E fn ) is the equivalent oxide trap density that produces the

same noise power in absence of mobility fluctuations and is given as

2
 N
N t* (E fn ) = N t (E fn )  1 ± α sc µ s  (7.160c)
 R

In BSIM implementation of the unified noise model, three additional

parameters are introduced to fit the noise measurement results:

N t* (E fn ) = A + BN + CN 2 (7.161)

In (7.161), A, B, and C are technology-dependent model parameters. In (7.160b),

the integration variable is changed as follows:

ND
q 2 kTI DSµ s R2
SIDS ( f ) =
γ f L2 Cox ∫ N t* (E fn )
N
dN (7.162)
NS
MOSFET Characterization for VLSI Circuit Simulation 339

In (7.162), NS and ND represent the inversion charge density at the source end
and drain end, respectively. These can easily be computed from the inversion
charge densities formulae discussed earlier for linear, saturation, and sub-
threshold regions. Without going into the detailed mathematical derivations
(lengthy but elementary), the drain current noise power at the three regions
of operations are written as follows [6]:

Linear Region

q 2 kTI DSµ s   NS + N *  1 
SIDS ( f ) =
mγ f L2 Cox
 A ln  * 
 ND + N  2
( )
+ B ( N S − N D ) + C N S2 − N D2  (7.163a)
 

Saturation Region

q 2 kTI DSµ s   NS + N *  1 
SIDS ( f ) = 2  A ln  * 
+ B ( N S − N D ) + C( N S2 − N D2 ) 
mγ f L Cox   ND + N  2 
2
kTI DS A + BN D + CN D2
+ L (7.163b)
γ f WL2 ( N D + N * )2

In (7.163a) and (7.163b), NS and ND are evaluated as follows:

qN S = Cox (VGS − VT ) (7.163c)

qN D = Cox (VGS − VT − mVDSsat ) (7.163d)

In (7.163b), the second term in the flicker noise power spectrum density esti-
mates the noise arising in the velocity saturation region. In the subthreshold
region, it is reasonable to assume that N  N * and N t* (E fn ) = A + BN + CN 2 ≈ A.
Thus the flicker noise power in the subthreshold region is simplified to [6]

2
AkTI DS
SIDS ( f ) = (7.163e)
WLγ fN *2

7.8.3 Simulation Results and Discussion

This section presents simulation results of drain current noise spectra and
input referred noise voltage of n-channel MOS transistors and p-channel
MOS transistors using HSPICE, utilizing 65-nm PTM technology. The
340 Technology Computer Aided Design: Simulation for VLSI MOSFET

VDS = 0.4 V, VGS = 0.2 V, VT = 0.453 V

10–12
VDS = 50 mV, VGS = 0.6 V, VT = 0.465 V
10–13 VDS = 0.8 V, VGS = 0.6 V, VT = 0.439 V
10–14
Drain Current Noise (A2/Hz)

10–15
10–16
10–17
10–18
10–19
10–20
10–21
10–22
10–23
10–24
10–25
1 10 100 1k 10 k 100 k 1 M 10 M 100 M 1G
Frequency (Hz)

FIGURE 7.35
Drain current noise power spectrum of an n-channel MOS transistor, operating at three differ-
ent regions of operations.

channel length and width of the transistor in all cases are taken to be 65 nm
and 10 µm, respectively. The model selector flags are fnoimod = 1 and
tnoimod = 1. Figure 7.35 shows a typical drain current noise spectrum mea-
sured in three different regions of operations for an n-channel MOS tran-
sistor. It is observed that noise spectrum shows 1/f k dependency with the
exponential factor k close to unity. This is consistent with the assumption
regarding the uniform spatial distribution of the oxide traps near the inter-
face. It is observed that in the weak inversion region, the drain current noise
of the transistor is lower compared to that in the strong inversion region. This
is explained by the fact that noise power spectrum is directly proportional
to the drain current, and in the weak inversion region the drain current is
very small. The measured drain current noise power at 100 Hz is plotted as a
function of gate bias for three different drain biases in Figure 7.36(a). The bias
dependence of the input referred noise power is plotted in Figure  7.36(b).
At the measured frequency, the thermal noise is negligible compared with
the flicker noise. It is observed that the dependence of input referred noise
power on the bias point is not significant in both linear and saturation
regions. The short channel behavior and DIBL effects are also reflected in the
noise power spectrum. The corresponding simulation results for a p-channel
MOS transistor are shown in Figures 7.37 and 7.38(a),(b). It is observed that
the p-channel transistor has a noise level lower than the n-channel MOS
MOSFET Characterization for VLSI Circuit Simulation 341

10–12
10–13
10–14
10–15
Drain Current Noise (A2/Hz)

10–16
10–17
10–18
10–19
10–20
10–21
10–22
10–23
VDS = 0.8 V, VT = 0.439 V
10–24 Frequency = 100 Hz VDS = 0.4 V, VT = 0.453 V
10–25 VDS = 50 mV, VT = 0.465 V

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VGS (V)
(a)

Frequency = 100 Hz
VDS = 0.8 V, VT = 0.439 V
10–8 VDS = 0.4 V, VT = 0.453 V
VDS = 50 mV, VT = 0.465 V
Input Referred Noise (V2/Hz)

10–9

10–10

10–11

10–12

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VGS (V)

(b)

FIGURE 7.36
(a) Bias dependence of drain current noise power of an n-channel MOS transistor. (b) Bias
dependence of input referred noise power of an n-channel MOS transistor.
342 Technology Computer Aided Design: Simulation for VLSI MOSFET

10–14 VSD = 0.4 V, VSG = 0.2 V, |VT| = 0.395 V

VSD = 50 mV, VSG = 0.6 V, |VT| = 0.410 V
10–15 VSD = 0.8 V, VSG = 0.6 V, |VT| = 0.379 V
10–16
10–17
Drain Current Noise (A2/Hz)

10–18
10–19
10–20
10–21
10–22
10–23
10–24
10–25
10–26
10–27

1 10 100 1k 10 k 100 k 1M 10 M 100 M 1G

Frequency (Hz)

FIGURE 7.37
Drain current noise power spectrum of a p-channel MOS transistor, operating at three differ-
ent regions of operations.

10–12 Frequency = 100 Hz VSD = 0.8 V, |VT| = 0.379 V

10–13 VSD = 0.4 V, |VT| = 0.395 V
10–14 VSD = 50 mV, |VT| = 0.410 V
10–15
Drain Current Noise (A2/Hz)

10–16
10–17
10–18
10–19
10–20
10–21
10–22
10–23
10–24
10–25
10–26
10–27

–1.1 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0.0
VGS (V)

(a)
FIGURE 7.38
(a) Bias dependence of drain current noise power of a p-channel MOS transistor. (b) Variation of
input referred noise spectrum for PMOS transistor operating in the subthreshold region. (continued)
MOSFET Characterization for VLSI Circuit Simulation 343

Frequency = 100 Hz VSD = 0.8 V, |VT| = 0.379 V

10–8
VSD = 0.4 V, |VT| = 0.395 V
VSD = 50 mV, |VT| = 0.410 V
10–9
Input Referred Noise (V2/Hz)

10–10

10–11

10–12

10–13

10–14

–1.1 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0.0
VGS (V)

(b)

FIGURE 7.38
(continued) (a) Bias dependence of drain current noise power of a p-channel MOS transistor. (b)
Variation of input referred noise spectrum for PMOS transistor operating in the subthreshold region.

transistor by one or two orders of magnitude. This is because of different

oxide trap density near the conduction and valence band edges, different
tunneling barriers for the electrons and holes, and different electron and
hole mobilities resulting in different degrees of mobility fluctuations.

7.9 Statistical Characterization
With the scaling of MOS transistors to sub-90 nm regime, the effects of sta-
tistical variations of process parameters on the performances of VLSI circuits
have become critical. The increasing impacts of the within-die variabil-
ity on the performances of VLSI circuits have posed significant challenges
to the conventional VLSI design methodologies. The commercially avail-
able computer aided design tools are used to determine the nominal design
parameters of a circuit, such that the nominal response of the circuit meets
the desired performance specifications. However, after fabrication, the actual
circuit response always shows deviations from the nominal value due to pro-
cess variations. Therefore, a paradigm shift to the conventional deterministic
344 Technology Computer Aided Design: Simulation for VLSI MOSFET

design methodology is required. Statistical design methodology has become

indispensable for the present VLSI circuits. Precise characterization of pro-
cess variability is essential for variability-aware statistical circuit design.

7.9.1 Classification of Process Variability

From a circuit design perspective, the process variations are classified into
two types: intra-die and inter-die variations. The intra-die variations are
defined as the parametric changes of identical MOS transistors across a short
distance, while the inter-die variations refer to such changes for identical
MOS transistors separated by longer distance or fabricated at different times
[24]. Thus intra-die variations are deviations occurring within a die. On the
other hand, the inter-die variations are deviations occurring from die-to-die,
wafer-to-wafer, and lot-to-lot. The wafer-to-wafer variations are caused usu-
ally by some change in machine conditions along time of manufacturing
apparatus. The die-level variations typically originate from lithography steps,
because pattern exposure is performed die-to-die. Imperfections in reticles or
non-uniformity in the lens system sometimes causes die-level variations. The
intra-die variations are significant in sub-90 nm technology and are of critical
concern to the IC designers. The intra-die variations have two components:
systematic and random. The systematic variations include the variations
caused due to optical proximity corrections, phase-sifting mask and layout-
induced strain, and well proximity effect [24]. On the other hand, the ran-
dom variations include variations due to random discrete dopant (RDD), line
edge roughness (LER), line width roughness (LWR), oxide thickness variation
(OTV), poly-silicon gate/metal gate granularity, and interface roughness. In
this chapter, we restricted ourselves to the local component of intra-die pro-
cess variations, which is of serious concern in the nanoscale regime.

7.9.2 Sources of Random Intra-Die Process Variations and Their Effects

In this subsection, the major sources of process variations are identified and
their effects on the device performances are discussed.

7.9.2.1 Random Discrete Dopant (RDD)

With the scaling of the transistor in sub-90 nm technology, it has been found
that the number of dopant atoms within the channel of a transistor becomes
discrete and is a statistical quantity. In 1 μm technology, the number of
dopant atoms in the channel is near about 5000, whereas that in a 32-nm
technology node is less than 100. The random fluctuations of the number
and position of the dopant atoms in the channel of a MOS transistor cause
device-to-device variations of electrical performances which is referred to as
the random discrete dopant effect [25].
RDD is considered to be the major contributor to performance mismatch
of identical MOS transistors placed very close to each other. Considering
MOSFET Characterization for VLSI Circuit Simulation 345

uniform channel doping, the effect of RDD on threshold voltage fluctuation

for a large geometry MOS transistor is given by [25]

q N AWdm
σ VT , RDD = (7.164)
Cox 3LW

In (7.164), Wdm is the depletion depth. For non-uniform doping, N A in (7.164)

is to be replaced by N EFF, which is calculated as follows [26]:
Wdm 2
 x  dx
N EFF = 3
∫ N ( x)  1 −
 Wdm  Wdm
(7.165)
0

In (7.165), N ( x) is the charge density along depth. It is observed from (7.164)

that with the scaling of CMOS technology, the device area LW decreases, so
that the threshold voltage variability caused due to RDD increases. However,
RDD decreases with scaling of oxide thickness. It is found that RDD is a
major contributor, over 60%, to the threshold voltage mismatch.

7.9.2.2 Line Edge Roughness (LER)

Line edge roughness is the second most important source of process variabil-
ity. The cause of this phenomenon is statistical variation in the incident photon
count during lithographic exposure and the absorption rate and molecular
composition of the photo resist [27]. As a result, roughness occurs along the
gate of the MOS transistor, causing variations in gate length along the width
of the transistor. This is schematically shown in Figure 7.39. Experimentally it
has been demonstrated that the LER is of the order of 4 nm and does not scale
down with device scaling. This is because of the fact that the lithographic gap,
defined as the difference between the wavelength of the light used for pat-
terning and the minimum feature size is increasing until extreme ultraviolet
technology is available [28]. LER is considered to be a dominant source of
process variability for short channel length devices beyond 45 nm technology
node, where the amount of LER becomes a significant fraction compared to the
channel length. Because the LER affects the channel length of the transistor, it
leads to threshold voltage variations and variations of all other performances
that depend on the channel length. Moreover, LER and RDD are statistically
independent. The threshold voltage mismatch due to LER depends on the
variations of the width of MOS transistors and is given by [28,29]

1
σ VT , LER ∝ < σVT , RDD (7.166)
W

σ VT , total = (σ VT , RDD )2 + (σ VT , LER )2 (7.167)

346 Technology Computer Aided Design: Simulation for VLSI MOSFET

Definition of LER Definition of LWR

FIGURE 7.39
Microscopic view of channel length along width illustrating LER and LWR.

7.9.2.3 Oxide Thickness Variation (OTV)

Another important source of random intra-die process variability is atomic-
scale oxide thickness variation. With the downscaling of the physical gate
oxide thickness up to 1 nm, it becomes equivalent to approximately five inter-
atom spacing. Through experimentation, it has been observed that the oxide
thickness roughly varies by one or two atomic spacing [30]. The oxide thick-
ness variation occurs primarily due to interface roughness. The oxide thick-
ness variations also lead to variations of all performances related to oxide
thickness either implicitly or explicitly. The threshold voltage variations due
to oxide thickness are also statistically independent of RDD and LER, so that
(7.167) is transformed to

σ VT , total = (σ VT , RDD )2 + (σ VT , LER )2 + (σ VT ,OTV )2 (7.168)

7.9.3 Characterization of Process Variability

Accurate characterization of process variability is a challenging task. The
present subsection highlights the conventional approach and briefly dis-
cusses the new approaches. The development of an accurate characterization
procedure is an important research topic.

7.9.3.1 Design Corner Approach

From an IC designer’s point of view, the collective effects of process variations
are lumped into their effects on the performances of a circuit. These define the
MOSFET Characterization for VLSI Circuit Simulation 347

Fast FF
SF

TT
PMOS

FS
SS
Slow

Slow Fast
NMOS

FIGURE 7.40
Design corners.

design or process corners. The term corner refers to an imaginary box that sur-
rounds the guaranteed performance of the circuits, as shown in Figure 7.40. The
corners for analog applications are slow NMOS and slow PMOS (SS) to charac-
terize the worst-case speed and fast NMOS and fast PMOS (FF) to characterize
the worst-case power. The corners for digital applications are fast NMOS and
slow PMOS (FS) to characterize the worst-case logic 1 and slow NMOS and
fast PMOS (SF) to characterize the worst-case logic 0. The typical (TT) case
characterizes the nominal design of the transistors. The corner parameters are
generated by deviating the selected process-sensitive SPICE model parameters
by a fixed number n of standard deviation σ. For example, an arbitrary SPICE
parameter si of the typical model file is represented through

si = si0 ± nσ (7.169)

In (7.169), n is selected to set the fixed lower and upper limits of the worst-
case models. The direction of the deviation from the mean/typical value
si0 depends on whether increasing or decreasing the parameter makes the
performance worse. This is usually determined by the sensitivity analysis,
by computing the derivative of the performance with respect to the chosen
SPICE parameter, and by considering the sign of the derivative.
The advantage of this design corner approach is that the corner models are
supplied to the designers so that the circuit can be simulated at each of the
process corners for statistical characterization of the effects of process vari-
abilities on circuit performances. However, this approach has two serious
limitations. First, it has the significant risk of over- or underestimation of the
process variations and their impact on the design. Overestimation makes
the task of designing the circuits difficult such that the performances meet
348 Technology Computer Aided Design: Simulation for VLSI MOSFET

the specifications at all the corners. On the other hand, underestimation may
lead to manufacturability problems and eventual loss in yield. The second
problem is that while generating the corner parameters, the correlations
between the device parameters are ignored. This approach therefore does
not provide adequate information about the robustness of the design.

7.9.3.2 Monte Carlo Simulation Approach

The Monte Carlo simulation technique is a stochastic technique widely used
for statistical characterization of the performance parameter variations due
to process variability. The Monte Carlo approach allows direct estimation
of the yield of a VLSI circuit. In this technique, the crucial SPICE param-
eters are sampled from a pre-defined statistical distribution conforming
to the process specification. This forms a large database of process-related
SPICE parameters, and for each sample of the database, the performance
parameters of the circuit are simulated through SPICE simulation. The sta-
tistical distributions of the performance parameters corresponding to each
sample of the process database are estimated by determining the mean and
the standard deviation. The method is very general and accurate for statisti-
cal characterization. The problem with the Monte Carlo-based approach is
that hundreds of simulation runs have to be performed and depending upon
the complexity of the circuit, the entire procedure may take several hours.
However, some strategies are available to reduce the sample size, such as
variance reduction techniques, stratified sampling, etc.

7.9.3.3 Statistical Corner Approach

The basic idea of the statistical corner model approach is to make the design
corner approach more realistic by adding a realistic value of the standard
deviation of the corresponding model parameter to its nominal value fol-
lowing (7.158). The value of each σ is obtained from the distribution of a
large set of production data. The production data are actual measurement
data collected over multiple dies, wafers, and lots. In the absence of actual
measurement data, which are fairly common for new process technology,
the production data may consist of calibrated TCAD simulation results.
The electrical test data, whatever the collection procedure, are mapped to
the appropriate SPICE parameters either directly or through some extrac-
tion procedure [31]. A statistical corner-based approach is thus more realistic
compared to the conventional design corner approach discussed earlier and
is faster compared to the Monte Carlo approach.

7.9.4 Simulation Results and Discussion

This section presents SPICE simulation results for statistical characterization
of three important performance parameters of an n-channel MOS transistor.
MOSFET Characterization for VLSI Circuit Simulation 349

These are (1) threshold voltage VT , (2) OFF current IOFF , and (3) subthreshold
slope S. The intra-die variations studied are random discrete dopants, line
edge roughness, and oxide thickness variations. The Monte Carlo simulation
technique has been utilized using 45-nm PTM model file.

7.9.4.1 Statistical Characterization of RDD

The effects of RDD on device performances are studied through SPICE
simulation by varying the threshold voltage SPICE parameter VTHO. The
reason behind such a selection is that with the variation of dopant number
and hence the doping concentration within the channel, the long channel
threshold voltage is primarily affected. In order to characterize the amount
of variation of this parameter, there are two approaches. The first is to extract
from TCAD simulation results, and the second is to calculate it from (7.164).
Because the present work attempts to provide only the philosophy of the
characterization procedure, the latter approach is performed, although the
first one is preferred for accurate characterization.
The effective channel length and width of the chosen MOS transistor are
37.5 nm and 120 nm, respectively. The substrate doping concentration is
3.24E10/cm3, and the electrical oxide thickness is 1.75 nm. Substituting the
necessary values, σ VT , RDD is calculated from (7.158) and is found to be 17.71 mV.
The same amount of variation is taken for the SPICE parameter VTHO. For
Monte Carlo simulation, a set of 1000 samples has been chosen. The dis-
tribution of the SPICE parameter VTHO is considered to be Gaussian. The
simulation is performed both at low drain bias and high drain bias—that is,
VDS = 50mV and VDS = 1V .
The variations of the gate characteristics of the transistor due to RDD at low
and high drain bias are shown in Figures 7.41(a) and 7.41(b), respectively. The
performance samples are characterized by four measures: mean, standard
deviation, skew factor, and kurtosis. These are summarized in Tables 7.4 and
7.5 for low drain bias and high drain bias, respectively. The distributions of
the samples for the high drain bias case are shown in Figures 7.42(a) through
7.42(c). The distribution of threshold voltage is Gaussian, whereas that for
IOFF and S are log-normal.

7.9.4.2 Statistical Characterization of Line Edge Roughness (LER)

Line edge roughness is the distortion of the gate edge. In order to charac-
terize the distortion of the gate edge, a simplified model of a rough line as
shown in Figure 7.43 is considered. The roughness in the gate edge is char-
acterized by high-frequency roughness and low-frequency roughness. The
gate is divided into segments with characteristic width WC, which character-
izes the change at which the low frequency part changes the gate length.
Within this portion, only high-frequency roughness is present. Assuming
350 Technology Computer Aided Design: Simulation for VLSI MOSFET

1E–5

1E–6
IDS (A) in Log Scale

1E–7

L = 65 nm
1E–8 W = 130 nm
VDS = 0.05 V
1E–9

1E–10

1E–11
0.0 0.2 0.4 0.6 0.8 1.0
VGS
(a)

1E–4

1E–5
IDS (A) in Log Scale

1E–6 L = 65 nm
W = 130 nm
VDS = 1 V
1E–7

1E–8

1E–9

0.0 0.2 0.4 0.6 0.8 1.0

VGS

(b)

FIGURE 7.41
(a) Effect of RDD process variations on the gate characteristics of the MOS transistor at VDS =
50 mV. (b) Effect of RDD process variations on the gate characteristics of the MOS transistor at
VDS = 1 V.
TABLE 7.4
Summary of RDD, LER, and OTV on Subthreshold Slope, OFF Current, and Threshold Voltage at VDS = 50 mV

Statistical RDD LER OTV All

Parameters S IOFF VT S IOFF VT S IOFF VT S IOFF VT
STDEV (σ) 0.568 mV/ 38.8 pA 18.45 4.992e-3 1.89 pA 1.42 mV 0.749 4.888 0.743 mV 0.932 mV/ 39.11 pA 18.52 mV
decade mV mV/ mV/ pA decade
decade decade
MEAN (m) 96.45 mV/ 84.7 pA 0.464 V 96.424 78.40 0.463 V 96.39 78.35 0.463 V 96.45 mV/ 84.97 pA 0.462 V
decade mV/ pA mV/ pA decade
decade decade
SKEW 0.546578 1.255 –0.009 0.246 0.135 –0.026 –0.029 0.107 –0.045 0.918 1.060 –0.012
KURT 0.225871 2.004 –0.177 –1.879 –0.296 –0.302 –0.166 –0.135 –0.182 0.802 1.464 –0.142
MOSFET Characterization for VLSI Circuit Simulation
351
352 Technology Computer Aided Design: Simulation for VLSI MOSFET

140 VT variation due to RDD

120

100
VDS = 1 V
80
Count

60

40

20

0
0.38 0.40 0.42 0.44 0.46 0.48 0.50
VT (V)
(a)

Ioff variation due to RDD

160

120 VDS = 1 V
Count

80

40

0
400.0 p 600.0 p 800.0 p 1.0 n 1.2 n
Ioff (A)

(b)

FIGURE 7.42
(a) Statistical distributions of threshold voltage variations occurring due to RDD at high drain
bias. (b) Statistical distributions of IOFF variations occurring due to RDD at high drain bias. (c)
Statistical distributions of S variations occurring due to RDD at high drain bias. (continued)
MOSFET Characterization for VLSI Circuit Simulation 353

500
S variation due to RDD
450

400

350 VDS = 1 V

300
Count

250

200

150

100

50

0
102.0 m 104.0 m 106.0 m 108.0 m
S (V/decade)
(c)

FIGURE 7.42
(continued) (a) Statistical distributions of threshold voltage variations occurring due to RDD
at high drain bias. (b) Statistical distributions of IOFF variations occurring due to RDD at high
drain bias. (c) Statistical distributions of S variations occurring due to RDD at high drain bias.

fluctuations of two gate edges are uncorrelated, random variation of channel

length due to LER is calculated as follows [29]:

2
σL = σ LER (7.170)
1 + W/WC

The edge locations of two different segments are uncorrelated and have a stan-
dard deviation σ LER. In the present work, effective channel width W = 120 nm,

Transistor Width W

L
Wc

FIGURE 7.43
Simplified model for estimating LER of the gate.
354 Technology Computer Aided Design: Simulation for VLSI MOSFET

WC = 30 nm, and 3σ LER = 4 nm. Substituting these, in (7.170), σ L = 0.843 nm. In

BSIM, the effective channel length is defined in simple form as

Leff = Ldrawn + XL − 2 LINT (7.171)

In (7.171), XL is the channel length offset due to mask/etch effect, and LINT
is the channel length offset parameter. In the present work, XL = −20 nm and
LINT = 3.75 nm. The effects of LER on device performance are simulated in
HSPICE Monte Carlo analysis by varying the value of the parameter XL. For
Monte Carlo simulation, a set of 1000 samples has been chosen. The distribu-
tion of the SPICE parameter XL is considered to be Gaussian. The simulation
is performed both at low drain bias and high drain bias (i.e., VDS = 50 mV
and VDS = 1V ). The effects of LER on the chosen device performances are
summarized in Tables  7.4 and 7.5, respectively. The effect of LER on sub-
threshold slope is not significant due to lack of any direct functional rela-
tionship between the two. However, at high drain bias, the depletion width
changes due to DIBL effect so that fluctuations in subthreshold slope are
observed. The distributions of the samples for the high drain bias case are
shown in Figures 7.44(a) through 7.44(c).

7.9.4.3 Statistical Characterization of OTV

The oxide thickness variation is induced by atom-level interface rough-
ness between silicon and gate dielectric. The minimum magnitude of oxide
thickness variation is the height of one silicon atom layer, which is 2.71 A0.
The effects of OTV on the chosen device performances are summarized in
Tables 7.4 and 7.5, respectively. The distributions of the samples for the high
drain bias case are shown in Figures 7.45(a) through 7.45(c).

7.9.4.4 Statistical Characterization of Simultaneous Variations

In real devices, the various sources of process variations simultaneously
affect the device and circuit performances. This can also be simulated in
HSPICE. The cumulative effects of RDD, LER, and OTV on the chosen
device performances are summarized in Tables 7.4 and 7.5. It is observed
from the simulation results that (7.168) is valid. The relative contribu-
tions of the different process variations on the device performances are
shown in Figures 7.46(a) and 7.46(b). It is observed that in all cases, RDD
is a dominant source of process variations. Therefore, mitigation of RDD
is an important challenge for the device designers for advancement of
nanoscale VLSI circuits. In addition, proper characterization of the
amount of process variability (RDD, LER, OTV) is also extremely impor-
tant, which is not an easy task. An elegant approach for this is to use
backward propagation of the variance method through which these are
TABLE 7.5
Summary of RDD, LER, and OTV on Subthreshold Slope, OFF Current, and Threshold Voltage at VDS = 1 V
RDD LER OTV All
Statistical
Parameters S IOFF VT S IOFF VT S VT VT S IOFF VT
STDEV σ 1.122 109.2 18.27 0.165 14.1 pA 2.904 0.68 125.2 0.061 1.45 mV/ 167.58 pA 18.48 mV
mV/ pA mV mV/ mV mV/ pA mV decade
decade decade decade
MEAN m 101.9 676.1 0.434 101.434 659 pA 0.433 V 101.7 684.6 0.433 101.48 702.30 pA 0.432 V
mV/ pA V mV/ mV/ pA V mV/
decade decade decade decade
MOSFET Characterization for VLSI Circuit Simulation

SKEW 2.123 1.249 –0.010 0.116 0.298 –0.111 1.998 0.992 –0.197 0.888 0.932 –0.004
KURT 5.339 1.979 –0.176 –0.341 –0.198 –0.215 4.846 1.152 0.243 0.978 1.098 –0.117
355
356 Technology Computer Aided Design: Simulation for VLSI MOSFET

160 VT variation due to LER

140

120
VDS = 1 V
100
Count

80

60

40

20

0
0.420 0.425 0.430 0.435 0.440 0.445
VT (V)

(a)

160 Ioff variation due to LER

140

120 VDS = 1 V

100
Count

80

60

40

20

0
620.0 p 640.0 p 660.0 p 680.0 p 700.0 p 720.0 p
Ioff (A)

(b)

FIGURE 7.44
(a) Statistical distributions of threshold voltage variations occurring due to LER at high drain
bias. (b) Statistical distributions of IOFF variations occurring due to LER at high drain bias. (c)
Statistical distributions of S variations occurring due to LER at high drain bias. (continued)
MOSFET Characterization for VLSI Circuit Simulation 357

S variation due to LER

250

200 VDS = 1 V

150
Count

100

50

0
100.8 m 101.2 m 101.6 m 102.0 m
S (V/decade)
(c)

FIGURE 7.44
(continued) (a) Statistical distributions of threshold voltage variations occurring due to LER
at high drain bias. (b) Statistical distributions of IOFF variations occurring due to LER at high
drain bias. (c) Statistical distributions of S variations occurring due to LER at high drain bias.

600
VT variation due to OTV
500

400
Count

VDS = 1 V
300

200

100

0
0.4329 0.4330 0.4331 0.4332 0.4333
VT (V)

(a)

FIGURE 7.45
(a) Statistical distributions of threshold voltage variations occurring due to OTV at high drain
bias. (b) Statistical distributions of IOFF variations occurring due to OTV at high drain bias. (c)
Statistical distributions of S variations occurring due to OTV at high drain bias. (continued)
358 Technology Computer Aided Design: Simulation for VLSI MOSFET

200
Ioff variation due to OTV

150
Count

VDS = 1 V
100

50

0
600.0p 800.0p 1.0n 1.2n
Ioff (A)

(b)

300 S variation due to OTV

250

200
Count

150
VDS = 1 V

100

50

0
101.0 m 102.0 m 103.0 m 104.0 m 105.0 m
S (V/decade)
(c)

FIGURE 7.45
(continued) (a) Statistical distributions of threshold voltage variations occurring due to OTV
at high drain bias. (b) Statistical distributions of IOFF variations occurring due to OTV at high
drain bias. (c) Statistical distributions of S variations occurring due to OTV at high drain bias.
MOSFET Characterization for VLSI Circuit Simulation 359

RDD
40 LER
OTV
ALL
30
(σ/m)*100

VDS = 50 mV
20

10

0
S Ioff VT

Performance Parameters
(a)

RDD
LER
24
OTV
ALL
20

16
(σ/m)*100

12

0
S Ioff VT
Performance Parameters
(b)

FIGURE 7.46
(a) Contributions of different sources of process variabilities on the performance parameters at
VDS = 50 mV. (b) Contributions of different sources of process variabilities on the performance
parameters at VDS = 1 V.
360 Technology Computer Aided Design: Simulation for VLSI MOSFET

estimated from the effects of these process variabilities on circuit perfor-

mances [32].

7.10 Summary and Conclusion

This chapter presents a comprehensive overview about characterizing a
MOS transistor to be used in VLSI circuit simulation. The issues discussed
along with the approaches mentioned are considered by the compact models
used in commercial circuit simulation packages. However, the objective is
to make the designers aware of the various issues related to the present-day
VLSI MOS transistors, such that these are taken care of by the IC design-
ers while designing and optimizing any VLSI circuit. Moreover, with bet-
ter control over the physics of the circuit operations, the design procedure
becomes more perfect and the design effort and time reduce drastically. In the
sub-90 nm design domain, several challenges related to circuit performances
can be solved at the device design level. This offers an additional flexibil-
ity to the designers for designing an optimal circuit without adding any
extra circuit components, thus making the circuit area and power efficient.
Technology-aware circuit design and device-circuit co-design are important
areas of research in nanoscale VLSI circuit design, as presented here in a
comprehensive manner.

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8
Process Simulation of a MOSFET
Using TSUPREM-4 and Medici

Atanu Kundu

CONTENTS
8.1 Introduction.................................................................................................364
8.2 Why Silicon?................................................................................................ 365
8.3 Initial Meshing of the Wafer..................................................................... 366
8.4 Start Material Initialization....................................................................... 367
8.5 Defining the Initial Mesh........................................................................... 368
8.6 N-Buried Layer............................................................................................ 368
8.7 Oxidation and Growth of the Initial Oxide............................................ 368
8.8 Wafer Masking for Buried Layer Implantation...................................... 369
8.9 Screen Oxidation......................................................................................... 371
8.10 Buried Layer Implantation........................................................................ 371
8.11 Buried Layer Drive-In................................................................................ 372
8.12 P-Type Epitaxial Growth............................................................................ 373
8.13 Pad Oxide Formation................................................................................. 374
8.14 Gate Under Channel Doping.................................................................... 375
8.15 Gate Oxide Formation................................................................................ 376
8.16 Gate-Poly Deposition.................................................................................. 377
8.17 Polysilicon Gate Doping............................................................................. 377
8.18 Gate-Poly Mask........................................................................................... 378
8.19 Creation of n+ Source and Drain Regions............................................... 379
8.20 Creation of p+ Region................................................................................ 380
8.21 Borophosphosilicate Glass (BPSG) Deposition....................................... 382
8.22 BPSG Anneal............................................................................................... 383
8.23 Contact Mask Formation............................................................................384
8.24 First Layer of Metal (metal-1) Deposition................................................ 386
8.25 Metal-1 Mask............................................................................................... 386
8.26 Inter-Metal Dielectric (IMD) Deposition................................................. 387
8.27 Second Layer of Metal (metal-2) Mask..................................................... 388
8.28 Second Layer of Metal (metal-2) Deposition........................................... 389
8.29 Metal-2 Final Mask..................................................................................... 389
8.30 MOSFET.inp................................................................................................. 392
8.31 Mask File Named t.tl1................................................................................ 397

363
364 Technology Computer Aided Design: Simulation for VLSI MOSFET

8.32 What Is Medici............................................................................................ 398

8.33 Execution of Command............................................................................. 398
8.34 Interfacing between TSUPREM-4 and Medici....................................... 398
8.35 Rename Electrodes from TSUPREM-4 to Standard Names................. 399
8.36 Major Physical Models...............................................................................400
8.37 Initial Guess/Convergence and Solution Methods................................ 401
8.38 Nonlinear System Solutions and Current-Voltage Analysis................. 402
8.39 Post-Processing and Parameter Extraction............................................. 402
8.40 Drain Current versus Drain Voltage Simulation.................................... 403
8.41 Drain Current versus Gate Voltage Simulation...................................... 405
8.42 Conclusion................................................................................................... 407
References..............................................................................................................408

8.1 Introduction
The objective of this chapter is to fabricate a 5 μm 2D n-MOSFET (n-type
metal-oxide-semiconductor field-effect transistor) using process simulator
TSUPREM-4 [1] and device simulator Medici [2]. SUPREM is the acronym of
Stanford University Process Engineering Modeling. Taurus TSUPREM-4 is for
the version IV, which is a 2D simulation program. TSUPREM-4 is a computer
program for the simulation of the fabrication steps required for the manufacture
of silicon integrated circuits and for other integrated circuits (ICs). TSUPREM-4
simulates the changes in semiconductor structure which take place after various
processing steps used during the actual fabrication procedure.
As the device dimensions have been reduced to micro or nano level, the
specialization and application of technology computer aided design (TCAD)
tools in new device creation for future technology generations are indis-
pensable to harness the ever-increasing complexity and challenges of the
“ever-shrinking transistors.” One of the main advantages of TCAD tools is
visualization. For deep sub-micron devices, it is possible to visualize the evo-
lution of the actual cross-sections of the structure during various process
simulation steps in order to obtain better insight into the IC processing steps.
TSUPREM-4, a popular commercial TCAD process simulator tool, allows
verifying the entire structure after every realistic silicon wafer processing
step via hands-on simulation, without the need for high-cost IC processing
facilities. Moreover, these TCAD tools after calibration exhibit impressive
predictive power with required accuracy, which can be utilized to speed up
the technology integration and transfer to volume manufacturing. Therefore
it is possible to experiment and explore the impact of process flow modifica-
tions at virtually no cost. This results in the possibility of manufacturing
high-yield profitable product with short product development life cycles,
which is absolutely necessary given the huge costs of nanoscale integrated
circuit fabrication lines.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 365

8.2  Why Silicon?

• Silicon can be easily oxidized to form high-quality silicon-dioxide
(SiO2) insulator, which is used as a masking or barrier material for
selective doping steps required for IC fabrication.
• The SiO2 layer is essential in metal-oxide-semiconductor (MOS)
device structure, and high-quality Si-SiO2 interface formation is pos-
sible to form the gate of MOSFET.
• Silicon also has wider band-gap than germanium, which means that
silicon devices can operate at higher temperatures than their germa-
nium counterparts.
• Silicon is available abundantly in nature as its primary constituent
is ordinary sand. So, silicon provides a very low cost source of semi-
conductor device or IC fabrication material.

Actual industrial device fabrication consists of several steps that have been
followed in fabrication procedure. The process starts with initializing a
<100> silicon wafer of 5 μm, and it requires proper meshing of the device.
During the selective doping procedure, several portions of the wafer need
to be masked or covered during various steps of the fabrication. By conven-
tion, the extension .tl1 is used for the mask layout files used by TSUPREM-4.
This mask file named ‘t.tl1’ has been used here as an input file for the entire
device fabrication where nine different mask names have been assigned for
different fabrication steps.
To run any program in TSUPREM-4, the linux environment is required
and one has to type ‘TSUPREM4’ followed by the filename having .inp exten-
sion in the terminal. The file in which the script is written is named MOSFET.
inp. To run this script file, the command would be ‘TSUPREM4 MOSFET.inp’.
With this script file another file is essential to execute the program: the mask
file. The mask file is of extension .tl1. Here the mask file name is t.tl1, which
contains the name of the masks with their length. Mask file has to be linked
with the MOSFET.inp file as an input file in the beginning of its script file by
the command MASK IN.FILE = t.tl1. Now it is possible to call any of its mask
names when required. Here masks used in the t.tl1 file are of names gateoxet,
nbl, Nplus, contact, metal1, metal2, metal3, and gateunderdoping. All lengths are
by default in micrometers. The first statement of the mask file 1e3 or 1000
signifies the length mentioned here divided by 1e3 to convert it into microm-
eters. For example, in the mask named gateoxet, only one length is mentioned
here from (1600–4100); that is why ‘1’ is mentioned after the mask name, like
gateoxet 1. (1600–4100) μm signifies that it is the length 1.6 to 4.1 μm of the 0 to
5 μm device as it is divided by 1e3. Similarly for mask name contact, there are
three lengths, so 3 is mentioned after the mask name contact, like contact 3,
and different lengths are (300–1100), (2550–2850), and (4400–4850).
366 Technology Computer Aided Design: Simulation for VLSI MOSFET

8.3  Initial Meshing of the Wafer

TSUPREM-4 is used to simulate 2D structures [2]. In the TSUPREM-4 coor-
dinate system, the distance from the surface of the wafer into the silicon is
positive (y-axis). The x-axis values are numbered from left to right. The device
performance is mainly dependent on vertical grid-spacing, and grid spacing
is crucial for predictive technology simulation [3,4]. The ‘mesh’ statement gen-
erates and controls the automatic simulation grids for TSUPREM-4. Meshing
refinement is chosen in such a way that meshing density is very high on the
top side of the wafer as the device structure will be grown there, so that car-
rier flow and any other changes occurring due to the terminal voltages will be
found out accurately. The plot shown in Figure 8.1 shows the mesh generation
of the 5μm wafer, where the MASK IN.FILE = t.tl1 statement signifies the input
file name is t and extension is tl1. The output figure will be plotted with name
‘Field,Poly,Contact’. From Figure 8.1, it can be seen that a denser grid is chosen
in the areas where a lot of activity and precision of information are important.
The ‘grid.fac’ parameter multiplies all grid spacing specifications in the
horizontal and vertical directions. By default this is set to 1 which produces
fine grid required for accurate simulations. To increase simulation speed this
value can be increased, but for more accurate simulation ‘grid.fac’ should be

0.00
Distance (microns)

4.00

8.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.1
Initial mesh used for entire device fabrication. Plotted by PLOT.2D GRID statement.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 367

reduced as required. The dx.min, dx.max, dy.surf, dy.activ, and dy.bot param-
eters on the mesh statement are multiplied by grid.fac.
Placement of the grid line in the x direction is controlled by the parameters
‘dx.min,’ dx.max’ in the ‘mesh’ statement. The depth of the surface region in
the vertical grid is controlled by the ‘ly.surf’ parameter. The grid spacing
between horizontal grid lines in the y direction in the surface region is con-
trolled by ‘dy.surf’ parameter. This spacing is used between y = 0 and y =
‘dy.surf’, and the spacing is multiplied by ‘grid.fac’ when it is used. The depth
of the bottom of the active region is controlled by ‘ly.activ’ parameter, and
the grid spacing between horizontal lines at the bottom of the active region
in the y direction of the active region is controlled by ‘dy.activ’ parameter.
The grid spacing varies geometrically between dy.surf at ly.surf and dy.activ
at ly.activ. This spacing is multiplied by grid.fac when it is used. The depth
of the bottom of the structure in the default vertical grid is controlled by
the parameter ‘ly.bot’, and the grid spacing y direction at the bottom of the
structure is controlled by the ‘dy.bot’ parameter. Spacing will be multiplied
by ‘grid.fac’ when it is used.

mesh grid.fac=1.0 dx.min=0.002 dx.max=0.1 ly.surf=0.06

dy.surf=0.001 +
ly.activ=0.5 dy.activ=0.02 ly.bot=10 dy.bot=1
MASK IN.FILE=t.tl1 PRINT GRID=“Field,Poly,Contact”

8.4  Start Material Initialization

Initial material of length 5 μm of <100> Si wafer with initial dose of boron
1e15 cm–3 has been taken to create the device on the initial material. Usually
<100> silicon material is used due to the fact that at the time of fabrica-
tion processing, <100> silicon wafer produces the lowest charges at the
oxide-silicon interface [5–7]. There is a strong dependence on the built-in
charge on the orientation of the silicon crystal. In the case of MOSFET, sur-
face charge is directly related to the sign and magnitude of the threshold
voltage. In case of <100> silicon material, the value of the built-in surface
charge is lowest [3,8]. It also gives higher mobility in the fabricated device.
The ‘initialize’ statement will set up the initial structure including back-
ground doping level, crystal orientation, and resistivity of the wafer for
a simulation. A structure must be initialized after meshing is done and
before any processing steps.

initialize ratio=1.4 <100> rot.sub=0 boron=1e+15 width=5.0

368 Technology Computer Aided Design: Simulation for VLSI MOSFET

8.5  Defining the Initial Mesh

SELECT TITLE=“Initial Mesh”
PLOT.2D GRID C.GRID=8

It is clear from Figure 8.1 that meshing density is very high on the top por-
tion of the wafer as the device structure will be grown there, so carrier flow
and any other changes due to the terminal voltages will take place there.

8.6  N-Buried Layer

An N-buried layer (NBL) is implanted on this wafer which allows source
voltage to be raised above the substrate voltage and to avoid leakage current
toward the base which could be avoided by silicon-on-insulator (SOI) type
devices. SOI structures become very unstable in high voltages as a reverse-
biased drain-bulk p-n junction generates a huge amount of heat that cannot
be dissipated with an insulator, and self heating becomes a serious concern
in terms of device reliability issues [9–10]. Therefore, antimony of dose 1e15
cm–3 (which equals 1 × 1015 cm–3) has been implanted followed by drive in volt-
age to place the NBL layer at the proper position on the wafer. This N-layer in
P-type wafer will create a p-n junction that will stop high bottom leakage cur-
rent flow due to high supply voltage at the drain end. As both initial wafer and
buried layer are doped by boron and antimony of dose 1e15 cm–3, respectively,
a p-n junction of equal depletion depth in both sides will be formed. For the
actual structure an epitaxial layer of 14 μm is grown on this wafer where device
parameter optimization is possible due to this epitaxial layer.

8.7  Oxidation and Growth of the Initial Oxide

The step required for creating an oxide layer on a semiconductor is called
oxidation. For oxidation of silicon, oxygen is made to react with silicon at 800
to 1200°C. For wet oxidation the presence of H2O in the reaction is essential.
Though the dry oxidation rate is slow, the quality of oxide grown in this
procedure is very good. Usually, dry oxidation is done in the presence of
inert gas that acts as a carrier to control oxygen. Inert gas will also ensure
that any other gas cannot take part in this reaction. In TSUPREM-4 the dif-
fusion statement is used for this purpose. For fabrication of desired device
structure, several steps may be used for the oxidation. The first line of the
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 369

statement of the program below signifies that the initial temperature of the
furnace is 800°C which will rise and reach the final temperature 1000°C for
20 minutes. Similar steps will be followed by changing conditions.
This layer is basically grown on the wafer for masking purposes which is
required for the dopant implementation for NBL layer formation. As there is
no mask assigned on it before the diffusion step, the entire SiO2 layer will be
formed on top of the whole wafer.

DIFFUSION TEMPERAT=800 T.FINAL=1000 TIME=20 F.O2=0.5 F.N2=9.5

DIFFUSION TEMPERAT=1000 TIME=65 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=1000 TIME=5 F.O2=9.5
DIFFUSION TEMPERAT=1000 TIME=190 F.O2=5.975 F.H2=10.4 F.HCL=0.475
DIFFUSION TEMPERAT=1000 TIME=1 F.O2=5.5 F.N2=5
DIFFUSION TEMPERAT=1000 TIME=10 F.N2=10
DIFFUSION TEMPERAT=1000 T.FINAL=800 TIME=50 F.N2=10
print layers

8.8  Wafer Masking for Buried Layer Implantation

As the middle portion of wafer material has been chosen for the dopant
implantation for NBL layer formation, so the rest of the wafer top needs to be
covered by masking material, as a negative photoresist is being used here on
the wafer of thickness 1 μm. The mask used here from the mask file (t.tl1) is
nbl. It will be developed and be a selective part of the photoresist, and oxide
will be etched out simultaneously due to the nature of the photoresist mate-
rial and the etchant.

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1

EXPOSE MASK=nbl
DEVELOP
etch oxide

The above sets of commands are used to display the device structure at any
fabrication step as in Figure 8.2. These sets of commands can be used after
every step of fabrication to have a look at the device structure formed at that
point of time. Plot.2D will plot the characteristics, boundaries, junctions, and
depletion edges of the two-dimensional simulated structure. The title of the
paragraph will be printed along with the simulated output as mentioned
here: “Deposition of negative photoresist.” Different colors have been assigned
for different materials to display at the output. Different doping contour is
being plotted by assigning different colors by FOREACH command. This
procedure has been repeated for different dopants such as boron, phosphor,
370 Technology Computer Aided Design: Simulation for VLSI MOSFET

–2.50
Distance (microns)

2.50

7.50

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.2 (See color insert)

Deposition of negative photoresist of thickness 1 μm on grown oxide; a portion (2 to 3 μm) of the
photoresist is being etched out by using mask NBL.

arsenic, and antimony. These dopants are commonly used for any semicon-
ductor fabrication procedure and also used for this device fabrication. After
every step of fabrication, a created structure has been generated and is now
being shown in the figure.

SELECT Z=LOG10(BORON) TITLE=“ Deposition of negative photoresist “

PLOT.2D
COLOR SILICON COLOR=7
COLOR OXIDE COLOR=5
COLOR NITRIDE COLOR=3
COLOR PHOTORESIST COLOR=2
COLOR polysili COLOR=1
COLOR aluminum COLOR=3
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 1)
END
SELECT Z=LOG10(phosphor)
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 3)
END

SELECT Z=LOG10(arsenic)
FOREACH X (19 TO 21 STEP 1)
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 371

COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 5)

END
SELECT Z=LOG10(antimony)
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 7)
END
COLOR OXIDE COLOR=10
COLOR NITRIDE COLOR=3
COLOR PHOTORESIST COLOR=2
COLOR polysili COLOR=1
COLOR aluminum COLOR=3

8.9  Screen Oxidation

A layer of thin oxide is required to form on the wafer at the time of dopant
implantation. This layer of oxide is called screen oxide and it protects the
wafer when dopant bombardment takes place during the ion implanta-
tion procedure. Again, few oxidation steps are required in various con-
trolled conditions.

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=0.5 F.N2=9.5

DIFFUSION TEMPERAT=900 TIME=15 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.0
DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.5
DIFFUSION TEMPERAT=900 TIME=28 F.O2=9.0 F.HCL=0.19
DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.0
DIFFUSION TEMPERAT=900 TIME=30 F.N2=10.0
DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=37.5 F.N2=10
print layers

8.10  Buried Layer Implantation

Due to nbl mask, which is defined as 2000 to 3000 in mask file, which effec-
tively will be 2 to 3 μm as the rule defined in the mask file, there will be
an opening of 2 to 3 μm on the wafer. The statement implant antimony will
implant through it. As few other conditions like dopant angle of dopant
implantation, dose and energy of implanted dopant by which it will be
implanted into the wafer, and the tilt at which it will be implanted need to be
372 Technology Computer Aided Design: Simulation for VLSI MOSFET

mentioned as stated by the line here. It defines tilt as 7° and dopant dose is
1.0 e15 cm–3, and energy of the implanted ion is 100 KeV. After implantation of
the layer of screen oxide and the rest of the oxide layer on which photoresist
was placed, what was used before this step is being removed by the state-
ment ‘etch oxide all’. The photoresist was placed on oxide, so etching of oxide
will automatically remove photoresist.

implant antimony pearson tilt=7 dose=1.0e15 energy=100

etch oxide all

8.11  Buried Layer Drive-In

As shown in Figure 8.3, a buried layer is implanted very close to the surface
of the wafer in the region where it is bombarded. When it is needed to be
placed deep inside the wafer, a drive-in voltage is required to drive these
dopants through the wafer toward the positive Y axis, as shown in Figure 8.4.
Dopant drive-in operation is performed by high temperature. Due to ther-
mal agitation, the dopants will move in the downward direction of the wafer.
So again diffusion statement is required, and at the end of the process a layer

0.00
Distance (microns)

2.00

4.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.3 (See color insert)

Implantation of antimony of pearson tilt = 7, dose = 1.0 e15, and energy = 100, which will be
used as NBL.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 373

0.00
Distance (microns)

4.00

8.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.4 (See color insert)

Placement of antimony dopant in the wafer after the application of drive-in voltage on it.

of SiO2 will be formed automatically by nature, which is needed to be etched

out by the etch oxide all statement.

DIFFUSION TEMPERAT=800 T.FINAL=1200 TIME=100 F.O2=0.5 F.N2=9.5

DIFFUSION TEMPERAT=1200 TIME=600 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=1200 T.FINAL=1000 TIME=67 F.O2=9
DIFFUSION TEMPERAT=1000 TIME=20 F.O2=10
DIFFUSION TEMPERAT=1000 TIME=67 F.O2=5.5 F.H2=10.4
DIFFUSION TEMPERAT=1000 TIME=1 F.O2=5.5 F.N2=5.0
DIFFUSION TEMPERAT=1000 T.FINAL=800 TIME=67 F.N2=10
etch oxide all
print layers

8.12  P-Type Epitaxial Growth

Drive-in voltage will place the NBL layer in proper place in the wafer. This
N-layer in a P-type wafer will create a p-n junction that will stop high bot-
tom leakage current flow due to high supply voltage at the drain end. To
ensure this, both the initial wafer and buried layer are doped by boron and
374 Technology Computer Aided Design: Simulation for VLSI MOSFET

–15.00
Distance (microns)

–5.00

5.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.5 (See color insert)

Placement of NBL and epitaxial growth on the initial wafer.

antimony of dose 1e15 cm–3, respectively. A p-n junction of the same deple-
tion depth on both sides will be formed. For the actual structure an epitaxial
layer of 14 μm is grown on this wafer, as device parameter optimization is
possible in this epitaxial layer. It is always required to grow an epitaxial layer
on the initial wafer, as shown in Figure 8.5, to avoid crystal defects in the
initial wafer and parameter optimization is convenient in this epitaxial layer.
The statement epitaxy will create an epitaxial layer of 14 μm which will
grow on this initial wafer [9–12], as stated below.

EPITAXY TIME=14 TEMPERAT=1150 THICKNES=14 dx =.001 ydy=0.0

SPACES=100 +
RESISTIV BORON=45
print layers

8.13  Pad Oxide Formation

During the masking process, as shown in Figure 8.6, the masking materials,
nitride, and photoresist are not deposited directly on the wafer, as strain
would be created on the wafer when the photoresist hardens due to ultravio-
let (UV) light. This strain on the silicon material may change the property
of the silicon material. So whenever this layer for masking is deposited, it is
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 375

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.6 (See color insert)

Pad oxide on the wafer is shown; here the y-axis has been chosen up to −12 μm.

always essential to grow a layer of oxide on the wafer to avoid strain. Hence,
a layer of 500 A0 SiO2 has been grown here using the following statements.

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=9.0

DIFFUSION TEMPERAT=900 TIME=15 F.O2=9.0
DIFFUSION TEMPERAT=900 TIME=18 F.O2=5.5 F.H2=10.4
DIFFUSION TEMPERAT=900 TIME=1 F.O2=5.5 F.N2=5.0
DIFFUSION TEMPERAT=900 TIME=10 F.N2=10
DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=25 F.N2=10
print layers

8.14  Gate Under Channel Doping

Gate under substrate region is doped in this portion by boron of dose
2.0 e11cm–3. The mask chosen has been named ‘gateunderdoping’. Threshold
voltage modification can be done by this doping. The statements needed to
perform this doping procedure are given below. With the dose 2.0 e11cm–3,
threshold voltage achieved is 0.65 V.

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1

EXPOSE MASK=gateunderdoping
376 Technology Computer Aided Design: Simulation for VLSI MOSFET

DEVELOP
etch nitride
etch oxide thickness=0.02
implant boron pearson tilt=7 dose=2.0e11 energy=100
etch nitride all

8.15  Gate Oxide Formation

For a MOS structure, gate oxide has to be formed. As gate length has been
chosen 1.6 to 4.1 μm or effectively 2.5 μm, so the rest of the wafer has to be
covered by mask, as shown in Figure 8.7. A mask has been assigned a length
of 1600 to 4100 named gateoxet in mask file. As photoresist used here in most
of the cases is the negative type, part of the length mentioned in the mask
file will be dissolved when it is developed. Now the oxidation steps have
been executed to form the gate oxide at the end of the oxidation steps. The
entire photoresist and nitride will be removed from the remaining part of
the wafer.

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=0.25 F.N2=10

DIFFUSION TEMPERAT=900 TIME=5 F.O2=0.25 F.N2=10
DIFFUSION TEMPERAT=900 TIME=3 F.O2=9.5
DIFFUSION TEMPERAT=900 TIME=47.5 F.O2=9.5 F.HCL=0.19

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.7 (See color insert)

Structure of the wafer after formation of the gate oxide.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 377

DIFFUSION TEMPERAT=900 TIME=3 F.O2=9.5

DIFFUSION TEMPERAT=900 TIME=15 F.N2=10.0
DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=37.5 F.N2=10
print layers
etch Photoresist
etch nitride all

8.16  Gate-Poly Deposition

MOS gate material may be polysilicon or metals [13]. As a gate metal, molybde-
num or aluminum can be used. Polysilicon is polycrystalline silicon, a material
consisting of small silicon crystals. Though polysilicon gate has severe disad-
vantages, such as low conductivity which can cause occurrence of delay in
circuits as well as unwanted variation of threshold voltage of the MOSFET
due to polysilicon depletion effect, polysilicon has several advantages over
the metal gate. Polysilicon behaves like a perfect conductor once a poly-layer
is doped properly, and it will reduce the delay in channel formation [14–17].
Typically doping concentrations are of the order of 1020 atoms cm–3. The main
reason for use of the polysilicon gate is that fabrication processes require very
high temperature annealing after the initial doping to passivate the radiation
damage caused to the silicon crystal structure by the ion implantation [18–
19]. Metal gate would melt under such conditions, whereas polysilicon will
not. Polysilicon needs a single-step process of etching, whereas a metal gate
requires multiple steps. Threshold voltage of the MOSFET is corrected with
the work function difference between the gate and the channel.
The statement below will deposit polysilicon on the entire wafer in the
ambient temperature 625°C and pressure of 1.0 atmosphere. This statement
also mentions the thickness of the deposited polysilicon material which is
mentioned here as 0.4 μm. This polysilicon material will be used as polysili-
con gate material of the MOSFET, as shown in Figure 8.8.

deposition polysili temperature=625 pressure=1.0 thickness=0.4

concentr

8.17  Polysilicon Gate Doping

Polysilicon doping is done by the following expression which is essential to
increase the conductivity of the gate material.

DIFFUSION TEMPERAT=950 TIME=20 INERT

378 Technology Computer Aided Design: Simulation for VLSI MOSFET

–14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.8 (See color insert)

Polysilicon material deposition on the grown gate oxide material.

8.18  Gate-Poly Mask

The polysilicon material is deposited on the entire wafer as shown in
Figure 8.9. It is necessary to remove the unnecessary extra portion of poly-
silicon and oxide from the wafer. Here polysilicon is deposited on the total
length of the gate oxide. So the same mask gateoxet has been called again, and
the photoresist used here is a positive type so that from length 1600 to 4100
of the photoresist will remain on it and will use it as a mask for that portion.
The remaining part of the photoresist will be dissolved when it is devel-
oped. This part nitride and polysilicon will be etched out by etch nitride and
etch polysili statements. After the selective polysilicon etching, the remaining
nitride will be removed using the etch nitride all statement. Figure 8.10 shows
2.5 μm polysilicon gate formation on the gate oxide.

DEPOSITION NITRIDE THICKNES=0.10 CONCENTR

DEPOSIT PHOTORESIST POSITIVE THICKNESS=1
EXPOSE MASK=gateoxet
DEVELOP
etch nitride
etch polysili
etch nitride all
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 379

–14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.9 (See color insert)

Polysilicon gate formation on the gate oxide after selective polysilicon material by etching from
the wafer; polysilicon gate length is 2.5 μm.

8.19  Creation of n+ Source and Drain Regions

The next step of fabrication is to create source and drain regions for the
n-MOSFET, as shown in Figure  8.10. For n-type doping, arsenic dopant is
used. The mask name used to mask the rest of the wafer is Nplus. Two lengths
assigned in the Nplus mask are of lengths 900 to 1500 and 4200 to 4900. To
cover the rest of the wafer top, it must be masked. So a negative photoresist has
been deposited and mask name Nplus has been called, followed by the mask
develop stage. From 0.9 to 1.5 μm and 4.2 to 4.9 μm there will not be any pho-
toresist as the mask deposited was negative-type photoresist. Now the nitride
and oxide materials from these portions will also be removed to implant
arsenic in these regions for source/drain formation in the above-mentioned
regions. Here arsenic of dose 6.0 e15 cm–3 with energy 100 keV has been doped
in equal and opposite tilt 7° and –7° to get a source drain shape. After comple-
tion, source drain doping, photoresist, and nitride are removed from the entire
wafer which was used as a mask at the time of source/drain doping.

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=Nplus
DEVELOP
etch nitride
380 Technology Computer Aided Design: Simulation for VLSI MOSFET

–14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.10 (See color insert)

Device structure after source and drain formation.

etch oxide
implant arsenic pearson tilt=7 dose=6.0e15 energy=100
implant arsenic pearson tilt=-7 dose=6.0e15 energy=100
etch PHOTORESIST
etch nitride all

8.20  Creation of p+ Region

The next step is to create a p region that will remain connected to the sub-
strate material and finally work as a bulk material. This p region mask length
is chosen as 100 to 700, which means 0.1 to 0.7 μm, and the mask is named
pplus. Figure 8.11 shows the formation of the p region that will be used as
bulk material.
DEPOSITION NITRIDE THICKNES=0.15 CONCENTR
DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=pplus
DEVELOP
etch nitride
etch oxide
IMPLANT BORON PEARSON RP.EFF DOSE=1.0e15 ENERGY=30

Photoresist and nitride from the remaining part will be removed by etch pho-
toresist and etch nitride all statements. Figure 8.12 shows the structure achieved
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 381

–15.00
Distance (microns)

–14.00

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.11 (See color insert)

Formation of the p region in the wafer of length 0.1 to 0.7 μm.

–14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.12 (See color insert)

The structure achieved by executions of etch photoresist and etch nitride all statements.
382 Technology Computer Aided Design: Simulation for VLSI MOSFET

by executions of etch photoresist and etch nitride all statements. In this structure
it is evident that bulk, source, and drain regions are formed by doping the
wafer. Gate oxide and polysilicon deposition on the gate oxide are also being
formed. The next step is to create metal contacts for the different regions for
its terminals to connect the device with the outer world. To perform this next
step, borophosphosilicate glass (BPSG) deposition and anneal are required.
The diffusion statement causes annealing to occur. If the anneal occurs in an
oxidizing ambient, then silicon oxidation will occur on the exposed silicon
material surface. It is common to specify multiple anneal steps in sequence in
order to accurately model a specific furnace process. Semiconductor material
needs annealing after every ion implantation step. It will repair the damages
caused in the lattice during ion bombardment by the collisions with doping
ions. It also allows doping impurities to diffuse further into the bulk.

etch PHOTORESIST
etch nitride all

8.21  Borophosphosilicate Glass (BPSG) Deposition

Borophosphosilicate glass (BPSG), shown in Figure 8.13, is important in the
fabrication of silicon-based lightweight devices and integrated circuits [20]. It

–15.00
Distance (microns)

–13.00

–11.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.13 (See color insert)

Borophosphosilicate glass deposition before the first layer of metal contact to the device.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 383

consists of the final silica glass films. BPSG can be fabricated by several meth-
ods like CVD (chemical vapor deposition), sol-gel, and FHD (flame hydroly-
sis deposition). Usually the CVD procedure is used to form BPSG films
[3, 21, 23]. BPSG provides void free fill of 0.2 to 0.8 μm wide spaces between
succeeding higher metals or conducting layers. BPSG basically works as an
insulating layer for inter-metal layers.

deposition oxide thickness=0.7 concentr

8.22  BPSG Anneal

Deposited borophosphosilicate glass needs annealing, as shown in
Figure 8.14, which will be performed by the following steps:

DIFFUSION TEMPERAT=800 TIME=20 F.N2=10.0

DIFFUSION TEMPERAT=800 TIME=15 F.O2=9.5

The BPSG layer deposited on it is not smooth due to uneven device struc-
ture. It needs chemical-mechanical polishing (CMP) [3, 24, 25]. A nitride layer of
thickness 0.15 µm is deposited on it to determine the minimum y coordinate and

–15.00
Distance (microns)

–13.00

–11.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.14 (See color insert)

Structure of the device after application of annealing step for BPSG.
384 Technology Computer Aided Design: Simulation for VLSI MOSFET

–14.00
Distance (microns)

–12.00

–10.00

–8.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.15 (See color insert)

Polishing of the device top surface by removal of excess oxide.

is named CMP1. During polishing, the oxide above that minimum y coordinate
is etched out to make the surface smooth. Thus four points are defined using
the minimum y coordinate for two points, and the uneven portion is removed
by etch operations. After the removal of this oxide a smooth surface can be
achieved, and this can be seen from Figure 8.15. Statements below will perform
this CMP task.
DEPOSITION NITRIDE THICKNES=0.15 CONCENTR
extract nitride/oxide y.extract minimum name=CMP1
etch nitride all
ETCH OXIDE START X=0.0 Y=-14.6
ETCH CONTINUE X=5 Y=-14.6
ETCH CONTINUE X=5.0 Y=@CMP1
ETCH DONE X=0.0 Y=@CMP1

8.23  Contact Mask Formation

For metal contacts of different terminals like bulk, source, gate, and drain,
metallization is required. Aluminum is used most of the time for metal-
lization in integrated circuits, because aluminum and its alloys have low
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 385

–14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.16 (See color insert)

Selective etching has been performed to deposit aluminum through it for the first layer of
metal contacts.

resistivity (2.7 μΩ for aluminum). Aluminum adheres well to silicon diox-

ide, though use of aluminum in shallow junctions may create problems like
spiking and electromigration. A mask named contact has been assigned in
the mask file having three lengths assigned to it: one to create source-bulk
contact, one for gate, and one for drain contact. Three lengths assigned
to the mask contacts are 300 to 1100, 2550 to 2850, and 4400 to 4850, or
effectively 0.3 to 1.1 μm, 2.55 to 2.85, and 4.4 to 4.85 μm. The first mask is
chosen in such a way that both bulk and source region contact formation
are possible, as for an n-MOSFET bulk and source normally remain in the
same potential most of the time. The second region from 2.5 to 2.85 μm is
chosen for gate contact, and the last region from 4.4 to 4.85 μm is for drain
contact. Figure 8.16 shows the structure where selective etching has been
performed, after which aluminum is deposited through those regions for
the contacts.

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1

EXPOSE MASK=contact
DEVELOP
etch oxide
etch PHOTORESIST
386 Technology Computer Aided Design: Simulation for VLSI MOSFET

8.24  First Layer of Metal (metal-1) Deposition

The statement below will deposit aluminum of thickness 0.3 µm on the entire
material.
deposition aluminum thickness=0.3 concentr

8.25  Metal-1 Mask

As the metal will be deposited on the entire wafer, the undesired part of
the metal must be removed from the entire material. So another mask is
assigned in the mask file and called here. The mask name is metal1, which
has three regions assigned in it. The regions are 150 to 1200, 2400 to 3000, and
4300 to 4950, meaning 0.15 to 1.2 μm, 2.4 to 3.0 μm, and 4.3 to 4.95 μm. Only on
these regions will the aluminum remain on the wafer, as the contact material
and rest of the aluminum will be removed by an etch statement. Figure 8.17
shows the final structure formed after deposition on metal.

DEPOSIT PHOTORESIST POSITIVE THICKNESS=1

EXPOSE MASK=metal1
DEVELOP

–14.50

–14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.17 (See color insert)

First layer of metal deposition through the opening of BPSG for the direct contacts from the device.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 387

etch aluminum
etch PHOTORESIST

8.26  Inter-Metal Dielectric (IMD) Deposition

For final outer world connection to the device another layer of metallization
is required [3]. Another layer of oxide which is called inter-metal dielectric
(IMD) is deposited here by the statement below of thickness 0.5 μm which
is shown in Figure  8.18. From the figure it is obvious that the top surface
requires chemical-mechanical polishing again.

deposition oxide thickness=0.5 concentr

To polish the top surface, a layer of nitride of thickness 0.15 µm is depos-

ited on it to determine minimum y coordinates at which nitride and oxide
meet. Until that point, oxide is etched to get a smooth oxide on the top.
Figure 8.19 shows the structure in which the top surface is smoothened by
CMP operation.

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR

extract nitride/oxide y.extract minimum name=CMP2
etch nitride all

–15.00
Distance (microns)

–14.00

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.18 (See color insert)

Deposition of IMD after formation of the first layer of metal contacts.
388 Technology Computer Aided Design: Simulation for VLSI MOSFET

–14.50

–14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.19 (See color insert)

Structure achieved by smoothening the top surface by the polishing operation again.

ETCH OXIDE START X=0.0 Y=-15.2

ETCH CONTINUE X=5 Y=-15.2
ETCH CONTINUE X=5.0 Y=@CMP2
ETCH DONE X=0.0 Y=@CMP2

8.27  Second Layer of Metal (metal-2) Mask

For the final layer of metallization, another mask is required and through its
opening another layer of metal is deposited on it. The mask assigned here
is named metal-2 and three regions assigned here are 200 to 1100, 2000 to
3100, and 4200 to 4900 to connect this layer to the previous layer of metal.
Figure 8.20 shows the opening regions through which the next layer of metal
will be deposited.

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1

EXPOSE MASK=metal2
DEVELOP
etch oxide
etch PHOTORESIST
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 389

–14.50

–14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.20 (See color insert)

Opening region has been created by etching through which the second layer of metal will be
deposited.

8.28  Second Layer of Metal (metal-2) Deposition

Now the aluminum of thickness 0.2 μm will be deposited on it, as shown in
Figure 8.21 for the next layer of metallization.

deposition aluminum thickness=0.2 concentr

etch PHOTORESIST

8.29  Metal-2 Final Mask

Figure 8.22 shows a layer of aluminum is deposited on the top, in which a part
of metal is essential and the remaining part has to be removed from the top
portion. The following statements will remove the undesired metal from it,
lengths assigned in the mask file named metal3 are 200 to 1100, 2200 to 3100,
and 4200 to 4900, or effectively 0.2 to 1.1 μm, 2.2 to 3.1 μm, and 4.2 to 4.9 μm.
Figure 8.23 shows the final device structure.

DEPOSIT PHOTORESIST positive THICKNESS=1

EXPOSE MASK=metal3
390 Technology Computer Aided Design: Simulation for VLSI MOSFET

–15.00

–14.00
Distance (microns)

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.21 (See color insert)

Second layer of metal is being deposited and connected to the first layer of the metal through
the openings.

–15.00

–14.00
Distance (microns)

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

FIGURE 8.22 (See color insert)

Final device structure, y coordinate is taken up to –12.0 µm.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 391

–15.00
Distance (microns)

–5.00

5.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

FIGURE 8.23 (See color insert)

Final simulated structure of the 5 µm MOSFET.

DEVELOP
etch aluminum
etch PHOTORESIST

SELECT Z=LOG10(BORON)
PLOT.2D GRID C.GRID=3
COLOR SILICON COLOR=7
COLOR OXIDE COLOR=5
COLOR NITRIDE COLOR=3
COLOR PHOTORESIST COLOR=2
COLOR polysili COLOR=1
COLOR aluminum COLOR=3
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 1)
END

SELECT Z=LOG10(phosphor)
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 3)
END

SELECT Z=LOG10(arsenic)
FOREACH X (19 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 5)
END
SELECT Z=LOG10(antimony)
392 Technology Computer Aided Design: Simulation for VLSI MOSFET

FOREACH X (14 TO 21 STEP 1)

COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 7)
END
COLOR OXIDE COLOR=10
COLOR NITRIDE COLOR=3
COLOR PHOTORESIST COLOR=2
COLOR polysili COLOR=1
COLOR aluminum COLOR=3

savefile medici out.file=LDNBL.str

coordinat

8.30 MOSFET.inp
The complete program is given below, and a final full view of the structure
is shown in Figure 8.23.

$nitial mesh

mesh grid.fac=1.0 dx.min=0.002 dx.max=0.1 ly.surf=0.06

dy.surf=0.001 +
 ly.activ=0.5 dy.activ=0.02 ly.bot=10 dy.bot=1

MASK IN.FILE=t.tl1 PRINT GRID=“Field,Poly,Contact”

$start material
initialize ratio=1.4 <100> rot.sub=0 boron=1e+15 width=5.0

$ Plot initial mesh

SELECT TITLE=“Initial Mesh”
PLOT.2D GRID C.GRID=8

$ Grow the initial ox... E2010

DIFFUSION TEMPERAT=800 T.FINAL=1000 TIME=20 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=1000 TIME=65 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=1000 TIME=5 F.O2=9.5
DIFFUSION TEMPERAT=1000 TIME=190 F.O2=5.975 F.H2=10.4 F.HCL=0.475
DIFFUSION TEMPERAT=1000 TIME=1 F.O2=5.5 F.N2=5
DIFFUSION TEMPERAT=1000 TIME=10 F.N2=10
DIFFUSION TEMPERAT=1000 T.FINAL=800 TIME=50 F.N2=10
print layers

$ NBL mask
DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=nbl
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 393

DEVELOP

etch oxide

$ Screen oxidation... E8020

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=900 TIME=15 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.0
DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.5
DIFFUSION TEMPERAT=900 TIME=28 F.O2=9.0 F.HCL=0.19
DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.0
DIFFUSION TEMPERAT=900 TIME=30 F.N2=10.0
DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=37.5 F.N2=10
print layers

$ Buried layer implant

implant antimony pearson tilt=7 dose=1.0e15 energy=100
etch oxide all

$ Buried layer drive-in... E0381

DIFFUSION TEMPERAT=800 T.FINAL=1200 TIME=100 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=1200 TIME=600 F.O2=0.5 F.N2=9.5
DIFFUSION TEMPERAT=1200 T.FINAL=1000 TIME=67 F.O2=9
DIFFUSION TEMPERAT=1000 TIME=20 F.O2=10
DIFFUSION TEMPERAT=1000 TIME=67 F.O2=5.5 F.H2=10.4
DIFFUSION TEMPERAT=1000 TIME=1 F.O2=5.5 F.N2=5.0
DIFFUSION TEMPERAT=1000 T.FINAL=800 TIME=67 F.N2=10
etch oxide all
print layers

$ Epi growth, P-type, 30-60 ohm-cm, 14 um

EPITAXY TIME=14 TEMPERAT=1150 THICKNES=14 dx =.001 ydy=0.0

SPACES=100 +
 RESISTIV BORON=45

$ Pad oxide, tox=500A

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=9.0
DIFFUSION TEMPERAT=900 TIME=15 F.O2=9.0
DIFFUSION TEMPERAT=900 TIME=18 F.O2=5.5 F.H2=10.4
DIFFUSION TEMPERAT=900 TIME=1 F.O2=5.5 F.N2=5.0
DIFFUSION TEMPERAT=900 TIME=10 F.N2=10
DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=25 F.N2=10
print layers

$ N-tub mask
DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=gateunderdoping
394 Technology Computer Aided Design: Simulation for VLSI MOSFET

DEVELOP
etch nitride
etch oxide thickness=0.02
implant boron pearson tilt=7 dose=2.0e11 energy=100
etch nitride all

$ Gate oxide-2 200A

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=gateoxet
DEVELOP

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=0.25 F.N2=10

DIFFUSION TEMPERAT=900 TIME=5 F.O2=0.25 F.N2=10
DIFFUSION TEMPERAT=900 TIME=3 F.O2=9.5
DIFFUSION TEMPERAT=900 TIME=47.5 F.O2=9.5 F.HCL=0.19
DIFFUSION TEMPERAT=900 TIME=3 F.O2=9.5
DIFFUSION TEMPERAT=900 TIME=15 F.N2=10.0
DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=37.5 F.N2=10
print layers
etch Photoresist
etch nitride all

$ Gate-poly deposition - 4000A

deposition polysili temperature=625 pressure=1.0 thickness=0.4
concentr
$ Poly doping
DIFFUSION TEMPERAT=950 TIME=20 INERT
$ Gate-poly mask
DEPOSITION NITRIDE THICKNES=0.10 CONCENTR
DEPOSIT PHOTORESIST POSITIVE THICKNESS=1
EXPOSE MASK=gateoxet
DEVELOP
etch nitride
etch polysili
etch nitride all

$ N+ mask and implant

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR
DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=Nplus
DEVELOP
etch nitride
etch oxide
implant arsenic pearson tilt=7 dose=6.0e15 energy=100
implant arsenic pearson tilt=-7 dose=6.0e15 energy=100

etch PHOTORESIST
etch nitride all
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 395

$ P+ mask and implant

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR
DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=pplus
DEVELOP
etch nitride
etch oxide
IMPLANT BORON PEARSON RP.EFF DOSE=1.0e15 ENERGY=30
etch PHOTORESIST
etch nitride all
$ BPSG deposition
deposition oxide thickness=0.7 concentr
$ BPSG anneal
DIFFUSION TEMPERAT=800 TIME=20 F.N2=10.0
DIFFUSION TEMPERAT=800 TIME=15 F.O2=9.5

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR

extract nitride/oxide y.extract minimum name=CMP1
etch nitride all
ETCH OXIDE START X=0.0 Y=-14.6
ETCH CONTINUE X=5 Y=-14.6
ETCH CONTINUE X=5.0 Y=@CMP1
ETCH DONE X=0.0 Y=@CMP1
$ Contact mask
DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=contact
DEVELOP
etch oxide
etch PHOTORESIST
$ Metal-1 Deposition
deposition aluminum thickness=0.3 concentr

$ Metal-1 mask
DEPOSIT PHOTORESIST positive THICKNESS=1
EXPOSE MASK=metal1
DEVELOP
etch aluminum
etch PHOTORESIST
$ IMD dep
deposition oxide thickness=0.5 concentr

DEPOSITION NITRIDE THICKNES=0.15 CONCENTR

extract nitride/oxide y.extract minimum name=CMP2
396 Technology Computer Aided Design: Simulation for VLSI MOSFET

etch nitride all

ETCH OXIDE START X=0.0 Y=-15.2
ETCH CONTINUE X=5 Y=-15.2
ETCH CONTINUE X=5.0 Y=@CMP2
ETCH DONE X=0.0 Y=@CMP2

$ metal2 mask
DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1
EXPOSE MASK=metal2
DEVELOP
etch oxide
etch PHOTORESIST
$ Metal-2 Deposition
deposition aluminum thickness=0.2 concentr
etch PHOTORESIST
$ Metal-2 final mask
DEPOSIT PHOTORESIST positive THICKNESS=1
EXPOSE MASK=metal3
DEVELOP
etch aluminum
etch PHOTORESIST

SELECT Z=LOG10(BORON)
PLOT.2D GRID C.GRID=3
COLOR SILICON COLOR=7
COLOR OXIDE COLOR=5
COLOR NITRIDE COLOR=3
COLOR PHOTORESIST COLOR=2
COLOR polysili COLOR=1
COLOR aluminum COLOR=3
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 1)
END
SELECT Z=LOG10(phosphor)
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 3)
END
SELECT Z=LOG10(arsenic)
FOREACH X (19 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 5)
END
SELECT Z=LOG10(antimony)
FOREACH X (14 TO 21 STEP 1)
COLOR MIN.V=X MAX.V=(X + 1) COLOR=(X - 7)
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 397

END
COLOR OXIDE COLOR=10
COLOR NITRIDE COLOR=3
COLOR PHOTORESIST COLOR=2
COLOR polysili COLOR=1
COLOR aluminum COLOR=3

savefile medici out.file=LDNBL.str

8.31  Mask File Named t.tl1

The mask file named t.tl1 is given here because it was used during the fabri-
cation of the device. This mask file should be kept in the same folder where
the files are kept, especially the actual device fabrication file MOSFET.inp.
The first line identifies the file format that contains the character ‘TL1’ fol-
lowed by a space and a four-digit binary number. The version of Taurus-
Layout that created the file is represented by the binary number. The
current version of the Taurus-Layout specifies values from 0000 to 0100.
Nine masks are being used in this file named gateoxet, nbl, Nplus, pplus,
contact, metal1, metal2, metal3, and gateunderdoping, and that is why nine is
mentioned in the fourth line of this mask file. This information must be
provided before the mask names and their dimensions. Total length of the
wafer must also be provided, as it is mentioned here 0 to 5000 or 5 μm by
the rule assigned here.

TL1 0100

1e3
  0 5000
9
gateoxet 1
  1600 4100
nbl 1
  2000 3000
Nplus 2
  900 1500
  4200 4900
pplus 1
  100 700
contact 3
  300 1100
  2550 2850
  4400 4850
metal1 3
  150 1200
398 Technology Computer Aided Design: Simulation for VLSI MOSFET

  2400 3000
  4300 4950
metal2 3
  500 900
  2600 2800
  4500 4750
metal3 3
  200 1100
  2200 3100
  4200 4900
gateunderdoping 1
  1600 3700

8.32  What Is Medici

Taurus Medici is a 2D device simulator that can model the electrical, ther-
mal, and optical characteristics of any semiconductor device like MOSFETs,
bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs),
power devices, insulated-gate bipolar transistors (IGBTs), high electron
mobility transistors (HEMTs), charge-coupled devices (CCDs), and photode-
tectors [2]. It also can be used for design and optimization of a device to meet
performance goals without having to manufacture the actual device, thereby
reducing the need for costly experiments. Once the device structure is fab-
ricated using TSUPREM-4, it is saved in the (LDNBL.str) file where detailed
description about it is saved in the file named LDNBL whose extension is str,
or structure. Here the Medici simulator has been used to analyze the fabri-
cated MOSFET electrical characteristics. To do that an interface is necessary
between TSUPREM-4 and Medici.

8.33  Execution of Command

Execution of Medici is initiated with the following command, medici or medici
<filename>. The Medici file name given here is BVNBL.inp, so at the time of
execution of this Medici script file, the command would be medici BVNBL.inp.

8.34  Interfacing between TSUPREM-4 and Medici

A meaningful simulated device fabrication is possible if it is based on a real
fabrication procedure. It is also essential to analyze the fabricated device perfor-
mance, especially electrical characteristics, for realistic device structure. For this
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 399

purpose it is necessary to create an interface between TSUPREM-4 and Medici.

The output structure (having extension .str) file is saved during TSUPREM-4
simulation in such a way that it can be used in the Medici script file. It is done
by the expression ‘savefile medici out.file = LDNBL.str’ of the last line of the
TSUPREM-4 script. This file ‘LDNBL.str’ is basically created to incorporate the
device structure in Medici for its output characteristics analysis. The same file is
called to read the simulation meshing information by the following statement.
MESH IN.FILE=LDNBL.str TSUPREM4 ELEC.BOT POLY.ELEC Y.MAX=10

8.35  Rename Electrodes from TSUPREM-4 to Standard Names

Three metal contacts of the simulated device will be named as 1, 2, and 3
by default at the end of the TSUPREM-4 simulation. After the simulation
the program numbered the left-most metal contact (Source and Bulk in this
case) as 1. In accordance with this numbering scheme, Table 8.1 represents
the electrode names and their coordinate positions.
The minimum and maximum x and y positions of different electrodes will
be automatically created at the end of the TSUPREM-4 simulation.
The electrode name 1 will be renamed Source by the expression ‘RENAME
ELECTR OLDNAME = 1 NEWNAME = Source’ in Medici. Similarly, elec-
trodes 2 and 3 will be renamed as Gate and Drain. After renaming the elec-
trodes to the actual standard device name, the mesh file has been saved with
the new electrode name by the expression ‘SAVE MESH OUT.FILE = BVNBL’
in the ext line. The following commands will plot the device structure in the
screen with proper labeling as mentioned in the expressions.

RENAME ELECTR OLDNAME=1 NEWNAME=Source

RENAME ELECTR OLDNAME=2 NEWNAME=Gate
RENAME ELECTR OLDNAME=3 NEWNAME=Drain

SAVE MESH OUT.FILE=BVNBL

PLOT.2D GRID FILL TITLE=“Structure from TSUPREM-4”
PLOT.1D DOPING LOG X.START=0 X.END=0 Y.START=0 Y.END=2
+   POINTS BOT=1E14 TOP=1E21 TITLE=“S/D Profile”
PLOT.1D DOPING LOG X.START=1.8 X.END=1.8 Y.START=0 Y.END=2

TABLE 8.1
Electrode Names and Their Coordinate Positions
Electrode Number of X-min X-max Y-min Y-max
Name Nodes (microns) (microns) (microns) (microns)
1 50 0.1500 1.1500 −14.5918 −13.3914
2 21 2.2000 3.1000 −14.5918 −13.7969
3 32 4.2000 4.9500 −14.5918 −13.3868
400 Technology Computer Aided Design: Simulation for VLSI MOSFET

+   POINTS BOT=1E14 TOP=1E19 TITLE=“Channel Profile”

PLOT.2D BOUND FILL L.ELEC=-1 TITLE=“Impurity Contours”
CONTOUR DOPING LOG MIN=14 MAX=20 DEL=1 COLOR=2
CONTOUR DOPING LOG MIN=-20 MAX=-14 DEL=1 COLOR=1 LINE=2

8.36  Major Physical Models

For accurate simulations, a number of physical models are incorporated
into the program. Depending on the type of device structure and the
device type models like recombination, mobility, band-gap narrowing,
band-to-band tunneling, photogeneration, impact ionization, and lifetime
can be incorporated.

• Medici also includes semiconductor statistics like Boltzmann

and Fermi-Dirac statistics including the incomplete ionization of
impurities.
• Different recombination models like SRH, Auger, direct, surface
recombinations, and concentration-dependent lifetimes can be
incor­pora­ted.
• Carrier mobility and scattering are very important phenomena in
the mechanism of electrical transport of the device. Mobility models
can be divided into two major categories:
• Low and high field mobility
• Surface scattering and electron hole scattering

Low field mobility models are

1. Constant mobility that can be specified with the MUN0 and
MUP0 parameters for electron and hole.
2. Concentration dependent mobility can be incorporated with the
CONMOB parameter.
3. Either of the two analytic mobility models can be incorporated
with the ANALYTIC or ARORA parameters.
4. Carrier-carrier scattering mobility can be incorporated with the
CCSMOB parameter.
5. Philips unified mobility can be incorporated with the
PHUMOB parameter.

High field mobility models are

1. Field-dependent mobility that can be incorporated with the
FLDMOB parameter.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 401

2. Caughey-Thomas mobility can be incorporated with the

FLDMOB = 1 parameter.
3. Gallium arsenide–like mobility can be incorporated with the
FLDMOB = 2 parameter.
4. Hewlett-Packard mobility can be incorporated with the
HPMOB parameter.

Surface scattering mobility models are

1. Surface mobility model can be incorporated with the SRFMOB
parameter.
2. Enhanced surface mobility model can be incorporated with the
SRFMOB2 parameter.
3. Perpendicular field dependent mobility model can be incorpo-
rated with the PRPMOB parameter.
4. Lombardi surface mobility model can be incorporated with the
LSMMOB parameter.
5. A number of MOS inversion layer models are available through
the parameters UNIMOB, LSMMOB, GMCMOB, SHIRAMOB,
and TFLDMOB.
One or more models to be included in a Medici simulation can be specified in
models statement. For this device simulation models such as lsmmob, fldmob,
auger, bgn, btbt, fermi, incomplete, energy.l and high.dop have been incorpo-
rated by the ‘models lsmmob fldmob auger bgn btbt fermi incomplete energy.l high.
dop’ statement below.

models lsmmob fldmob auger bgn btbt fermi incomplete energy.l

high.dop

8.37  Initial Guess/Convergence and Solution Methods

Depending on the device structure and the range of its operation, one solu-
tion method may not be optimal in all cases. Several possibilities can arise
for different cases, like at zero bias a Poisson alone is sufficient. For MOSFET,
as the device is a unipolar type, only one carrier needs to be solved for its
I-V characteristics, though in bipolar and MOSFET breakdown simulations,
both carriers are needed. For small geometry devices where the electric field
changes rapidly, carrier energy balance may be added to see hot-carrier
effect. Solving the lattice heat equation is essential when the device heating
effect is important.
The equation that needs to be solved is specified on the SYMBOLIC or
SYMB statement.
402 Technology Computer Aided Design: Simulation for VLSI MOSFET

8.38  Nonlinear System Solutions and Current-Voltage Analysis

For nonlinear system, the solutions are performed by two widely used itera-
tion methods. The methods are de-coupled solutions (Gummel’s method)
and coupled solutions (Newton’s method). Newton’s method with Gaussian
elimination of the Jacobian is by far the most stable method of solution. For
low current solutions, Gummel’s method offers an attractive alternative to
inverting the full Jacobian.
Either approach involves solving several large linear systems of equations.
The total number of equations in each system is on the order of one to four
times the number of grid points, depending on the number of device equa-
tions being solved for.
Several ideas are common to all methods of solving the equations. They
are convergence rate, error norms, convergence criteria, error norms selec-
tion, linear solution options, and initial guess.
The nonlinear iteration converges usually at a linear rate or at a quadratic rate.
At a linear rate, the error decreases by about the same factor at each iteration.
The convergence is rapid in the quadratic method, as the error is approxi-
mately squared at each iteration. Hence Gummel’s method, which is linear in
most cases, is less accurate than Newton’s method, which is quadratic.
Medici uses six types of initial guesses named initial, previous, local, proj-
ect, p.local, and post-regrid initial.
For tracing the I-V curves, bias step and number of steps are specified on
the SOLVE statement by VSTEP and NSTEP for a corresponding electrode.

SYMB GUMMEL CARR=1 ELECTRON

METHOD ICCG DAMPED itlimit=40 stack=10 cont.stk
SOLVE initial V(Source)=0.0 V(Gate)=0.0 V(Drain)=0.005
SYMB NEWTON CARR=1 ELECTRON
METHOD AUTONR N.DAMP N.DVLIM=0.5

SOLVE PREVIOUS V(Source)=0.0 V(Gate)=2 V(Drain)=0.0

LOG OUT.FILE=BVNBLlog
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=0.2 NSTEP=50

8.39  Post-Processing and Parameter Extraction

After the fabrication of the device, fabricated and simulated device results
are necessary, which is possible by the post-processing of the data by the
following commands:

Print: The command print will print specific quantities at points within
a defined area.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 403

Plot.1D: Plot.1D will plot specific quantity along a line segment through
the device.
Plot.2D: Plot.2D command will plot characteristics, boundaries, junc-
tions, and depletion edges.
Contour: It will plot the contours of a physical quantity on a 2D area.
E.line: It will plot potential gradient paths and calculate the ioniza-
tion integrals.
Label: This command will plot character strings, symbols, and lines as
part of a 1D or 2D plot.

PLOT.1D X.AXIS=V(Drain) Y.AXIS=I(Drain)

+  TITLE=“Ids vs. Vgs” COLOR=2 POINTS OUTFILE=Id_Vd.DAT
LABEL LABEL=“Vds=2 V” COLOR=2

EXTRACT MOS.PARA DRAIN=Drain GATE=Gate IN.FILE=BVNBLlog

I.Drain=9e-10

8.40  Drain Current versus Drain Voltage Simulation

The complete Medici simulation program, explained step by step, is given
below. By executing this program in Medici, drain current has been plotted
with respect to drain voltage, shown in Figure 8.24. The gate voltage is fixed
at 5 V. From the graph it is evident that initially current is increasing with
the increase of drain voltage. Then the current reaches the saturation value,
and then it increases slowly with the drain voltage due to channel length
modulation.

COMMENT MEDICI Input File

MESH IN.FILE=LDNBL.str TSUPREM4 ELEC.BOT POLY.ELEC Y.MAX=10

RENAME ELECTR OLDNAME=1 NEWNAME=Source

RENAME ELECTR OLDNAME=2 NEWNAME=Gate
RENAME ELECTR OLDNAME=3 NEWNAME=Drain
SAVE MESH OUT.FILE=BVNBL
PLOT.2D GRID FILL TITLE=“Structure from TSUPREM-4”
PLOT.1D DOPING LOG X.START=0 X.END=0 Y.START=0 Y.END=2
+ POINTS BOT=1E14 TOP=1E21 TITLE=“S/D Profile”
PLOT.1D DOPING LOG X.START=1.8 X.END=1.8 Y.START=0 Y.END=2
+ POINTS BOT=1E14 TOP=1E19 TITLE=“Channel Profile”
PLOT.2D BOUND FILL L.ELEC=-1 TITLE=“Impurity Contours”
404 Technology Computer Aided Design: Simulation for VLSI MOSFET

1.50
Vgs = 5.0 Volts
I(Drain) (Amps/µm) *10t–4

1.00

0.50

0.00
0.0 2.0 4.0 6.0 8.0 10.0
V(Drain) (Volts)

FIGURE 8.24
Id versus Vds at gate voltage = 5V, device length is 5 μm.

CONTOUR DOPING LOG MIN=14 MAX=20 DEL=1 COLOR=2

CONTOUR DOPING LOG MIN=-20 MAX=-14 DEL=1 COLOR=1 LINE=2

models lsmmob fldmob auger bgn btbt fermi incomplete

energy.l high.dop

SYMB GUMMEL CARR=1 ELECTRON

METHOD ICCG DAMPED itlimit=40 stack=10 cont.stk
SOLVE initial V(Source)=0.0 V(Gate)=0.0005 V(Drain)=0.0

SYMB NEWTON CARR=1 ELECTRON

METHOD AUTONR N.DAMP N.DVLIM=0.5
SOLVE PREVIOUS V(Source)=0.0 V(Gate)=5.0 V(Drain)=0.0
LOG OUT.FILE=BVNBLlog
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=0.1 NSTEP=100

PLOT.1D X.AXIS=V(Gate) Y.AXIS=I(Drain) Y.LOGARITH

PLOT.1D X.AXIS=V(Drain) Y.AXIS=I(Drain)
+ TITLE=“Ids vs. Vds” COLOR=2 POINTS OUTFILE=Id_Vd_vg_5V.DAT
LABEL LABEL=“Vgs=5.0 Volts” COLOR=2
EXTRACT MOS.PARA DRAIN=Drain GATE=Gate IN.FILE=BVNBLlog
I.Drain=9e-10
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 405

8.41  Drain Current versus Gate Voltage Simulation

In the Medici program, drain current versus drain voltage simulation has
been performed. The drain voltage is fixed at 0.1 V. Drain current in logarithm
scale versus gate voltage and drain current in versus gate voltage has been
plotted in Figures 8.25 and 8.26, respectively. Threshold voltage is extracted
from this curve, which is equal to 0.65 V. On resistance (ron) can be calculated
from these data. Different ron can be achieved for different gate voltage. It
can be seen that on resistance is decreasing with Vgs increase, as higher Vgs
increase I and ron = Vds/I, so automatically ron will decrease at higher Vgs, as
Vds is fixed at 0.1 V. At the time of on resistance (ron) calculations, Vds should
be fixed at 0.1 V.

COMMENT MEDICI Input File

MESH IN.FILE=LDNBL.str TSUPREM4 ELEC.BOT POLY.ELEC Y.MAX=10
RENAME ELECTR OLDNAME=1 NEWNAME=Source
RENAME ELECTR OLDNAME=2 NEWNAME=Gate
RENAME ELECTR OLDNAME=3 NEWNAME=Drain

SAVE MESH OUT.FILE=BVNBL

PLOT.2D GRID FILL TITLE=“Structure from TSUPREM-4”
PLOT.1D DOPING LOG X.START=0 X.END=0 Y.START=0 Y.END=2

–5 Vds = 0.1 Volts

–6
–7
Log(I(Drain) (Amps/um))

–8
–9
–10
–11
–12
–13
–14
–15

0.00 1.00 2.00 3.00 4.00 5.00

V(Gate) (Volts)

FIGURE 8.25
log (Id) versus Vgs at drain voltage = 0.1 V, device length is 5 μm.
406 Technology Computer Aided Design: Simulation for VLSI MOSFET

Vds = 0.1 Volts

6.00
I(Drain) (Amps/um) *10t–6

4.00

2.00

0.00
0.00 1.00 2.00 3.00 4.00 5.00
V(Gate) (Volts)

FIGURE 8.26
Id versus Vgs at drain voltage = 0.1 V, device length is 5 μm.

+ POINTS BOT=1E14 TOP=1E21 TITLE=“S/D Profile”

PLOT.1D DOPING LOG X.START=1.8 X.END=1.8 Y.START=0 Y.END=2
+ POINTS BOT=1E14 TOP=1E19 TITLE=“Channel Profile”
PLOT.2D BOUND FILL L.ELEC=-1 TITLE=“Impurity Contours”
CONTOUR DOPING LOG MIN=14 MAX=20 DEL=1 COLOR=2
CONTOUR DOPING LOG MIN=-20 MAX=-14 DEL=1 COLOR=1 LINE=2

models lsmmob fldmob auger bgn btbt fermi incomplete energy.l

high.dop

SYMB GUMMEL CARR=1 ELECTRON

METHOD ICCG DAMPED itlimit=40 stack=10 cont.stk

SOLVE initial V(Source)=0.0 V(Drain)=0.0005 V(Gate)=0.0

SYMB NEWTON CARR=1 ELECTRON

METHOD AUTONR N.DAMP N.DVLIM=0.5

SOLVE PREVIOUS V(Source)=0.0 V(Drain)=0.1 V(Gate)=0.0

LOG OUT.FILE=BVNBLlog

SOLVE V(Gate)=0.0 ELEC=Gate VSTEP=0.1 NSTEP=50

COMMENT Plot results

Process Simulation of a MOSFET Using TSUPREM-4 and Medici 407

PLOT.1D X.AXIS=V(Gate) Y.AXIS=I(Drain) Y.LOGARITH

+   TITLE=“Ids vs. Vgs” COLOR=2 POINTS OUTFILE=Id_Vg_vd_pt1V.DAT
LABEL LABEL=“Vds=0.1 Volts” COLOR=2

PLOT.1D X.AXIS=V(Gate) Y.AXIS=I(Drain)

+   TITLE=“Ids vs. Vgs” COLOR=2 POINTS OUTFILE=Id_Vg_vd_pt1V.DAT
LABEL LABEL=“Vds=0.1 Volts” COLOR=2

EXTRACT MOS.PARA DRAIN=Drain GATE=Gate IN.FILE=BVNBLlog

I.Drain=9e-10

8.42 Conclusion
Device fabrication technology is a complex process that involves develop-
ing process-dependent patterns at each step using different masks. For
this it is required to define the mask lengths that require accurate calcu-
lations of junction depths and pattern areas that vary with process steps.
For scaled devices, the temperature, time, and ion implantation dose needs
to be predefined by accurate estimation to obtain desired specification with
minimum variation. Complete fabrication procedure needs many oxidation
steps and annealing steps for eliminating the lattice defects arising because
of ion bombardment at a different stage of fabrication, which tends to induce
device parameter and specification variation. Usually, a thin layer of protec-
tive oxide, also known as padding oxide, is grown on the wafer surface for
protection before the ion implantation steps. While fabricating a device, all of
the process dependent variations need to be accounted for with extreme care,
or acquired results will deviate from the desired results. Thus a simulation
of the entire fabrication process helps us optimize the mask lengths, temper-
ature, implantation dose, etc., before proceeding toward the actual process,
thereby helping reduce production cost and time.
The threshold voltage of the device presented here is 0.65 V, which can be fur-
ther modified by varying the gate oxide thickness and under-the-gate substrate
doping. Higher meshing densities in appropriate regions are considered for
more accurate simulation results. Meshing is chosen in such a way that meshing
density is higher near the surface of the wafer, as most of the phenomena occur
near the surface and boundary regions. The operation of the device fabricated
by TSUPREM-4 can be analyzed in a TCAD Medici device simulator by incor-
porating a different physical model and appropriate biasing conditions in the
simulator program of the device. Medici simulations are very fast, widely used,
and well accepted in industry. Before commencing analysis of a device, the
TCAD Medici simulator must be calibrated with standard experimental data.
408 Technology Computer Aided Design: Simulation for VLSI MOSFET

References
1. Taurus TSUPREM-4 User Guide, Version D-2010.03, March 2010.
2. Taurus Medici User Guide, Version F-2011.09, September 2011.
3. Gary S. May and Simon M. Sze, Fundamentals of Semiconductor Fabrication, Wiley,
New York.
4. Samar Saha, MOSFET test structures for two-dimensional device simulation,
Solid-State Electronics, 38(1), 69–73 (1995).
5. E.H. Nicollian and J.R. Brews, MOS Physics and Technology, Wiley, New York, 1982.
6. J.D. Meindl et al., Silicon epitaxy and oxidation, in F. Van de Wiele, W.L. Engl,
and P.O. Jesper, Eds., Process and Device Modeling Integrated Circuits Design,
Noorhoff, Leyden, 1977.
7. B.E. Deal, Standardization terminology for oxide charge associated with ther-
mally oxidized silicon, IEEE Trans. Electron Devices, ED-27, 606 (1980).
8. S.K. Gandhi, VLSI Fabrication Principles, Wiley, New York, 1983.
9. Kalyan Koley, Binit Syamal, Atanu Kundu, N. Mohankumar, and C.K. Sarkar,
Subthreshold analog/RF performance of underlap DG FETs with symmetric
and asymmetric source/drain extensions, Microelectronics Reliability, 52(11),
2572–2578 (2012).
10. Atanu Kundu, Binit Syamal, Kalyan Koley, N. Mohankumar, and C.K. Sarkar,
RF parameter extraction of bulk FinFET: A non quasi static approach, IEEE
International Conference on Electron Devices and Solid-State Circuits (EDSSC’10) in
Hong Kong, China, December 15–17 (2010).
11. C.W. Pearce, Crystal growth and wafer preparation and epitaxy, in S.M. Sze,
Ed., VLSI Technology, McGraw-Hill, New York, 1983.
12. W.F. Beadle, J.C.C. Tsai, and R.D. Plumber, Eds., Quick Reference Manual for
Engineers, Wiley, New York, 1985.
13. Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis
and Design, 3rd ed., McGraw-Hill, New York, 2003.
14. J.C. Bean, The growth of noble silicon material, Physics Today, 39(10), 36 (1986).
15. T. Yamamoto et al., An advanced 2.5 nm oxidized nitride gate dielectric for highly
reliable 0.25 µm MOSFETs, Symp. VLSI Technol. Dig. Tech. Pap., p. 45 (1997).
16. H.N. Yu et al., 1 µm MOSFET VLSI technology. Part I—An overview, IEEE Trans.
Electron Devices, ED-26, 318 (1979).
17. D. Pramanik and A.N. Saxena, VLSI metallization using aluminum and its alloy,
Solid State Tech., 26(1), 127 (1983); 26(3), 131 (1983).
18. K.A. Pickar, Ion implantation in silicon, in R. Wolfe, Ed., Applied Solid State
Science, vol. 5, Academic Press, New York, 1975.
19. W.G. Oldham, The fabrication of microelectronic circuit, in Microelectronics,
237(3), pp. 111–114. Freeman, San Francisco, 1977.
20. Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New
York, 2002.
21. M.C. King, Principles of optical lithography, in N.G. Einspruch, Ed., VLSI
Electronics, Vol. 1, pp. 73–81, Academic, New York, 1981.
Process Simulation of a MOSFET Using TSUPREM-4 and Medici 409

22. J.H. Bruning, A tutorial on optical lithography, in D.A. Doane, et al., Eds.,
Semiconductor Technology, p. 119, Electrochemical Society, Penningstone, 1982.
23. W.L. Brown, T. Venkatesan, and A. Wagner, Ion beam lithography, Solid State
Technol., 24, 8, 60 (1981).
24. J.P. Joly, Metallic contamination of silicon wafers, Microelectron. Eng., 40, 285 (1998).
25. J.C. Irvin, Evaluation of diffused layers in silicon, Bell Syst. Tech. J., 41, 2 (1962).
COLOR FIGURE 4.13
Tecplot_sv showing electrostatic potential across the device at VGS = 2.0 V, VDS = 2.0 V.

COLOR FIGURE 4.14

Tecplot_sv showing conduction band energy (eV) across the device at VGS = 2.0 V, VDS = 2.0 V.
 –0.05
Polysilicon gate Spacer

0 Gate oxide

SDE

0.05
Y[um]

DSD
Depletion Contour
Doping Concentration [cm–3]
1.0E+22
0.1
4.8E+18
2.3E+15
8.6E+11
0.15 –4.8E+14
p-sub –1.0E+18

–0.1 –0.05 0 0.05 0.1 0.15 0.2

X[um]

COLOR FIGURE 6.3

Bulk MOSFET structure created using TCAD.

0
Y[um]

0.05

0.1

–0.1 –0.05 0 0.05 0.1

X[um]

COLOR FIGURE 6.4

A zoomed-in view of the active region of the meshed structure.
 0
Y[um]

0.5 Electrostatic Potential [V]

1.6E+00
1.2E+00
7.8E–01
3.7E–01
–3.6E–02
1 –4.5E–01

–1 –0.5 0 0.5 1
X[um]
(a)

–0.05

0
Y[um]

0.05 Electrostatic Potential [V]

1.6E+00
1.2E+00
7.8E–01

0.1 3.7E–01
–3.6E–02
–4.5E–02

–0.1 –0.05 0 0.05 0.1

X[um]
(b)
COLOR FIGURE 6.6
Electrostatic potential contours in (a) long channel Leff = 1 µm and (b) short channel Leff = 65 nm
(Vgs = 1.0V , Vds = 0.05V ).
 0.05

Polysilicon gate
Depth (um)

0 Gate oxide (SiO2)

STI oxide
Electrostatic Potential [V]
5.3E–01
–0.05 Depletion Width Contour 3.4E–01
1.4E–01
–5.5E–02
–2.5E–01
p-sub –4.5E–01
–0.1
–0.0.5 0 0.05 0.1 0.15
Width (um)

COLOR FIGURE 6.17

Cross-section along the width of a trench-isolated MOSFET.

Front gate

Front oxide
0
Y[um]

0.02 Source Drain

0.04
Back oxide
Back gate

–0.04 –0.02 0 0.02 0.04

X[um]

COLOR FIGURE 6.26

A typical DG-MOSFET structure as simulated in TCAD.
 –2.50
Distance (microns)

2.50

7.50

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

COLOR FIGURE 8.2

Deposition of negative photoresist of thickness 1 μm on grown oxide; a portion (2 to 3 μm) of the
photoresist is being etched out by using mask NBL.

0.00
Distance (microns)

2.00

4.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

COLOR FIGURE 8.3

Implantation of antimony of pearson tilt = 7, dose = 1.0 e15, and energy = 100, which will be
used as NBL.
 0.00
Distance (microns)

4.00

8.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

COLOR FIGURE 8.4

Placement of antimony dopant in the wafer after the application of drive-in voltage on it.

–15.00
Distance (microns)

–5.00

5.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

COLOR FIGURE 8.5

Placement of NBL and epitaxial growth on the initial wafer.
 –13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.6

Pad oxide on the wafer is shown; here the y-axis has been chosen up to −12 μm.

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.7

Structure of the wafer after formation of the gate oxide.
 –14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.8

Polysilicon material deposition on the grown gate oxide material.

–14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.9

Polysilicon gate formation on the gate oxide after selective polysilicon material by etching from
the wafer; polysilicon gate length is 2.5 μm.
 –14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.10

Device structure after source and drain formation.

–15.00
Distance (microns)

–14.00

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.11

Formation of the p region in the wafer of length 0.1 to 0.7 μm.
 –14.00

–13.50
Distance (microns)

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.12

The structure achieved by executions of etch photoresist and etch nitride all statements.

–15.00
Distance (microns)

–13.00

–11.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

COLOR FIGURE 8.13

Borophosphosilicate glass deposition before the first layer of metal contact to the device.
 –15.00
Distance (microns)

–13.00

–11.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

COLOR FIGURE 8.14

Structure of the device after application of annealing step for BPSG.

–14.00
Distance (microns)

–12.00

–10.00

–8.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.15

Polishing of the device top surface by removal of excess oxide.
 –14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.16

Selective etching has been performed to deposit aluminum through it for the first layer of
metal contacts.

–14.50

–14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.17

First layer of metal deposition through the opening of BPSG for the direct contacts from the device.
 –15.00
Distance (microns)

–14.00

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.18

Deposition of IMD after formation of the first layer of metal contacts.

–14.50

–14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.19

Structure achieved by smoothening the top surface by the polishing operation again.
 –14.50

–14.00
Distance (microns)

–13.50

–13.00

–12.50

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.20

Opening region has been created by etching through which the second layer of metal will be
deposited.

–15.00

–14.00
Distance (microns)

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.21

Second layer of metal is being deposited and connected to the first layer of the metal through
the openings.
 –15.00

–14.00
Distance (microns)

–13.00

–12.00
0.00 1.00 2.00 3.00 4.00 5.00
Distance (microns)

COLOR FIGURE 8.22

Final device structure, y coordinate is taken up to –12.0 µm.

–15.00
Distance (microns)

–5.00

5.00

0.00 1.00 2.00 3.00 4.00 5.00

Distance (microns)

COLOR FIGURE 8.23

Final simulated structure of the 5 µm MOSFET.
ElEctrical EnginEEring

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