MUFFAKHAM JAH

COLLEGE OF ENGINEERING AND TECHNOLOGY

EC-432 ELECTRONIC DESIGN AUTOMATION LAB

(With effect from the academic year 2011-2012)

STUDENT’S MANUAL

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
EDA LAB MANUAL ECE Department

Vision and Mission of the Institution

Vision
To be part of universal human quest for development and progress by contributing high calibre,
ethical and socially responsible engineers who meet the global challenge of building modern
society in harmony with nature.

Mission
• To attain excellence in imparting technical education from the undergraduate through
doctorate levels by adopting coherent and judiciously coordinated curricular and co-curricular
programs
• To foster partnership with industry and government agencies through collaborative research
and consultancy
• To nurture and strengthen auxiliary soft skills for overall development and improved
employability in a multi-cultural work space
• To develop scientific temper and spirit of enquiry in order to harness the latent innovative
talents
• To develop constructive attitude in students towards the task of nation building and empower
them to become future leaders
• To nourish the entrepreneurial instincts of the students and hone their business acumen.
• To involve the students and the faculty in solving local community problems through
economical and sustainable solutions.
Vision and Mission of ECE Department
Vision
To be recognized as a premier education center providing state of art education and facilitating
research and innovation in the field of Electronics and Communication.

Mission
We are dedicated to providing high quality, holistic education in Electronics and Communication
Engineering that prepares the students for successful pursuit of higher education and challenging
careers in research, R& D and Academics.

Program Educational Objectives of B. E (ECE) Program:

1. Graduates will demonstrate technical competence in their chosen fields of employment by

identifying, formulating, analyzing and providing engineering solutions using current
techniques and tools
2. Graduates will communicate effectively as individuals or team members and demonstrate
leadership skills to be successful in the local and global cross-cultural working environment
3. Graduates will demonstrate lifelong learning through continuing education and professional
development
4. Graduates will be successful in providing viable and sustainable solutions within societal,
professional, environmental and ethical contexts

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EDA LAB MANUAL ECE Department

MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY

BANJARA HILLS, ROAD NO-3, TELANGANA

LABORATORY MANUAL

FOR

ELECTRONIC DESIGN AUTOMATION LAB

Prepared by: Checked by:

Approved by:

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EDA LAB MANUAL ECE Department

MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATIONS ENGINEERING

(Name of the Subject/Lab Course): Electronic Design Automation

Code: EC432 Programme: UG

Branch: ECE Version No: 1

Year : IV Updated on: 20/3/16

Semester :I No. of Pages:

Classification Status(Unrestricted/restricted): Unrestricted

Distribution List :Department, Lab, Library, Lab Incharge

Prepared by: 1) Name : 1) Name :

2) Sign : 2) Sign :

3)Designation : 3) Designation :

4) Date : 4) Date :

Verified by: 1) Name : * For Q.C Only

2) Sign : 1) Name :

3)Designation : 2) Sign :

4) Date : 3) Designation :

4) Date :

Approved by: (HOD) 1) Name:

2) Sign :

3) Date :

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EDA LAB MANUAL ECE Department

EC 432

ELECTRONIC DESIGN AUTOMATION LAB

Instructions 3 Periods per week
Duration of University Examination 3 Hours
University Examination 50 Marks
Sessionals 25 Marks
Objectives:

Part A
Write the Code using VERILOG, Simulate and synthesize the following

1. Arithmetic Units: Adders and Subtractors.

2. Multiplexers and Demultiplexers.
3. Encoders, Decoders, Priority Encoder and Comparator.
4. 8-bit parallel adder using 4-bit tasks and functions.
5. Arithmetic and Logic Unit with minimum of eight instructions.
6. Flip-Flops.
7. Registers/Counters.
8. Sequence Detector using Mealy and Moore type state machines.

Note:-
1. All the codes should be implemented appropriately using Gate level, Dataflow and
Behavioral Modeling.
2. All the programs should be simulated using test benches.
3. Minimum of two experiments to be implemented on FPGA/CPLD boards.

Part B

Transistor Level implementation of CMOS circuits

1. Basic Logic Gates: Inverter, NAND and NOR.

2. Half Adder and Full Adder.
3. 4:1 Multiplexer.
4. 2:4 Decoder.

Mini project:
i) 8 bit CPU
ii) Generation of different waveforms using DAC
iii) RTL code for Booth‟s algorithm for signed binary number multiplication
iv) Development of HDL code for MAC unit and realization of FIR Filter
v) Design of 4-bit thermometer to Binary Code Converter
.

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EDA LAB MANUAL ECE Department

MUFFAKHAM JAH
COLLEGE OF ENGINEERING & TECHNOLOGY
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

ELECTRONIC DESIGN AUTOMATION LAB

GENERAL INSTRUCTIONS AND SAFETY MEASURES

1. Sign in the log register as soon as you enter the lab.

2. Strictly observe lab timings.
3. Strictly follow the written and verbal instructions given by the teacher / Lab
Instructor
4. It is mandatory to come to lab in a formal dress and wear your ID cards.
5. Do not wear loose-fitting clothing or jewelry in the lab.
6. Mobile phones should be switched off in the lab.
7. Keep the labs clean at all times, no food and drinks allowed inside the lab.
8. Do not tamper with computer configurations
9. Playing games on the computers is strictly prohibited.
10.Use of Internet during laboratory timings is prohibited
11. Shut down the computer and switch off the monitor before leaving your table.
12.Handle the Trainer kits with care.
13.Don't plug any external devices / Pen drives without permission from lab staff.
14.Don't install any software without the permission of the lab Incharge.
15.Observation book and lab record should be carried to each lab.
16.Be sure of location of fire extinguishers and first aid kits in the laboratory.
17.Please take care of your personal belongings. Lab incharges /Staff are not
responsible for any loss of your belongings.

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List of Experiments Page

Gate Level Modeling

1. All Logic Gates
2. Arithmetic Units
2.1 Adder - Binary 1-Bit Half Adder
2.2 Subtractor - Binary 1-Bit Half Subtractor
3. Multiplexers And Demultiplexer
3.1 Multiplexer 2-To-1
3.2 Demultiplexer 1-To-2

Data Flow Level Modeling

4. All Logic Gates
5. Arithmetic Units
5.1 Adder - Binary 1-Bit Half Adder
5.2 Subtractor - Binary 1-Bit Half Subtractor
6 Multiplexers And Demultiplexer
6.1 Multiplexer 2-To-1

6.2 Demultiplexer 1-To-2

Behavioral Modeling
7. Encoders, Decoders, Priority Encoder And Comparator

8. 8-Bit Parallel Adder Using 4-Bit Tasks And Functions

9. Arithmetic And Logic Unit With Minimum Of Eight Instructions

10.Flip-Flops

11.Registers/Counters

12.Sequence Detector Using Mealy And Moore Type State Machines

13. Appendix

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1. HDL CODE TO REALIZE ALL THE LOGIC GATES

AIM:
i) To verify truth table and waveforms of logic gates using gate level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

TRUTH TABLE:

Vin1 Vin2 invert_ out and_ out or_ out nand_ out nor_ out exor_out exnor_out

0 0 1 0 0 1 1 0 1
0 1 0 0 1 1 0 1 0
1 0 1 0 1 1 0 1 0
1 1 0 1 1 0 0 0 1

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LOGICAL DIAGRAM:

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

PROGRAM: TESTBENCH

`resetall
`timescale 1 ns / 1 ns `timescale 1 ns / 1
ps module test;
module allgates(inverter_out, and_out, nand_out,
or_out, nor_out, exor_out, exnor_out, vin1, vin2); reg vin1, vin2;

input vin1, vin2; wire inverter_out_vin2, and_out, nand_out, or_out,

nor_out, exor_out, exnor_out;
output inverter_out, and_out, nand_out, or_out,
nor_out, exor_out, exnor_out; integer i;

not nverter1(inverter_out,vin2); allgates ag(inverter_out_vin2, and_out, nand_out,

and and1(and_out,vin1,vin2); or_out, nor_out, exor_out, exnor_out, vin1, vin2);

nand nand1(nand_out,vin1,vin2); initial

or or1(or_out,vin1,vin2); for(i=0;i<4;i=i+1

nor or1(nor_out,vin1,vin2); ) begin

xor or1(exor_out,vin1,vin2); {vin1,vin2}=i;

#5 ;
xnor xnor1(exnor_out,vin1,vin2);
endmodule end
endmodule

RESULT:

i) Truth tables and waveforms of logic gates are verified.

ii) Code is verified on FPGA board

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2. ARITHMETIC UNITS: ADDERS AND SUBTRACTORS

AIM:
i) To verify truth table and waveforms of arithmetic units: adder and subtractor
(binary 1-bit half adder/binary 1-bit half subtractor) using gate level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

TRUTH TABLE: BINARY 1-BIT HALF ADDER/BINARY 1-BIT HALF

SUBTRACTOR

A B SUM CO DIFF BARROW

0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0
1 1 0 1 0 0

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LOGIC DIAGRAM:
Circuit diagram:

Fig. 1 Binary 1-bit half-adder Fig. 2 Binary 1-bit half-subtractor

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

PROGRAM: 1-bit binary half adder TESTBENCH: 1-bit binary half adder
module ha(a,b,sum,co); `timescale 1ns/1ps
module ha_test;
input a,b; reg a,b;

wire sum,co;
output sum,co; ha hadder(a,b,sum,co); /*INSTANTIATE THE

MODULE NAME(ha)
xor (sum,a,b);
THAT NEEDS BE TESTED WITH
INSTANTIATION NAME hadder*/
and (co,a,b);
initia
l
endmodule
begin

{a,b}=2‟b00; #5
{a,b}=2‟b01; #5
{a,b}=2‟b10; #5
{a,b}=2‟b11;

#5 $finish;
end
initial

$monitor($time, “a=%b, b=%b, sum=%b, co=%b” , a, b,

sum, co);
endmodule

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TESTBENCH: 1-bit binary half subtracor

PROGRAM: 1-bit binary half subtracor
`timescale 1ns/1ps
module hs(a,b,diff,barrow); module hs_test; reg
a,b;
input a,b;
wire diff,barrow;

output diff,barrow; xor hs hsub(a,b,diff,barrow); /*INSTANTIATE THE

MODULE NAME(hs)
(diff,a,b); not(abar,a);
THAT NEEDS BE TESTED WITH
INSTANTIATION NAME hsub*/
and (barrow,abar,b);
initial
endmodule begin
{a,b}=2‟b00;

#5 {a,b}=2‟b01;
#5 {a,b}=2‟b10;
#5 {a,b}=2‟b11;

#5 $finish;
end
initial

$monitor($time, “a=%b, b=%b, diff=%b,

barrow=%b” , a, b, diff, barrow);
endmodule

RESULT:

i) Truth tables and waveforms of

arithmetic units- binary 1-bit half adder and
half subtractor are verified.
ii) Code is verified on FPGA
board.

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3. MULTIPLEXERS AND DEMULTIPLEXERS

AIM:

i) To verify truth table and waveforms of 2x1 multiplexer and 1x2

demultiplexer using gate level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:

Operating System: Windows

Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different
combinations of input as per the truth table and verify simulation results
with expected output waveform.
3. Now synthesize the program and note down how many lookup tables
(LUTs) been consumed.
4. Also verify output on FPGA board.

TRUTH TABLE: MUX 2x1 and DEMUX

S A B
S Y
0 Y 0
0 A
1 0 Y
1 B

MUX 2x1 DEMUX 1x2

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LOGICAL DIAGRAM:

Components:

Fig.1 Multiplexer 2x1 Fig.2 Demultiplexer 1x2

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

TESTBENCH: (MUX 2x1)

PROGRAM: (MUX 2x1)
`timescale 1 ns / 1 ps
module mux_test;
`resetall
reg x,a,b;
`timescale 1 ns / 1 ns module mux2to1(x,a,b,y); input
wire y;
x,a,b;
(NOTE only primary inputs “a,b,x” and primary output “y”
output y;
have been declared with reg and wire respectively; but not
wire xbar,y1,y2; not (xbar,x); and (y1,a,xbar);
the intermediary(OR intermediatory) signals such as
and (y2,b,x); “xbar,y1,y2″)
or (y,y1,y2); endmodule mux2to1 mux(x,a,b,y); /*INSTANTIATE THE MODULE

NAME(mux2to1) THAT NEEDS BE TESTED WITH

INSTANTIATION NAME mux*/

initi
al
begi
n

a=0; b=0; x=0;

#5 a=1;
#5 x=1;

#5 b=1;x=1;
#5 $finish;
end
initial

$monitor($time, “a=%b, b=%b, x=%b” , a , b , x);

endmodule

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PROGRAM: (DeMux 1x2)

TESTBENCH: (DeMux 1x2)
`resetall
`timescale 1 ns / 1 ps module
`timescale 1 ns / 1 ns demux_test; reg x,y;

module demux1to2(x,a,b,y); wire a,b;

input x,y;
demux1to2 dm(x,a,b,y);
output a,b; not (xbar,x); initial
and (a,y,xbar);
begin
and (b,y,x);
y=0; x=0;
endmodule
#5 y=1; x=1;

#5 y=0; x=1;

#5 y=1; x=0;

#5 $finish;

end

initial

$monitor($time, “a=%b, b=%b, x=%b” , a , b , x);

endmodule

RESULTS:

i) Truth tables and waveforms of 2x1 multiplexer and 1x2 demultiplexer are
verified.
ii) Code is verified on FPGA board.

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Exercise:

Write Verilog Module and Testbench to simulate the following using gate level Modeling

1. 4 Input NAND Gate

2. 3 Input NOR Gate
3. 3 Input XOR Gate
4. 2 Input XOR using minimum number of 2 input NAND gates.
5. Realization of four variable function
 F= (A.B + C.D)‟ 

 F= (A.B‟ + C‟.D) 

 Or - and - Invert logic 

 F = (A + B C + C D) 



6. Full adder using basic gates
7. Full Subtractor using basic gates

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EDA LAB MANUAL ECE Department

DATA FLOW LEVEL MODELING

List Of Experiments

7 All Logic Gates

8 Arithmetic Units

8.1.1 Adder - Binary 1-Bit Half Adder

8.2 Subtractor - Binary 1-Bit Half Subtractor

9 Multiplexers And Demultiplexer

3.1 Multiplexer 2-To-1

3.2 Demultiplexer 1-To-2

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EDA LAB MANUAL ECE Department

1. HDL CODE TO REALIZE ALL THE LOGIC GATES

AIM:
i) To verify truth table and waveforms of logic gates using dataflow level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

TRUTH TABLE:

Vin1 Vin2 invert_ out and_ out or_ out nand_ out nor_ out exor_out exnor_out

0 0 1 0 0 1 1 0 1
0 1 0 0 1 1 0 1 0
1 0 1 0 1 1 0 1 0
1 1 0 1 1 0 0 0 1

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 EDA LAB MANUAL ECE Department

LOGICAL DIAGRAM:

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

PROGRAM: TESTBENCH:
`timescale 1 ns / 1 ps
`resetall
module test;
`timescale 1 ns / 1 ns
reg vin1, vin2;
module allgates(inverter_out, and_out, nand_out, or_out,
wire inverter_out_vin2, and_out, nand_out, or_out, nor_out,
nor_out, exor_out, exnor_out, vin1, vin2); input vin1, vin2; exor_out, exnor_out;
output inverter_out, and_out, nand_out, or_out, nor_out, integer i;
exor_out, exnor_out;
allgates ag(inverter_out_vin2, and_out, nand_out, or_out,
assign inverter_out=~vin2; assign nor_out, exor_out, exnor_out, vin1, vin2); initial
and_out=vin1&vin2; assign
for(i=0;i<4;i=i+1)
nand_out=~(vin1&vin2); assign
begin
or_out=vin1|vin2;
{vin1,vin2}=i; #5 ;
assign nor_out=~(vin1|vin2);
end
assign exor_out=(vin1^vin2;
endmodule
assign exnor_out=vin1~^vin2;
endmodule

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RESULT:
i) Truth tables and waveforms of logic gates are verified.
ii) Code is verified on FPGA board.

2. ARITHMETIC UNITS: ADDERS AND SUBTRACTORS

AIM:
i) To verify truth table and waveforms of arithmetic units: adder and
subtractor(binary 1-bit half adder/binary 1-bit half subtractor) using dataflow
level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

TRUTH TABLE: BINARY 1-BIT HALF ADDER/BINARY 1-BIT HALF

SUBTRACTOR
 EDA LAB MANUAL ECE Department

A B SUM CO DIFF BARROW

0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0
1 1 0 1 0 0
LOGIC DIAGRAM:

Fig. 1 Binary 1-bit half-adder Fig. 2 Binary 1-bit half-subtractor

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

PROGRAM: 1-bit binary half adder TESTBENCH: 1-bit binary half adder
module ha(a,b,sum,co); `timescale 1ns/1ps
module ha_test;
input a,b;
reg a,b;
output sum,co;
wire sum,co;
assign sum=a^b; ha hadder(a,b,sum,co); /*INSTANTIATE THE

MODULE NAME(ha) THAT NEEDS BE TESTED

assign co=a&b; WITH INSTANTIATION NAME hadder*/

endmodule initial
begin
{a,b}=2‟b00; #5
{a,b}=2‟b01; #5
{a,b}=2‟b10; #5
{a,b}=2‟b11;
#5 $finish;

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EDA LAB MANUAL ECE
Department

e
$monitor($time, “a=%b, b=%b,
n
sum=%b, co=%b” , a, b, sum, co);
d
endmodule
initial

PROGRAM: 1-bit binary half subtracor

module hs(a,b,diff,barrow);
RESULTS
input a,b;

output diff,barrow;

assign diff=a^b; assign

abar=~a;

assign barrow=abar&b;

endmodule

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#5
TESTBENCH: 1-bit binary half subtracor {a,b}=2‟b01;
#5
`timescale {a,b}=2‟b10;
1ns/1ps module #5
hs_test; reg a,b; {a,b}=2‟b11;
wire diff,barrow;
#5
hs hsub(a,b,diff,barrow); /*INSTANTIATE THE
$finish;
MODULE NAME(hs) THAT NEEDS BE TESTED end
WITH INSTANTIATION NAME hsub*/
initial
initi
$monitor($time, “a=%b, b=%b,
al
diff=%b, barrow=%b” , a, b, diff,
begi
n barrow); endmodule

{a,b}=2‟b00;
i) Truth tables and waveforms of arithmetic units- binary 1-bit half adder and half
subtractor are verified.
ii) Code is verified on FPGA board.

3. MULTIPLEXERS AND DEMULTIPLEXERS

AIM:

i) To verify truth table and waveforms of 2x1 multiplexer and 1x2 demultiplexer
using dataflow level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:

Operating System: Windows

Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device : XC3S500E-4FG320

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PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

TRUTH TABLE:

S A B
S Y
0 Y 0
0 A
1 0 Y
1 B

MUX 2x1 DEMUX 1x2

LOGICAL DIAGRAM:

Fig.1 Multiplexer 2x1 Fig.2 Demultiplexer 1x2

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

`timescale 1 ns / 1 ns module mux2to1(x,a,b,y); input

PROGRAM: (MUX 2x1)
x,a,b;
`resetall output y;

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wire xbar,y1,y2;
TESTBENCH: (MUX 2x1)
assign xbar=~x;

assign y1=a&xbar;
`timescale 1 ns / 1 ps
assign y2=b&x;
module mux_test;
assign y=y1|y2; reg x,a,b;
wire y;
(NOTE only primary inputs “a,b,x” and primary output
endmodule
“y” have been declared with reg and wire respectively;
but not the intermediary(OR intermediatory) signals
such
as “xbar,y1,y2″)
mux2to1 mux(x,a,b,y); /*INSTANTIATE
THE
MODULE NAME(mux2to1) THAT NEEDS BE
TESTED WITH INSTANTIATION NAME mux*/
initial
begin
a=0; b=0; x=0;
#5 a=1;
#5 x=1;
#5 b=1;x=1;
#5 $finish;
end
initial
$monitor($time, “a=%b, b=%b, x=%b” , a , b
, x);
endmodule

MUX 2X1 USING CONDITIONAL OR TERNARY OPERATOR:

mux2to1(x,a,b,y); input x,a,b;

output y;
PROGRAM: (MUX 2x1)
assign y=x? b: a;
`resetall
endmodule
`timescale 1 ns / 1 ns module

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TESTBENCH: (MUX 2x1)

`timescale 1 ns / 1 ps

module
mux_test; reg
x,a,b;
wire y;
(NOTE only primary inputs “a,b,x” and
primary output “y” have been declared with
reg and wire respectively; but not the
intermediary(OR intermediatory) signals
such as “xbar,y1,y2″)
mux2to1 mux(x,a,b,y); /*INSTANTIATE
THE
MODULE NAME(mux2to1) THAT NEEDS BE TESTED WITH
INSTANTIATION NAME mux*/
Initial

Begin
a=0;b=0;
x=0; #5 a=1;
#5 x=1;
#5 b=1;x=1;
#5 $finish;
End
initial
$monitor($time, “a=%b, b=%b, x=%b” , a ,b
,x);
endmodule

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PROGRAM: (DeMux 1x2) TESTBENCH: (DeMux 1x2)
`resetall

`timescale 1 ns / 1 ns module `timescale 1 ns / 1 ps

demux1to2(x,a,b,y); input x,y; module demux_test; reg

x,y;
output a,b; assign

xbar=~x; wire a,b;

assign a=y&xbar; demux1to2 dm(x,a,b,y);

assign b=y&x; initial

endmodule begin

y=0;

x=0;

#5 y=1;

x=1; #5

y=0; x=1;

#5 y=1;

x=0; #5

$finish; end

initial

$monitor($time, “a=%b, b=%b, x=%b” , a , b ,

x); endmodule

Results:

i) Truth tables and waveforms of 2x1 multiplexe and 1x2 demultiplexer are
verified.
ii) Code is verified on FPGA board.
EDA LAB MANUAL ECE Department

Exercise:

Write Verilog Module and Testbench to simulate the following using

Dataflow Modeling

1. 1 bit binary Full Adder

2. 1 bit Comparator
3. 4:1 Multiplexer
4. 1:8 Demux
5. 4:2 Encoder
6. 2:4 Decoder
7. 4:1 Multiplexer Using Conditional or ternary Operator
8. One Bit Comparator Using Conditional or ternary and Relational
Operators
9. Half Adder Using Conditional or ternary Operator
10. 2:4 Decoder Using Conditional or ternary Operator

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BEHAVIORAL MODELING

LIST OF EXPERIMENTS

12. Encoders, Decoders, Priority Encoder and Comparator

13. 8-bit parallel adder using 4-bit tasks and functions

14. Arithmetic and Logic Unit with minimum of eight instructions

15. Flip-Flops

16. Registers/Counters

17. Sequence Detector using Mealy and Moore type state machines

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1. HDL CODE TO REALIZE ENCODERS, DECODERS, PRIORITY

ENCODER AND COMPARATOR
AIM:
i) To verify truth table and waveforms of Encoders, Decoders, Priority
Encoder and Comparator using behavioural level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:
1. Write the program and testbench.
2. Simulate the testbench and observe the waveform for different
combinations of input as per the truth table and verify simulation results
with expected output waveform.
3. Now synthesize the program and note down how many lookup
tables(LUTs) been consumed.
4. Also verify output on FPGA board.

TRUTH TABLE/ BLOCK DIAGRAM:

A. ENCODER 4x2 A. BLOCK DIAGRAM
Y0
inputs outputs I0
I3 I2 I1 I0 Y1 Y0 I1
Y1
0 0 0 1 0 0 I2 4-to-2
encoder
0 0 1 0 0 1 I3

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0 1 0 0 1 0
1 0 0 0 1 1

Y0
B. DECODER 2x4 B. I0
BLOCK DIAGRAM Y1
2-to-4
I1 decoder Y2

Y3

inputs outputs
I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

C. PRIORITY ENCODER 4x2 C. BLOCK DIAGRAM

inputs outputs
I0 Y0
I3 I2 I1 I0 Y1 Y0 Status
0 0 0 0 0 0 0 I1
Priority Y1
I2 Encoder
0 0 0 1 0 0 1
4x2
0 0 1 x 0 1 1 I3 Status

0 1 x x 1 0 1
1 x x x 1 1 1

D. COMPARATOR

Binary inputs A Binary inputs B

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A3 A2 A1 A0 B3 B2 B1 B0 A<B

4-bit Magnitude A=B

Comparator
A>B

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

1. ENCODER 4x2

PROGRAM: TESTBENCH:
module encoder4to2(i0,i1,i2,i3,y1,y0); `timescale 1ns/1ps
input i0,i1,i2,i3; module enco_test;
output reg y1,y0; reg i0,i1,i2,i3;
always@* wire y1,y0;
case({i3,i2,i1,i0}) integer I;
4‟b0001:{y1,y0}=2‟b00; encoder4to2 encoder(i0,i1,i2,i3,y1,y0);
4‟b0010:{y1,y0}=2‟b01; /*INSTANTIATE THE MODULE NAME (encoder4to2) THAT
NEEDS BETESTED WITH INSTANTIATION NAME
4‟b0100:{y1,y0}=2‟b10; encoder*/

4‟b1000:{y1,y0}=2‟b11; initial
default:{y1,y0}=2‟bxx; begin
endcase { i0,i1,i2,i3}=0;
endmodule for(i=1; i<16; i=i+1)
#5 {i3,i2,i1,i0}=I;
#150
$finish;
end
initial
$monitor($time, “i0=%b, i1=%b,
i2=%b, i3=%b, y1=%b, y0=%b”,
i0,i1,i2,i3,y1,y0);
endmodule

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2. DECODER 2x4

PROGRAM: TESTBENCH:

module deco2to4(i0,i1,,y0,y1,y2,y3); `timescale 1ns/1ps

input i0,i1; module test_decoder;

output reg y0,y1,y2,y3; reg i0,i1;

always@(*) wire y0,y1,y2,y3;

casex({i0,i1}) deco2to4 deco(i0,i1,y0,y1,y2,y3);

3‟b00:{y0,y1,y2,y3}=4‟b1000; /*INSTANTIATE THE MODULE NAME(deco2to4) THAT

NEEDS BE TESTED WITH INSTANTIATION NAME deco*/

3‟b01:{y0,y1,y2,y3}=4‟b0100;
initial
3‟b10:{y0,y1,y2,y3}=4‟b0010;
begin
3‟b11:{y0,y1,y2,y3}=4‟b0001;
{i0,i1}=0;
endcase
for(i=1;i<3;i=i+1);
endmodule
#5 {i1,i0}=i;

end

initial

#150 $finish;

initial

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$monitor($finish,

“i0=%b,i1=%b,y0=%b,y1=%b,y2=%b,y3=

%b”, i0,i1,y0,y1,y2,y3);

endmodule

3. PRIORITY ENCODER 4x2

PROGRAM:

TESTBENCH:
module pe(i3,i2,i1,i0,y1,y0,status);
input i3,i2,i1,i0;

output y1,y0,status;
always@*
casex({i3,i2,i1,i0}) // note it is casex not case
4‟b0000:{y1,y0,status}=3‟b000;
4‟b0001:{y1,y0,status}=3‟b001 ;
4‟b001x:{y1,y0,status}=3‟b011;
4‟b01xx:{y1,y0,status}=3‟b101;

4‟b1xxx:{y1,y0,status}=3‟b111;
`timescale 1ns/1ps
endcase
module test_priority;
endmodule
reg i3,i2,i1,i0;

wire y1,y0,status;
integer i;
pe encoder(i3,i2,i1,i0,y1,y0,status);
/*INSTANTIATE THE MODULE NAME(pe) THAT NEEDS
BE TESTED WITH INSTANTIATION NAME encoder*/

initial
begin

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{i3,i2,i1,i0}=4‟b000 endmodule

0; for(i=1;i<16;
i=i+1) #5
{i3,i2,i1,i0}=i; #150
$finish;

end
initial

$monitor($time,”i3=%b, i2=%b, i1=%b,

i0=%b, y1=%b, y0=%b, status=%b” , 4. COMPARATOR (4-BIT BINARY)
i3,i2,i1,i0,y1,y0,status);

PROGRAM: TESTBENCH:

TESTBENCH:
module comp(a,b,agtb,altb,aeqb);
input [2:0]a,b;
`timescale 1ns/1ps
output reg agtb, altb, aeqb; module test_comparator;
always@* reg [2:0]a,b;
begin wire agtb, altb, aeqb;
if(a>b) comp com1(a,b,agtb,altb,aeqb);
{agtb,altb,aeqb}=3‟b100; initial
else if(a<b) begin
{agtb,altb,aeqb}=3‟b010; {a,b}=0;
else #5 {a,b}=1;
{agtb,altb,aeqb}=3‟b001; #5 {a,b}=2;
end #5 {a,b}=3;
endmodule #10 $finish;
End
Initial
$monitor($time, “a=%b, b=%b, agtb=%b,
altb=%b, aeqb=%b” , a,b,agtb,altb,aeqb);
endmodule

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RESULT:

i) Truth tables and waveforms of Encoders, Decoders, Priority Encoder and

Comparator are verified.
ii) Code is verified on FPGA board.

2. HDL CODE TO REALIZE 8-BIT PARALLEL ADDER USING 4-BIT

TASKS AND FUNCTIONS

AIM:
i) To verify truth table and waveforms of 8-bit parallel adder using 4-bit tasks and
functions using behavioural level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

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BLOCK DIAGRAM:

B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
SUM
8-BIT PARALLEL ADDER
CO

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

1. 8-BIT PARALLEL ADDER USING 4-BIT TASK

PROGRAM: TESTBENCH:

endmodule
module adder8bit_task4bit(a,b,sum,co);
input [7:0]a,b;
output reg [7:0]sum;
output reg co;
reg cint;
task task4bit;
input [3:0]a_task, b_task;
input cin_task;
output [3:0]sum_task;
output co_task;
{co_task,sum_task}=a_task + b_task +
cin_task; `timescale 1ns/1ps
module test_adder8bit;
endtask
reg [7:0]a,b;
always@(
wire [7:0]sum;
*) begin
wire co;
task4bit(a[3:0], b[3:0], 0, sum[3:0], cint);
adder8bit_task4bit add_task(a,b,sum,co);
task4bit(a[7:4], b[7:4], cint, sum[7:4], co); /*INSTANTIATE THE MODULE NAME(adder8bit_task4bit)
end THAT NEEDS BE TESTED WITH INSTANTIATION NAME

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add_task*/
$monitor($time, “a=%b, b=%b, sum=%b,
initial co=%b)” , a, b, sum, co);
begin endmodule
repeat(10)
begin

#5 a=$random; b=$random;
end
end
initial

#150
$finish;
initial
2.8-BIT PARALLEL ADDER USING 4-BIT FUNCTION

PROGRAM: TESTBENCH:
module `timescale 1ns/1ps
adder8bit_function4bit(a,b,sum,co); module test_adder8bit;
input [7:0]a,b;
output reg [7:0]sum; reg [7:0]a,b;
output reg co; wire [7:0]sum;
reg cint;
function [4:0]function4bit; wire co;
input [3:0]a_function, b_function; adder8bit_function4bit
input cin_function; add_function(a,b,sum,co);
function4bit=a_function + b_function + /*INSTANTIATE THE MODULE
NAME(adder8bit_function4bit) THAT NEEDS BE TESTED
cin_function; WITH INSTANTIATION NAME add_function*/

endfunction initial
always@(*) begin
begin repeat(10)
{cint,sum[3:0]}= begin
function4bit(a[3:0],b[3:0],0); #5 a=$random; b=$random;

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{co,sum[7:4]}= end
function4bit(a[7:4],b[7:4],cint); end
end initial
endmodule #150 $finish;
initial
$monitor($time, “a=%b, b=%b, sum=%b,
co=%b)” , a, b, sum, co);
endmodule

RESULT:
i) Truth tables and waveforms of 8-bit parallel adder using 4-bit tasks and
functions are verified.
ii) Code is verified on FPGA board.

3. HDL CODE TO REALIZE ARITHMETIC AND LOGIC UNIT

WITH MINIMUM OF EIGHT INSTRUCTIONS
AIM:
i) To verify truth table and waveforms of Arithmetic and Logic Unit with minimum
of eight instructions using behavioural level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.

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EDA LAB MANUAL ECE Department

3. Now synthesize the program and note down how many lookup tables(LUTs) been
consumed.
4. Also verify output on FPGA board.
TRUTH TABLE:

Opcode Operation
0 AND
1 OR
2 NAND
3 NOR
4 ADDITION
5 SUBTRACTION
6 MULTIPLICATION
7 XOR

BLOCK DIAGRAM:

OPERAND1 OPERAND2

OPCODE 4-BIT ALU

RESULT

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

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PROGRAM:

module alu4bit(op1, op2, opcode,

result); input [3:0]op1,op2;
input
[2:0]opcode;
output reg
[3:0]result;
always@(*)
case(opcode)
0: result=op1 & op2; // AND
1: result=op1 | op2; //OR
2: result= ~(op1 & op2); //NAND
3: result= ~(op1 | op2); //NOR
4: result=op1 + op2; //ADDITION
5: result=op1 - op2; //SUBTRACTION
6: result=op1 * op2; //MULTIPLICATION
7: result=op1 ^ op2; //XOR
endc
ase
end
mod
ule

TESTBENCH: Left Blank Intentionally

RESULT:

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EDA LAB MANUAL ECE Department

i) Truth tables and waveforms of Arithmetic and Logic Unit with minimum of eight
instructions are verified.
ii) Code is verified on FPGA board.

4. HDL Code to realize Flip-Flops

AIM:
i) To verify truth table and waveforms of Flip-Flops(JK,T and D) using behavioural
level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

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EDA LAB MANUAL ECE Department

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

BLOCK DIAGRAM: TRUTH TABLE:

lk rst J K Q Qbar
0 x x 0 1
1 0 0 Previous
state
1 0 1 0 1
1 1 0 1 0
1 1 1 Toggle

BLOCK DIAGRAM: TRUTH TABLE:

rst Clk Tin Q Q bar

1 0 Q
1 1 Q
0 x 0 1

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 EDA LAB MANUAL ECE Department

BLOCK DIAGRAM:
TRUTH TABLE:

Clk rst D Q Q bar

0 X 0 1

1 0 0 1

1 1 1 0

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

1. JK-FLIP FLOP
case({j,k})
2‟b00: begin q=q; qbar=~q; end 2‟b01: begin
PROGRAM: q=0; qbar=~q; end 2‟b10: begin q=1;
qbar=~q; end 2‟b11: begin q=~q; qbar=~q;
end endcase
module jkff(j,k,clk,rst,q,qbar); end endmodule
input j,k,clk,rst; output
reg q,qbar;
always@(posedge clk)
begin
if(~rst)
begin
q=0;
qbar=~q;
end
else

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TESTBENCH: 3; end
initial // inputs rst, clk
begin
`timesca rst=1;
le
clk=0; #5
1ns/1ps
rst=0; #5
module
rst=1;
jkff_test
end
; reg
always
j,k,clk,rs
t; wire #5 clk=~clk;
q,qbar; initial
jkff jk1(j,k,clk,rst,q,qbar); $monitor($time, “j=%b, k=%b, clk=%b,
/*INSTANTIATE THE MODULE NAME(jkff) rst=%b, q=%b, qbar=%b “, j,k,clk,rst,q,qbar);
THAT NEEDS BE TESTED WITH
INSTANTIATION NAME jk1*/ initial
initial // #90 $finish;
inputs endmodule
j,k begin
{j,k}=0;
{j,k}=1;
{j,k}=2;
{
j
,
k
}
=

2. T-FLIP FLOP

PROGRAM:

module tff(t,clk,rst,q,qbar); input t,clk,rst;

output reg q,qbar; always@(posedge
clk) begin
if(~rst) begin q=0;
qbar=~q; end

else case(t)
0: begin q=q; qbar=~q; end
1: begin q=~q; qbar=~q; end endcase

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EDA LAB MANUAL ECE Department

end endmodule initial // input t

begin
t=0; #15 t=1;
#20 t=0; #10
t=1; #5 t=0;
end initial
begin
clk=0; rst=1; #5 rst=0; #5 rst=1
end
always
#5
clk=~clk;
initial

$monitor($time, “t=%b, clk=%b, rst=%b,

q=%b, qbar=%b”, t, clk,rst, q, qbar); initial

#200
$finish;
endmodule

TESTBENCH:
3. D-FLIP FLOP

`timescale
1ns/1ps module PROGRAM:
tff_test; reg
t,clk,rst;
module dff(d,clk,rst,q,qbar); input d,clk,rst;
wire q,qbar;
output reg q,qbar; always@(posedge
tff tff1(t,clk,rst,q,qbar);
clk) begin
/*INSTANTIATE THE MODULE NAME(tff) THAT NEEDS
BE TESTED WITH INSTANTIATION NAME tff1*/ if(~rst) begin q=0;

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qbar=~q; end test_dff; reg

else case(d) d,clk,rst; wire

0: begin q=0; qbar=~q; end q,qbar;

dff dff1(d,clk,rst,q,qbar);
1: begin q=1; qbar=~q; end endcase
/*INSTANTIATE THE MODULE NAME(dff) THAT NEEDS
end endmodule BE TESTED WITH INSTANTIATION NAME dff1*/

initial //inputs clk, rst

begin
rst=1; clk=0; #5 rst=0; #5 rst=1;
end
initial //input
D begin

d=0; #15 d=1; #20 d=0; #50 d=1; #30

d=0; end
always
#5
clk=~clk;
initial
$monitor($time, “d=%b, clk=%b, rst=%b,
q=%b, qbar=%b”, d, clk, rst, q, qbar); initial
RESULTS:
#200
i) T/T & W/F of flipflop are verified $finish;
ii) Code is verified on FPGA board. endmodule

TESTBENCH:
`timescale
1ns/1ps module

5. HDL Code to realize Registers/Counters

AIM:

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EDA LAB MANUAL ECE Department

i) To verify truth table and waveforms of Registers/Counters using behavioural

level model.
ii) Verification of code on FPGA board.

REQUIREMENTS:
Operating System: Windows
Software: Mentor Graphics: Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

BLOCK DIAGRAM:

clk
4-bit right
r_out rst shift
register
r_i

FUNCTIONAL TABLE:

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EDA LAB MANUAL ECE Department

clk rsr r_in r_out

1 1 X 0
1 0 1 0
1 0 0 0
1 0 1 0
1 0 0 1
1 0 1 0
1 0 1 1
1 0 1 0

BLOCK DIAGRAM:

clk
l_in
Rst
4-bit left
L_out shift

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FUNCTIONAL TABLE:

clk rsr l_in l_out

1 1 X 0
1 0 1 0
1 0 0 0
1 0 1 0
1 0 0 1
1 0 1 0
1 0 1 1
1 0 1 0
BLOCK DIAGRAM:

TRUTH TABLE:

Clk Rst Q3 Q2 Q1 Q0
1 1 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 0 0 0 0

WAVEFORMS: Expected Timing Diagrams (Left Blank Intentionally)

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1. 4-BIT RIGHT SHIFT REGISTER

PROGRAM:

module rsr(clk,rst,r_in,r_out); input

clk,rst,r_in; TESTBENCH:
output r_out; reg
[3:0]q;
always@(posedge clk) module test_rsr;
begin reg clk,rst,r_in;
if(rst) wire r_out;
q<=0; else rsr rsr1(clk,rst,l_in,l_out); /* instantiate rsr,
q<={r_in,q[3:1]}; end and the instantiation name is rsr1 */ initial
assign r_out=q[0]; begin
endmodule rst=0;
clk=0;
#5
rst=1;
#5
rst=0;
end
always
#5
clk=~clk;
initial
begin

#25
r_in=1;
#10
r_in=0;
#10
r_in=1;
#10
r_in=0;
end
initial
#900

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$finish;
endmodule

2. 4-BIT LEFT SHIFT REGISTER

PROGRAM:

module lsr(clk,rst,l_in,l_out); `timescale 1ns/1ps

input clk,rst,l_in; module test_lsr;
TESTBENCH:
output l_out; `timescale 1ns/1ps
reg clk,rst,l_in;
reg [3:0]q; wire
module l_out;
test_lsr;
always@(posedge clk) lsr lsr1(clk,rst,l_in,l_out);
reg clk,rst,l_in; wire l_out; /* instantiate
begin lsr lsr1(clk,rst,l_in,l_out); /* name
lsr, and the instantiation instantiate
is lsr1lsr,
*/
and the instantiation name is lsr1 */
if(rst) initial
q<=0; intial begin
else begin rst=0;
q<={q[2:0],l_in}; clk=0;
rst = 0; clk=0;
end #5 rst=1;
#5 rst=1; #5 rst=0;
assign l_out=q[3]; #5 rst=0;
endmodule End end

Always

#5 clk =~clk;

Initial begin

#25 l_in=1; #10 l_in=0;

#25 l_in=1; #10 l_in=0;

End

Initial

#900 $finish;

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endmodule

3. 4-BIT UNIVERSAL SHIFT REGISTER

PROGRAM:
module usr(clk,rst,mode,pl_data_out,pl_data_in,q,r_in,r_out,l_in,l_out);
input clk,rst,r_in,l_in;
input [3:0]pl_data_in;
input [1:0]mode;
output [3:0]pl_data_out;
output r_out, l_out;
always@(posedge clk)
begin
if(rst)
begin
pl_data_out=3‟b0000;
r_out=0;
l_out=0;
end
else
case(mode)
0:pl_data_out=pl_data_out; // hold state
1:pl_data_out={r_in,pl_data_out}; // shift right in
2:pl_data_out={pl_data_out,l_in}; // shift left in
3:pl_data_out=pl_data_in; // load new input
endcase
end

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assign r_out=pl_data_out[0]; // shift right out

assign l_out=pl_data_out[3]; // shift left out
endmodule

TESTBENCH: Left Blank Intentionally

4. 4-BIT UP COUNTER

PROGRAM: TESTBENCH:

module upcounter(clk,rst,q); `timescale 1ns/1ps

input clk,rst; module test_up;
output reg [3:0]q; reg clk,rst;
always@(posedge clk) wire [3:0]q;
if(rst) upcounter up1(clk,rst,q);
q<=0; /* instantiate upcounter with
instantiation
else name up1 */
q<=q+1; initial
endmodule begin
clk=0;
rst=0;
#5 rst=1;
#5 rst=0;
end
always
#5 clk=~clk;
endmodule

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5. UP/DOWN COUNTER

PROGRAM: TESTBENCH:

module up_down_counter(clk,rst,ud,q); `timescale 1ns/1ps

input clk,rst,ud; module updn_counter;
output reg [3:0]q; reg clk,rst,ud;
always@(posedge clk) wire [3:0]q;
if(rst) up_down_counter updn(clk,rst,ud,q);
q<=0; /* instantiate up_down_counter
with
else if(ud) instantiation name updn */
q<=q+1; initial
else begin
q<=q-1; clk=0;
endmodule rst=0;
#5 rst=1;
#5 rst=0;
end
always
#5 clk=~clk;
initial
begin
#15 ud=1;

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#300 ud=0;
#100 ud=1;
end
initial
#900 $finish;
endmodule

6. COUNTER WITH PARALLEL LOAD

PROGRAM:

module
pload_counter(clk,rst,pdata_in,pload,ud,q);
input clk,rst,pload,ud;

input [3:0]pdata_in;
output reg [3:0]q;
always@(posedge clk)
if(rst)
q<=0;
else
if(pload)
q<=pdat
a_in;
else
if(ud)
q<=q+1;
else q<=q-1;
endmodule

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TESTBENCH: Left Blank Intentionally

RESULT:

i) Truth tables and waveforms of Registers/Counters are verified.

ii) Code is verified on FPGA board.

6. HDL CODE TO REALIZE SEQUENCE DETECTOR USING MOORE

AND
MEALY TYPE STATE MACHINES

AIM:
i) To verify truth table and waveforms of sequence detector using moore and mealy
type state machines (sequence 101 non-over lapping).
ii) Verification of code on FPGA board.

REQUIREMENTS:

Operating System: Windows

Software: Mentor Graphics Modelsim, Precision RTL
Hardware: FPGA-Spartan 3E
Device: XC3S500E-4FG320

PROCEDURE:

1. Write the program and testbench.

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2. Simulate the testbench and observe the waveform for different combinations of input
as per the truth table and verify simulation results with expected output waveform.
3. Now synthesize the program and note down how many lookup tables (LUTs) been
consumed.
4. Also verify output on FPGA board.

BLOCK DIAGRAM: Moore Machine

INPUT
SEQUENTIAL
NEXT NEXT OUTPUT OUTPUT
STATE STATE (NS) LOGIC
LOGIC
LOGIC

CLOCK RESET
CURRENT
STATE (CS)

STATE DIAGRAM:

Sequence 101 non-over lapping pattern Moore type

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WAVEFORMS: expected timing diagrams left blank intentionally

PROGRAM:

`resetall
`timescale 1 ns / 1 ns
module moore101(clk,rst,in,out); input
clk,rst,in;
output out;
parameter s0=0,s1=1,s2=2,s3=3; reg [1:0]
cs,ns; always@(posedge clk)
begin if(rst) cs<=0;
else cs<=ns; end
always@* case(cs)
s0: if(in) ns=s1;
else ns=s0; s1:
if(in) ns=s1; else ns=s2;
s2: if(in) ns=s3;
else
ns=s0;
s3: if(in) ns=s1;
else
ns=s0;
endcase
assign out=(cs==s3)?1:0;
endmodule

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TESTBENCH:

`timescale 1 ns / 1 ps module test;

reg clk,rst,in; wire out;
moore101 m1(clk,rst,in,out); initial
begin clk=0;
rst=0;
#5 rst=1;
#5 rst=0; end
always #5 clk=~clk; initial
begin #15 in=1; #10
in=0; #10 in=1; #10
in=1; #10 in=1; #10
in=0; end

endmodule

BLOCK DIAGRAM: Mealy Machine

SEQUENTIAL
NEXT NEXT OUTPUT OUTPUT
STATE STATE (NS) LOGIC
LOGIC
LOGIC

INPUT

CLOCK RESET
CURRENT
STATE (CS)

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STATE DIAGRAM:
Sequence 101 non-over lapping pattern Mealy type

WAVEFORMS: expected timing diagrams left blank intentionally

PROGRAM: TESTBENCH:

`resetall `timescale 1 ns / 1 ps
`timescale 1 ns / 1 ns module test;
module mealy101(clk,rst,in,out); reg clk,rst,in;
input clk,rst,in; wire out;
output reg out; mealy101 m1(clk,rst,in,out);
parameter s0=0,s1=1,s2=2,s3=3; initial
reg [1:0] cs,ns; begin
always@(posedge clk) clk=0;
begin rst=0;
if(rst) cs<=0; #5 rst=1;
else cs<=ns; #5 rst=0;
end end
always@* always #5 clk=~clk;
case(cs) initial
s0: if(in) begin ns=s1; out=0; end begin
else begin ns=s0; out=0; end #15 in=1;
s1: if(in) begin ns=s1; out=0; end #10 in=0;

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else begin ns=s2; out=0; end #10 in=1;

s2: if(in) begin ns=s3; out=1; end #10 in=1;
else begin ns=s0; out=0; end #10 in=1;
s3: if(in) begin ns=s1; out=0; end #10 in=0;
else begin ns=s0; out=0; end end
endcase endmodule
endmodule

RESULT:

i) Truth tables and waveforms of sequence detector using moore and mealy type
state machines are verified.
ii) Code is verified on FPGA board.

Exercise:

Write Verilog Module and Testbench to simulate the following

using Behavioural Modeling

Write Verilog module for the following

1. 4 bit BCD adder

2. 8:1 MUX

3. 3:8 Decoder

4. 8: 3 Encoder
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5. 16 bit adder using 8 bit adder task and function

6. Half Adder and Full adder using CASE statement

7. Full Adder using if-else if – else

8. 101 over lapping pattern mealy and moore

9. 1011 over lapping and non over lapping pattern mealy and moore

Tanner Tools
IC Flow Diagram

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Experiments List

1. Design the Schematic of CMOS Inverter using S-edit (Tanner tools)

2. Design the Schematic of CMOS Buffer using S-edit (Tanner tools)
3. Design the Schematic of CMOS Ex-or using S-edit (Tanner tools)

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4. Design the Schematic of CMOS Halfadder using S-edit (Tanner tools)

Excersise

5. Design the Schematic of CMOS Universal Gates using S-edit (Tanner tools)
6. Design the Schematic of CMOS AND using S-edit (Tanner tools)
7. Design the Schematic of CMOS OR using S-edit (Tanner tools)
8. Design the Schematic of CMOS Ex Nor gates using S-edit (Tanner tools)
9. Design the Schematic of CMOS Fulladder using S-edit (Tanner tools)
10. Design the Schematic of CMOS Half Substractor using S-edit (Tanner tools)
11. Design the Schematic of CMOS Full Substractor using S-edit (Tanner tools)

1. Design of CMOS Inverter & Buffer

Aim:

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Design the Schematic of CMOS Inverter using S-edit (Tanner tools), generate
the netlist and veifty the output waveform.

Software requirements:
Operating System : Xp Windows

Software : S-edit,T-spice, W-edit (Tanner tools)

Procedure:

1. Create Library with your name or roll no in S-edit, include the all.lib
(library)in same directory.
2. Click on Cell tab, create a New cell name (Ex: Inverter design), inside the
library you will design name as inverter.
3. Design the schmatic design of in iverter in S-edit, give the DC Voltage
source, Pulse Voltage, Print voltage input node and output node.
4. Click on T-spice ( )which generate the circuit netlist, pop up t-spice editor,
where you can include the model file and Analysis.
5. Click on run button ( ) which simulation will done and open the waveform
editor (W-edit)

Invertor schematic:

Netlist Of Inverter

* SPICE export by: S-Edit 14.11

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* Export time: Wed Aug 05 14:44:58 2015

* Design: invert
* Cell: inverter
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude empty cells: yes
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\All\invert
* Exclude global pins: no
* Control property name: SPICE

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\Models\Generic_025.lib" tt

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 Out In Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out In N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_1 Gnd DC 5
VVoltageSource_2 In Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(In)
.PRINT TRAN V(Out)

********* Simulation Settings - Analysis section *********

.tran 1n 1000n
********* Simulation Settings - Additional SPICE commands *********

.end

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Invertor output Wave form:

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2. Design of CMOS Buffer Gates

Aim:
Design the Schematic of CMOS Buffer using S-edit (Tanner tools), generate
the netlist and veifty the output waveform.

Software requirements:
Operating System : Xp Windows

Software : S-edit,T-spice, W-edit (Tanner tools)

Procedure:

1. Existing libraries you can design different cells, need to change the cell name
only.
2. Click on Cell tab, create a New cell name (Ex: Buffer design), inside the
library you will design name as Buffer.
3. Design the schmatic design of in iverter in S-edit, give the DC Voltage
source, Pulse Voltage, Print voltage input node and output node.
4. Click on T-spice ( )which generate the circuit netlist, pop up t-spice editor,
where you can include the model file and Analysis.
5. Click on run button ( ) which simulation will done and open the waveform
editor (W-edit)

Buffer:

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Netlist

* SPICE export by: S-Edit 14.11

* Export time: Wed Aug 05 14:47:41 2015
* Design: invert
* Cell: inverter
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude empty cells: yes
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\All\invert
* Exclude global pins: no
* Control property name: SPICE

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\Models\Generic_025.lib" tt

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********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 N_2 In Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Out N_3 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_2 In N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out N_3 N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_1 Gnd DC 5
VVoltageSource_2 In Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(In)
.PRINT TRAN V(Out)

********* Simulation Settings - Analysis section *********

.tran 1n 1000n
********* Simulation Settings - Additional SPICE commands *********

.end

Output of buffer Wave form:

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3. Design of CMOS XOR Gates

Aim:
Design the Schematic of CMOS XOR Gate S-edit (Tanner tools), generate the
netlist and veifty the output waveform.

Software requirements:
Operating System : Xp Windows

Software : S-edit,T-spice, W-edit (Tanner tools)

Procedure:

1. Existing libraries you can design different cells, need to change the cell name
only.
2. Click on Cell tab, create a New cell name (Ex: Xor), inside the library you
will design name as Xor.
3. Design the schmatic design of in iverter in S-edit, give the DC Voltage
source, Pulse Voltage, Print voltage input node and output node.
4. Click on T-spice ( )which generate the circuit netlist, pop up t-spice editor,
where you can include the model file and Analysis.

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5. Click on run button ( ) which simulation will done and open the waveform
editor (W-edit)

Netlist * SPICE export by: S-Edit 14.11

* Export time: Wed Aug 05 11:38:02 2015
* Design: invert
* Cell: xor
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Wrap lines: no
* Root path: C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\All\invert
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\Models\Generic_025.lib" tt
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_3 N_10 a xnor 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_4 N_9 b Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_5 Gnd bbar N_10 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

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MNMOS_6 abar a Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_7 xorfinal xnor Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_1 bbar b Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 xnor abar N_9 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 bbar b N_2 N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 N_5 abar N_4 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_3 N_4 b N_5 N_6 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_4 xnor a N_5 N_7 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_5 N_5 bbar xnor N_8 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_6 abar a N_12 N_11 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_7 xorfinal xnor N_14 N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_3 N_12 Gnd DC 5
VVoltageSource_4 N_4 Gnd DC 5
VVoltageSource_6 N_14 Gnd DC 5
VVoltageSource_2 b Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_5 a Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(b)
.PRINT TRAN V(xnor)
.PRINT TRAN V(a)
.PRINT TRAN V(xorfinal)
********* Simulation Settings - Analysis section *********
.tran 1n 1000n
********* Simulation Settings - Additional SPICE commands *********
.end

Output of xor:

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Excersie:

Assignment:

1. Design the Schematic of CMOS NAND using S-edit (Tanner tools)

2. Design the Schematic of CMOS NOR using S-edit (Tanner tools)
3. Design the Schematic of CMOS Ex-NOR using S-edit (Tanner tools)
4. Design the Schematic of CMOS AND using S-edit (Tanner tools)
5. Design the Schematic of CMOS NOR using S-edit (Tanner tools)

4.Design of CMOS Half-Adder

Aim:

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Design the Schematic of CMOS Half Adder using S-edit (Tanner tools),
generate the netlist and veifty the output waveform.

Software requirements:

Operating System : Xp Windows

Software : S-edit,T-spice, W-edit (Tanner tools)

Procedure:

1. Existing libraries you can design different cells, need to change the cell name
only.
2. Click on Cell tab, create a New cell name (Ex: Halfadder design), inside the
library you will design name as Halfadder.
3. Design the schmatic design of in iverter in S-edit, give the DC Voltage
source, Pulse Voltage, Print voltage input node and output node.
4. Click on T-spice ( )which generate the circuit netlist, pop up t-spice editor,
where you can include the model file and Analysis.
5. Click on run button ( ) which simulation will done and open the waveform
editor (W-edit)

Half adder Schematic

Netlist oF Half adder

* SPICE export by: S-Edit 14.11

* Export time: Wed Aug 05 14:51:55 2015
* Design: invert

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* Cell: ha
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude empty cells: yes
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\All\invert
* Exclude global pins: no
* Control property name: SPICE
.lib "C:\Documents and Settings\Admin\My Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\Models\Generic_025.lib" tt
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_3 N_7 a xnor 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_4 N_8 b Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_5 Gnd bbar N_7 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_6 abar a Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_7 sum xnor Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_8 o a N_19 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_9 Gnd b N_19 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_10 carry o Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_1 bbar b Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 xnor abar N_8 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_10 carry o N_18 N_20 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 bbar b N_6 N_14 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 N_10 abar N_5 N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_3 N_5 b N_10 N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_4 xnor a N_10 N_11 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_5 N_10 bbar xnor N_9 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_6 abar a N_3 N_4 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_7 sum xnor N_1 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_8 o a N_16 N_15 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_9 N_16 b o N_17 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_6 Gnd DC 5
VVoltageSource_3 N_3 Gnd DC 5
VVoltageSource_4 N_5 Gnd DC 5
VVoltageSource_6 N_1 Gnd DC 5
VVoltageSource_7 N_16 Gnd DC 5

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VVoltageSource_8 N_18 Gnd DC 5

VVoltageSource_2 b Gnd PULSE(0 5 0 5n 5n 95n 200n)

VVoltageSource_5 a Gnd PULSE(0 5 0 5n 5n 95n 200n)

.PRINT TRAN V(b)

.PRINT TRAN V(xnor)
.PRINT TRAN V(a)
.PRINT TRAN V(sum)
.PRINT TRAN V(carry)
********* Simulation Settings - Analysis section *********
.tran 1n 1000n
********* Simulation Settings - Additional SPICE commands *********
.end

WaveForm

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Exercise:
1.Design the Schematic of CMOS Full Adder using S-edit (Tanner tools).
2. Design the Schematic of CMOS Full Substractor using S-edit (Tanner tools).
3. Design the Schematic of CMOS Half Substractor using S-edit (Tanner tools).
4. Design the Schematic of CMOS 4:1 Mux using S-edit (Tanner tools).
4. Design the Schematic of CMOS 2:4 Decoder using S-edit (Tanner tools).

APPENDIX

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LABORATORY COURSE ASSESSMENT GUIDELINES

i. The number of experiments in each laboratory course shall be as per the curriculum in the
scheme of instructions provided by OU. Mostly the number of experiments is 10 in each
laboratory course under semester scheme and 18 under year wise scheme.
ii. The students will maintain a separate note book for observations in each laboratory
course.
iii. In each session the students will conduct the allotted experiment and enter the data in the
observation table.
iv. The students will then complete the calculations and obtain the results. The course
coordinator will certify the result in the same session.
v. The students will submit the record in the next class. The evaluation will be continuous
and not cycle-wise or at semester end.
vi. The internal marks of 25 are awarded in the following manner:
a. Laboratory record - Maximum Marks 15
b. Test and Viva Voce - Maximum Marks 10
vii. Laboratory Record: Each experimental record is evaluated for a score of 50. The rubric
parameters are as follows:
a. Write up format - Maximum Score 15
b. Experimentation Observations & Calculations - Maximum Score 20
c. Results and Graphs - Maximum Score 10
d. Discussion of results - Maximum Score 5
While (a), (c) and (d) are assessed at the time of record submission, (b) is assessed during the
session based on the observations and calculations. Hence if a student is absent for an experiment
but completes it in another session and subsequently submits the record, it shall be evaluated for
a score of 30 and not 50.
viii. The experiment evaluation rubric is therefore as follows:

Parameter Max Score Outstanding Accomplished Developing Beginner Points

Observations
and 20
Calculations
Write up
format 15
Results and
graphs 10
Discussion of
Results 5

LABORATORY EXPERIMENT EVALUATION RUBRIC

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OUTSTANDING ACCOMPLISHED DEVELOPING BEGINNER

CATEGORY
(Up to 100%) (Up to 75%) (Up to 50%) (Up to 25%)
Write up Aim, Apparatus, The write up follows The report follows The write up
format material requirement, the specified format the specified format does not follow
theoretical basis, but a couple of the but a few of the the specified
procedure of specified parameters formats are missing format and the
experiment, sketch of are missing. and the experimental presentation is
the experimental sketch is not shabby.
setup etc. is included in the
demarcated and report
presented in clearly
labeled and neatly
organized sections.
Observations The experimental The experimental The experimental The experimental
and observations and observations and observations and observations and
Calculations calculations are calculations are calculations are results are
recorded in neatly recorded in neatly recorded neatly but recorded
prepared table with prepared table with correct units and carelessly.
correct units and correct units and significant figures Correct units
significant figures. significant figures are not used. Sample significant
One sample but sample calculation is also figures are not
calculation is calculation is not not shown followed and
explained by shown sample
substitution of values calculations not
shown
Results and Results obtained are Results obtained are Results obtained are Results obtained
Graphs correct within correct within correct within are not correct
reasonable limits. reasonable limits. reasonable limits. within reasonable
Graphs are drawn Graphs are drawn Graphs are not limits. Graphs
neatly with labeling neatly with labeling drawn neatly and or are not drawn
of the axes. Relevant of the axes. Relevant labeling is not neatly and or
calculations are calculations from the proper. No labeling is not
performed from the graphs are calculations are proper. No
graphs. Equations are incomplete and done from the calculations are
obtained by equations are not graphs and done from the
regression analysis or obtained by equations are not graphs and
curve fitting if regression analysis or obtained by equations are not
relevant curve fitting regression analysis obtained by
or curve fitting regression
analysis or curve
fitting
Discussion of All relevant points of Results are discussed Discussion of results Neither relevant
results the result are but no theoretical is incomplete and points of the
discussed and reference is divergent results are results are
justified in light of mentioned. Divergent not identified. discussed nor
theoretical results are identified divergent results
expectations. but no satisfactory identified
Reasons for divergent reasoning is given for
results are identified the same.
and corrective
measures discussed.

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ix. The first page of the record will contain the following title sheet:

SAMPLE ASSESSMENT SHEET

NAME: ROLL NO.

Date Observations Results and Discussion

Exp. Date Submitted Write up Total Score
&Calculations Graphs of Results
No. conducted (Max 15) (Max 50)
(Max 20) (Max 10) (Max 5)

10

11

12

x. The 15 marks of laboratory record will be scaled down from the TOTAL of the
assessment sheet.
xi. The test and viva voce will be scored for 10 marks as follows:
Internal Test - 6 marks
Viva Voce / Quiz - 4 marks

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xii. Each laboratory course shall have 5 course outcomes.

The proposed course outcomes are as follows:

On successful completion of the course, the student will acquire the ability to:

1. Conduct experiments, take measurements and analyze the data through hands-on
experience in order to demonstrate understanding of the theoretical concepts of
_______________________, while working in small groups.

2. Demonstrate writing skills through clear laboratory reports.

3. Employ graphics packages for drawing of graphs and use computational software for
statistical analysis of data.

4. Compare the experimental results with those introduced in lecture, draw relevant
conclusions and substantiate them satisfactorily.

5. Transfer group experience to individual performance of experiments and demonstrate

effective oral communication skills.

xiii. The Course coordinators would prepare the assessment matrix in accordance with the
guidelines provided above for the five course outcomes. The scores to be entered against
each of the course outcome would be the sum of the following as obtained from the
assessment sheet in the record:

a. Course Outcome 1: Sum of the scores under „Observations and Calculations‟.

b. Course Outcome 2: Sum of the scores under „Write up‟.
c. Course Outcome 3: Sum of the scores under „Results and Graphs‟.
d. Course Outcome 4: Sum of the scores under „Discussion of Results‟.
e. Course Outcome 5: Marks for „Internal Test and Viva voce‟.

xiv. Soft copy of the assessment matrix would be provided to the course coordinators.

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MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY

Program Outcomes of B.E (ECE) Program:
PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.

PO2: Problem analysis: Identify, formulate, research literature, and analyse complex engineering problems reaching
substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences

PO3: Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.

PO4: Conduct investigations of complex problems: Use research-based knowledge and research methods including
design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid
conclusions.

PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an understanding of the
limitations.

PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal, and cultural issues and the consequent responsibilities relevant to the professional engineering practice.

PO7: Environment and sustainability: Understand the impact of the professional engineering solutions in societal
and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.

PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.

PO9: Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams,
and in multidisciplinary settings.

PO10: Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.

PO11: Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one‟s own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.

PO 12: Life-long learning: Recognise the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

Program Specific Outcomes (PSOs) of ECE Department, MJCET

PSO1: The ECE Graduates will acquire state of art analysis and design skills in the areas of digital and analog VLSI
Design using modern CAD tools.

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PSO2: The ECE Graduates will develop preliminary skills and capabilities necessary for embedded system design
and demonstrate understanding of its societal impact.

PSO3: The ECE Graduates will obtain the knowledge of the working principles of modern communication systems
and be able to develop simulation models of components of a communication system.

PSO4: The ECE Graduates will develop soft skills, aptitude and programming skills to be employable in IT sector.

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