EEE378/3

Digital Electronic II

Week 1: Introduction
Digital Electronic II

Why this course?

 This course is an extension to EEE130/3. It is about digital

logic design.
 Both types of circuits (digital and analogue) are used in
practice, but digital circuits are much more prevalent than
analogue circuits. Why?
 Analogue data is more precise than digital data because
digital data (discrete) is an approximation of analogue data
(continuous).
 Digital systems are usually more accurate than analogue
systems because they are less vulnerable to noise.

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Syllabus
Week Topic
1 Introduction : hierarchical design, CAD software.
2 Logic simplification : entered-variable Karnaugh map, introduction
to hazard & glitches
3 Logic design using MSI components : multiplexor, decoder,
demultiplexor, tristate, parity.
4 Logic design using PLD : ROM, PLA, PAL, GAL, introduction to
FPGA & CPLD.
5 Arithmetic circuits I : half-adder, full adder, ripple-carry adder,
subtractor, CLA adder.
6 Arithmetic circuits II : ALU, combinational multiplier, design Trade-
offs
7 Sequential circuits : synchronous & asynchronous circuits,
introduction to state diagrams, latches & flip-flops, characteristic
equations, metastability
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Syllabus (cont’d)
Week Topic
8 Registers & Counters : registers file, shift registers, counters, state
diagrams, synthesis of synchronous counters
9 Finite State Machines (FSM) : State diagrams for FSM, Moore &
Mealy models, design of sequence detectors.
10 More FSM : multimode counters, state encoding.
11 Multi-Input Multi-Output FSM : Controller & Data Path concept,
design of vending machine, design of traffic light controller
12 FSM Implementation : implementation of using of MSI & PLD,
introduction to FSM optimization
13 Algorithmic State Machines (ASM) : ASM concepts, rearchitect
previous designs with ASM
14 Case Studies : FIFO, LIFO, combinational lock with keypad input,
sequential divider, or other circuits of equivalent complexity

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Lecturers and tutors

Lecturers and Tutors Room No. Email Ext.

Dr. Mohamad Adzhar Md Zawawi 3.33 [email protected] 6052

Mr. Ahmad Nazri Ali 2.38 [email protected] 6020

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Assessment and Mark Distribution

Option I Option II
Tests x 2 15% 10%
Assignments & Quizzes – Dr Mohamad Adzhar Md Zawawi 5% 10%

Project – Mr Ahmad Nazri Ali 20% 20%

Exam 60% 60%
Total 100% 100%

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Assignments & Quizzes

 Will be handled 100% by Dr Adzhar

 Will be given every week (tentative)
 Contribution: 5 marks of coursework

Mini Project

 Will be 100% handled by Mr Ahmad Nazri Ali

 Contribution: 20 marks of coursework

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Recommended Book(s)

 Donald D. Givone, "Digital Principles and Design",

McGraw-Hill, 2003.
 Milos Ercegovac, Tomas Lang, Jaime H, Moreno,
“Introduction Digital Ssystems”, Wiley,1999.
 Alan B. Marcovitz, “Introduction to Logic Design,” 2nd
edition, McGraw-Hill, 2005.
 Randy H. Katz & Gaetano Boriello, “Contemporary Logic
Design”, 2nd edition, Prentice-Hall, 2005.
 Get the original. Photocopy? Nahh.. You won’t read it.

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Digital Electronic II

Computer-Aided Design (CAD) skills

 We will use FPGA-based system - will be taught in lab

session.
 Familiarize yourself with this EDA.
 Simulation – VHDL
 Embedded into FPGA

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Major Topics To Be Discussed

 Fundamental digital design skills (Data types, Boolean

Algebra, Minimization techniques)
 Combinational circuits (Circuits without memory)
 Introduction to arithmetic circuitry
 Sequential circuits (Circuits with memory)
 Register Transfer Level, Algorithmic State Machine. Some
case studies

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Assumptions

 You’re all well versed in

 Data and number representation and operations
 Boolean Algebra
 Logic gates
 Simple minimization techniques (up to 4 variables Karnaugh maps)

 All these topics you have learned in EEE130/3

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Objectives

 To introduce students with the concept of hierarchical design

and CAD software
 To refresh students with Boolean expression, Boolean
Algebra, SOP and POS

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Hierarchical Design
System Level
System Specification
Design Flow
 Definition:Hierarchy, or
“divide and conquer” Functional Architecture
Behavioural Design
 Dividing a module into sub- Representation
modules and then repeating
Function Verification
this operation on the sub-
modules until the complexity
Logic Design
of the smaller parts becomes Logic (Gate
Level)
manageable.
Representation
Logic Verification

Implementation (Gate/
Transistor/ Layout Level)

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Top-down vs Bottom-up
 Top Down Design:
 Complex functions replaced by more primitive functions
 Bottom Up Implementation:
 Primitives composed to build more and more complex assemblies
 Rules of Composition and Correctness by Construction:
 Electrical Rules: how many components can be cascaded?
 Timing Rules: how does the system change in conjunction with periodic
triggering events?
 Top-down design flow provides an excellent design process control.
 In reality, there is no truly unidirectional approach.
 Both top-down and bottom-up approaches have to be combined. In system
level design, in order to fit the system into the allowable constraint (area,
speed, power consumption) some functions may have to be removed and
the design process must be repeated (may requires significant
modification).

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Level of Implementation

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Hierarchical Design

Top Down Design Bottom Up Implementation

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Computer-Aided Design

 Synthesis tools
 create a portion of the design from other portions
 map more abstract representation to more physical representation
 map a representation into a more optimized form of that representation

VHDL Behavioral Boolean Logic

Synthesis Equations Synthesis Schematics

Gate
Libraries

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Computer-Aided Design
 Simulation
 program which dynamically executes an abstract design description
 obtain verification of functional correctness and some timing information before
the design is physically constructed
 easier to probe and debug a simulation than an implemented design
 simulation cannot guarantee that a design will work
 only as good as the test cases attempted
 does not check electrical errors
 abstracts away some of the realities of a real system
 Logic Simulation
 design described in terms of logic gates
 values are 0, 1 (plus others to be introduced)
 good for truth table verification
 Timing Simulation
 waveform inputs and outputs
 model of gate delays
 are the waveform shapes what were expected?
 identification of performance bottlenecks
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Computer-Aided Design
 Rapid Implementation Technologies
 the function and interconnect of a component can be "personalized“
 alternative to discrete logic gates and wires
 reduces wiring complexity and parts count
 facilitates more rapid design changes and enhancements

 Programming with 1's and 0's

 component function configured through truth table
 interconnect among internal modules also configured in this way

 Programmable Logic Devices

 Relatively simple circuits – implement using GAL
 Complex to very complex circuits – implement using CPLD & FPGA

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Altera UP2 Development Board

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Development Process
Design Specification

Design Entry
Design Modification
Design Compilation

Functional Verification

Timing Verification

Device Programming

In-System Verification

Sytem Production

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Design Flow for Logic Circuits

Design concept
A

Partition
B

Design one block Design one block

C

Design interconnection between blocks

Functional simulation of complete system

No
Correct?
Yes D

Physical mapping

Timing simulation

No
Correct?
Yes

Implementation
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Concept of Regularity, Modularity and Locality

 Regularity
 means that the hierarchical decomposition of a large system must be
simple and similar as much as possible. It must exists at all levels of
abstraction:
 Eg: At the logic level, identical gate structures can be used, etc. If the
designer has a small library of well-defined and well-characterized
basic building blocks, a number of different functions can be
constructed by using this principle.

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Concept of Regularity, Modularity and Locality

 Modularity
 Hierarchical functional blocks must be well-defined – functionality and
interfaces.
 Each block can be designed independently (relatively from each other).
 All of the blocks can be combined with ease to form the large system.
 Enables the parallelization of the design process.

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Concept of Regularity, Modularity and Locality

 Locality
 The well-characterized definition of interfaces for each module in the
system stays at the local level.
 Thus, the internals of each module become unimportant to the exterior
modules.
 Connections are mostly between neighbouring modules, avoiding long-
distance connections as much as possible to avoid interconnect delay.
Time-critical operations should be performed locally.

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Where Are We Now?

This is only for review. Get a book!

Digital Electronic II

Logic Gates: Revisited

Name Graphical Algebraic Truth Table
Symbol Function

x y f
AND f = x.y
x 0 0 0
y f 0 1 0
1 0 0
1 1 1

OR f=x+y x y f
0 0 0
x
y f 0 1 1
1 0 1
1 1 1

INVERTER f = x’ x f
x f
0 1
1 0

BUFFER f=x x f
x f
0 0
1 1

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Logic Gates: Revisited

Name Graphical Algebraic Truth Table
Symbol Function

y
NAND f = (x.y)’ x f
x 0 0 1
y f 0 1 1
1 0 1
1 1 0

NOR f = (x + y)’ x y f
x 0 0 1
y f 0 1 0
1 0 0
1 1 0
y
EX-OR f = x’y + xy’ x f
x 0 0 0
y f 0 1 1
1 0 1
1 1 0

EX-NOR f = x’y’ + xy x y f
x 0 0 1
y f 0 1 0
1 0 0
1 1 1

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Boolean Expression
 Boolean expressions are a much better form for representing digital
circuits because it is much easier to manipulate and simplify.
 A Boolean expression is an expression formed with:
 binary variables
 the binary operators OR and AND
 the unary operator NOT
 parentheses
 an equal sign
 For example,
 F = x'y + z F is 1 when z = 1 OR when x = 0 AND y = 1.
 The precedence of operations is as follows:
 parentheses,
 NOT,
 AND
 OR.

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Boolean Algebra

 Definition: Theorems that are used at design time to manipulate and

simplify Boolean expressions for easier and less expensive
implementation.
 Any Boolean expression can be represented using only AND, OR, and
NOT operations.
 May need to use Boolean algebra to change the form of a Boolean
expression to better utilize the types of gates provided by the component
library being used.
 A Boolean variable, x, can have two values, typically 1 and 0 (on and off)

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Properties of Boolean Algebra

 Identity Elements  Distributive of ‘+ over •’ and

 X+0=X ‘• over +’
 X • 1=X (Dual of previous)
 A+(B•C) = (A+B) • (A+C)
 Commutative property
 A• (B+C) = (A•B)+(A•C)
 A+B=B+A
 A• B=B• A (Dual of previous)
 Existence of the complement
 Associative property  A+A’ = 1
 A + (B+C) = (A+B)+C  A•A’ = 0
 A• (B•C) = (A•B)•C

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Duality

 Every Boolean expression has a dual

 If the expression is valid, then the dual is valid
 To obtain the dual:
 Replace all + with · and all · with +
 A+(BC) = (A+B)(A+C)
 A(B+C) = AB+AC
Keep parenthesis order
 Replace ‘1’ with ‘0’ and vice versa
 Duality can be used to prove theorems and allow simple transformation of
Boolean functions
 Also makes it easy to find other forms of a theorem

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Variable Theorems
 Idempotency  Absorption
 A+A = A  A+AB = A
 A·A = A  A(A’+B) = AB
 AB+AB’ = A
 Null elements for + and ·
 (A+B)(A+B’) = A
operators
 AB+AB’C = AB+AC
 A+1 = 1
 (A+B)(A+B’+C) = (A+B)(A+C)
 A·0 = 0

 Involution  DeMorgan’s
 (A+B)’= A’·B’
 (A’)’ = A
 (A·B)’= A’+B’

 Consensus
 AB+A’C+BC=AB+A’C

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Some Definitions
 Literal - a variable or complement of the variable in terms
 Product term - single literal or product (·) of two or more literals,
 e.g.: ABC
 Sum term - single literal or sum (+) of two or more literals,
 e.g.: A+B+C
 minterm – normal product term of n literals that is 1 for exactly one set of input
values
– 2n unique n-variable minterms
– 4-variable minterm – A’B’C’D’, A’B’C’D …. ABDC (16 possible terms)
• maxterm – normal sum term of n literals , expression that is 0 for exactly one set
of input values
– 2n unique n-variable maxterms
– 4-variable maxterm – A+B+C+D, ….. A’+B’+C’+D’ (16 possible terms)

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Minterm – Maxterm relationship

Decimal ABC Minterm Maxterm

Number
 Mi = mi’ 0 000 A’B’C’=m0 A+B+C=M0
 Proof
1 001 A’B’C=m1 A+B+C’=M1
 At row 5,
m5 = AB’C 2 010 A’BC’=m2 A+B’+C=M2
m5’= (AB’C)’
3 011 A’BC=m3 A+B’+C’=M3
= A’ + B + C’
= M5 4 100 AB’C’=m4 A’+B+C=M4

5 101 AB’C=m5 A’+B+C’=M5

6 110 ABC’=m6 A’+B’+C=M6

7 111 ABC=m7 A’+B’+C’=M7

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Forms of Boolean Expression

Complement
 Use DeMorgan's theorem
 DeMorgan's theorem states:
 (X + Y)' = X' * Y'
 DeMorgan's theorem can be extended to 3 or more variables.
 Example
 Given (X + Y + Z)‘ Let A = Y + Z
 (X + A)' = (X' * A')
 Substituting back in Y + Z
 = (X' * (Y + Z)')
 = X' * Y' * Z'
 The compliment of a function can be obtained by interchanging AND's and
OR's and complementing each literal.
 Parenthesis may need to be included to keep the order of the evaluation.
 Remember, that in the absence of parenthesis, AND has precedence
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Canonical SOP and POS

 Canonical SOP Of A Function

 a function represented as a sum of minterms
 F(A,B,C) = A’BC’+ABC’+A’BC+ABC

 Canonical POS Of A Function

 a function represented as a product of maxterms
 F = (A+B’+C)(A+B’+C’)(A’+B+C’)

 Any function can be represented as a canonical POS or SOP

form, which is either an two-level AND-OR tree or a OR-AND
tree

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Example
 In SOP
Row xyz Minterm Maxterm F
 x’y’z+ x’yz’+ x’yz+ xyz
 Σm(1,2,3,7) 0 000 x’y’z’ x+y+z 0
 In POS 1 001 x’y’z x+y+z’ 1
 (x+y+z) (x’+y+z) (x’+y+z’) (x’+y’+z)
 ΠM(0,4,5,6)
2 010 x’yz’ x+y’+z 1

 For the same function F 3 011 x’yz x+y’+z’ 1

 Σm(1,2,3,7)= ΠM(0,4,5,6)
4 100 xy’z’ x’+y+z 0

5 101 xy’z x’+y+z’ 0

6 110 xyz’ x’+y’+z 0

7 111 xyz x’+y’+z’ 1

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Don’t Cares

 Very often, the specification of a function is incomplete

 Output state is unimportant for that particular set of inputs or
input state never occurs
 Any input combination whose state is unimportant is a “don’t
care” state (d in SOP and D in POS)
 Useful feature for minimization of states
 Example, with minterms AB’C (101) and ABC’(110) are don’t
cares
 Minterm – F(A,B,C) = Σm(0,1,2) + Σd(5,6)
 Maxterm – F(A,B,C) = ΠM(3,4,7) . ΠD(5,6)

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DIY Example
 Given the following SOP expression, minimize it:
 f(x,y,z) = x’y’z’ + x’y’z + xy’z’ + xy’z + xyz’

 Find the minimum Boolean expression for the following

functions:
 f(x,y,z)=ΠM(0,1,2,3)
 f(w,x,y,z)=wxy + w’x(yz + yz’) + x’(wz + y’z) + z(w’x’ + xy’)

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Credit to Prof. Dr. Norashidi for the presentation

slides.

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