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Lab # 03 I2C Write

The document discusses configuring I2C registers and interfacing a PIC microcontroller with an EEPROM chip. It provides details on I2C communication including the protocol, registers involved, and 24C01 EEPROM chip. Code is written to configure the required registers and write data to the EEPROM following the I2C timing diagram.

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SOBAN KHAN
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31 views

Lab # 03 I2C Write

The document discusses configuring I2C registers and interfacing a PIC microcontroller with an EEPROM chip. It provides details on I2C communication including the protocol, registers involved, and 24C01 EEPROM chip. Code is written to configure the required registers and write data to the EEPROM following the I2C timing diagram.

Uploaded by

SOBAN KHAN
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Embedded Systems Lab # 03 17-10-2019

I2C Communication
Objective:
 Configure the I2C registers and interface with EEPROM 24C01 with PIC 16F877A.
Components:
 Microcontroller PIC16F877A
 Pull Up Resistor (10 Kilohms)
 EEPROM 24C01C
 I2C Debugger
Theory:
I2C Communication:
I²C (Inter-Integrated Circuit), pronounced I-squared-C, is multi-master, multi-slave, packet
switched, single-ended, serial computer bus invented in 1982 by Philips.
The I2C (Inter-IC) bus is a bi-directional two-wire serial bus that provides a communication link
between integrated circuits (ICs).
I2C is a synchronous protocol that allows a master device to initiate communication with a slave
device. Data is exchanged one bit at a time. Most of the sensor are related to I2C.
The two wires, or lines are called Serial Clock (or SCL) and Serial Data (or SDA). The SCL line is
the clock signal which synchronize the data transfer between the devices on the I2C bus and it’s
generated by the master device. The other line is the SDA line which carries the data.
The two lines are “open-drain” which means that pull up resistors needs to be attached to them so
that the lines are high because the devices on the I2C bus are active low. Commonly used values for
the resistors are from 2K for higher speeds at about 400 kbps, to 10K for lower speed at about 100
kbps.
The I2C mode fully implements all master and slave functions (including general call support) and
provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function).
It supports 7-bit and 10-bit addressing. 127 devices connected on two wires.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
Master:
A device on the I2C bus which starts the communication.
Slave:
A device which is being addressed by MASTER.
Protocol:
The data signal is transferred in sequences of 8 bits. So, after a special start condition occurs comes
the first 8 bits sequence which indicates the address of the slave to which the data is being sent. The
device addressing sequence starts with the most significant bit (MSB) first and ends with the least

Khan Soban Bin Khalil(16-006) Page 1


Embedded Systems Lab # 03 17-10-2019

significant bit (LSB) and it’s actually composed of 7 bits because the 8th bit is used for indicating
whether the master will write to the slave (logic low) or read from it (logic high). After each 8 bits
sequence follows a bit called Acknowledge. After the first Acknowledge bit in most cases comes
another addressing sequence but this time for the internal registers of the slave device. After the
addressing sequences follows the data sequences as many until the data is completely sent and it
ends with a special stop condition.

I2C communication can only start if the bus is idle.


Register:
SSPCON, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation.
The SSPCON and SSPCON2 registers are readable and writable. The lower six bits of the SSPSTAT
are read-only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used
for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read
from. SSPADD register holds the slave device address when the SSP is configured in I2C Slave
mode. When the SSP is configured in Master mode, the lower seven bits of SSPADD act as the baud
rate generator reload value.

We configure these register for I2C communication as shown in code.


24C01C:
The Microchip Technology Inc. 24C01C is a 1K bit Serial Electrically Erasable PROM with a
voltage range of 4.5V to 5.5V. The device is organized as a single block of 128 x 8-bit memory with
a 2-wire serial interface. Low-current design permits operation with max. standby and active currents
of only 5uA and 1 mA, respectively. The device has a page write capability for up to 16 bytes of
data and has fast write cycle times of only 1 ms for both byte and page writes.

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Embedded Systems Lab # 03 17-10-2019

Code:

Khan Soban Bin Khalil(16-006) Page 3


Embedded Systems Lab # 03 17-10-2019

Output:

I2C Debug:

I2C Internal Memory:

Variables Status:

Conclusion:
In this lab, we studied about the I2C communication and interface with EEPROM 24C01C by using
PIC 16F877A. Configured the required registers and write code by understand the timing diagram
of I2C protocol. Also write data in EEPROM 24C01.

Khan Soban Bin Khalil(16-006) Page 4

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