IMAGE SENSOR SOLUTIONS

DEVICE
PERFORMANCE
SPECIFICATION

KODAK KAI-11000M
KODAK KAI-11000CM
Image Sensor
4008 (H) x 2672 (V)
Interline Transfer
Progressive Scan CCD

March 14, 2005

Revision 4.0

KAI-11000 Rev 4.0

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IMAGE SENSOR SOLUTIONS

TABLE OF CONTENTS

TABLE OF FIGURES ................................................................................................................................................4

DEVICE DESCRIPTION...........................................................................................................................................5

DEVICE DESCRIPTION...........................................................................................................................................6
ARCHITECTURE .........................................................................................................................................................6
OVERALL ...................................................................................................................................................................6
Pixel .....................................................................................................................................................................7
Vertical to Horizontal Transfer............................................................................................................................8
Horizontal Register to Floating Diffusion ...........................................................................................................9
Horizontal Register Split....................................................................................................................................10
Single Output Operation ....................................................................................................................................10
Dual Output Operation ......................................................................................................................................10
Output ................................................................................................................................................................11
PHYSICAL DESCRIPTION ..........................................................................................................................................12
Pin Description and Device Orientation............................................................................................................12
PERFORMANCE .....................................................................................................................................................13
POWER - ESTIMATED ...............................................................................................................................................13
FRAME RATES – CONTINUOUS MODE .....................................................................................................................13
IMAGING PERFORMANCE .........................................................................................................................................14
Image Performance Operational Conditions.....................................................................................................14
Imaging Performance Specifications .................................................................................................................14
Defect Definitions ..............................................................................................................................................17
Defect Map.........................................................................................................................................................17
Quantum Efficiency............................................................................................................................................18
Angular Quantum Efficiency..............................................................................................................................20
TEST DEFINITIONS ...............................................................................................................................................21
TEST REGIONS OF INTEREST ....................................................................................................................................21
OVERCLOCKING ......................................................................................................................................................21
Tests ...................................................................................................................................................................22
OPERATION.............................................................................................................................................................23
MAXIMUM RATINGS ................................................................................................................................................23
MAXIMUM VOLTAGE RATINGS BETWEEN PINS .......................................................................................................23
DC BIAS OPERATING CONDITIONS ..........................................................................................................................24
POWER UP SEQUENCE .............................................................................................................................................24
AC OPERATING CONDITIONS ..................................................................................................................................25
Clock Levels.......................................................................................................................................................25
Clock Line Capacitances ...................................................................................................................................25
TIMING REQUIREMENTS ..........................................................................................................................................26
MAIN TIMING – CONTINUOUS MODE ......................................................................................................................27
FRAME TIMING – CONTINUOUS MODE ....................................................................................................................28
Frame Timing without Binning ..........................................................................................................................28
Frame Timing for Vertical Binning by 2............................................................................................................28
Frame Timing Edge Alignment ..........................................................................................................................29
LINE TIMING – CONTINUOUS MODE ........................................................................................................................30
Line Timing Single Output .................................................................................................................................30
Line Timing Dual Output – Left Output.............................................................................................................30
Line Timing Dual Output – Right Output ..........................................................................................................31
Line Timing Vertical Binning by 2 .....................................................................................................................31

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Line Timing Detail .............................................................................................................................................32

Line Timing Binning by 2 Detail........................................................................................................................32
Line Timing Edge Alignment..............................................................................................................................33
PIXEL TIMING – CONTINUOUS MODE ......................................................................................................................34
Pixel Timing Detail ............................................................................................................................................34
FAST LINE DUMP TIMING ........................................................................................................................................35
ELECTRONIC SHUTTER ............................................................................................................................................36
Electronic Shutter Line Timing ..........................................................................................................................36
Electronic Shutter – Integration Time Definition ..............................................................................................36
Electronic Shutter Description...........................................................................................................................37
STORAGE AND HANDLING .................................................................................................................................38
STORAGE CONDITIONS ............................................................................................................................................38
ESD.........................................................................................................................................................................38
COVER GLASS CARE AND CLEANLINESS .................................................................................................................38
ENVIRONMENTAL EXPOSURE ..................................................................................................................................38
SOLDERING RECOMMENDATIONS ............................................................................................................................39
MECHANICAL DRAWINGS..................................................................................................................................40
PACKAGE.................................................................................................................................................................40
DIE TO PACKAGE ALIGNMENT .................................................................................................................................41
GLASS .....................................................................................................................................................................42
GLASS TRANSMISSION .............................................................................................................................................43
QUALITY ASSURANCE AND RELIABILITY ....................................................................................................44

ORDERING INFORMATION ................................................................................................................................45

AVAILABLE PART CONFIGURATIONS .......................................................................................................................45
REVISION CHANGES............................................................................................................................................46

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IMAGE SENSOR SOLUTIONS

TABLE OF FIGURES
Figure 1 - Sensor Architecture ..................................................................................................................................... 6
Figure 2 - Pixel Architecture......................................................................................................................................... 7
Figure 3 - Vertical to Horizontal Transfer Architecture ................................................................................................. 8
Figure 4 - Horizontal Register to Floating Diffusion Architecture.................................................................................. 9
Figure 5 - Horizontal Register .................................................................................................................................... 10
Figure 6 - Output Architecture.................................................................................................................................... 11
Figure 7 - Power ........................................................................................................................................................ 13
Figure 8 - Frame Rates .............................................................................................................................................. 13
Figure 9 - Color with Microlens Quantum Efficiency Using AR Glass ........................................................................ 18
Figure 10 - Color without Microlens Quantum Efficiency Using AR Glass ................................................................. 18
Figure 11 - Monochrome with Microlens Quantum Efficiency .................................................................................... 19
Figure 12 - Monochrome without Microlens Quantum Efficiency ............................................................................... 19
Figure 13 – Monochrome with Lenslets Angular Quantum Efficiency ........................................................................ 20
Figure 14 - Color with Lenslets Angular Quantum Efficiency ..................................................................................... 20
Figure 15 - Overclock Regions of Interest.................................................................................................................. 21
Figure 16 - Main Timing - Continuous Mode .............................................................................................................. 27
Figure 17 - Framing Timing without Binning............................................................................................................... 28
Figure 18 - Frame Timing for Vertical Binning by 2.................................................................................................... 28
Figure 19 - Frame Timing Edge Alignment ................................................................................................................ 29
Figure 20 - Line Timing Single Output ....................................................................................................................... 30
Figure 21 - Line Timing Dual Output – Left Output .................................................................................................... 30
Figure 22 – Line Timing Dual Output – Right Output ................................................................................................. 31
Figure 23 - Line Timing Vertical Binning by 2............................................................................................................. 31
Figure 24 - Line Timing Detail .................................................................................................................................... 32
Figure 25 - Line Timing by 2 Detail ............................................................................................................................ 32
Figure 26 - Line Timing Edge Alignment .................................................................................................................... 33
Figure 27 - Pixel Timing ............................................................................................................................................. 34
Figure 28 - Pixel Timing Detail ................................................................................................................................... 34
Figure 29 - Fast Line Dump Timing............................................................................................................................ 35
Figure 30 - Electronic Shutter Line Timing ................................................................................................................. 36
Figure 31 - Integration Time Definition....................................................................................................................... 36
Figure 32 - Package Drawing..................................................................................................................................... 40
Figure 33 - Die to Package Alignment ....................................................................................................................... 41
Figure 34 - Glass Drawing ......................................................................................................................................... 42
Figure 35 – AR Glass Transmission .......................................................................................................................... 43

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IMAGE SENSOR SOLUTIONS

SUMMARY SPECIFICATION

KODAK KAI-11000 Image Sensor

4008 (H) x 2672 (V) Interline
Transfer Progressive Scan CCD
Parameter Value
Interline CCD;
Architecture
Progressive Scan
4072 (H) x 2720 (V) =
Total Number of Pixels
approx. 11.1M
Number of Effective 4032 (H) x 2688 (V) =
Pixels approx. 10.8M
4008 (H) x 2672 (V) =
Number of Active Pixels
approx. 10.7M
Number of Outputs 1 or 2

Pixel Size 9.0µm (H) x 9.0µm (V)

Imager Size 43.3mm (diagonal)
37.25mm (H) x
Chip Size
25.70mm (V)
Aspect Ratio 3:2
Saturation Signal 60,000 electrons
Description
The Kodak KAI-11000 Image Sensor is a high- Quantum Efficiency
50%
performance, 11-million pixel sensor designed for (KAI-11000M)
professional digital still camera applications. The 9.0
Quantum Efficiency
µm square pixels with microlenses provide high (KAI-11000CM) RGB
34%, 37%, 42%
sensitivity and the large full well capacity results in
high dynamic range. The two high-speed outputs and Output Sensitivity 13 µV/e
binning capabilities allow for 1-3 frames per second
Total Noise 30 electrons
(fps) video rate for the progressively scanned images.
The vertical overflow drain structure provides Dark Current < 50 mV/s
antiblooming protection and enables electronic
Dark Current Doubling
shuttering for precise exposure control. Other features 7 ºC
Temperature
include low dark current, negligible lag and low smear.
Dynamic Range 66 dB
Charge Transfer
> 0.99999
Efficiency
Blooming Suppression > 1000X
Smear < -80 dB
Image Lag < 10 electrons
All parameters above are specified at T = 40*C
Maximum Data Rate 28 MHz
REVISION NO.: 4.0
EFFECTIVE DATE: March 14, 2005 40-pin, CerDIP, 0.070” pin
Package
spacing
Cover Glass AR Coated
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IMAGE SENSOR SOLUTIONS

DEVICE DESCRIPTION
Architecture
Overall

16 Dark Rows

8 Buffer Rows
B G B G
G R G R

12 Buffer Columns

13 Buffer Columns
20 Dark Columns

19 Dark Columns
4008 (H) x 2672 (V)
Active Pixels

Pixel 1,1
4 Dummy Pixels

4 Dummy Pixels
B G B G
G R G R
8 Buffer Rows

17 Dark Rows

Video L Fast Line Dump

Video R

Single 4 20 12 4008 13 19 4
or
Dual 4 20 12 2004 2004 13 19 4
Output

Figure 1 - Sensor Architecture

There are 17 light shielded rows followed 2688 half of the image is clocked out Video R. For the
photoactive rows and finally 16 more light shielded Video L each row consists of 4 empty pixels
rows. The first 8 and the last 8 photoactive rows followed by 20 light shielded pixels followed by
are buffer rows giving a total of 2672 lines of 2016 photosensitive pixels. For the Video R each
image data. row consists of 4 empty pixels followed by 19 light
shielded pixels followed by 2017 photosensitive
In the single output mode all pixels are clocked out pixels. When reconstructing the image, data from
of the Video L output in the lower left corner of the Video R will have to be reversed in a line buffer
sensor. The first 4 empty pixels of each line do not and appended to the Video L data.
receive charge from the vertical shift register. The
next 20 pixels receive charge from the left light The dark rows are not entirely dark and so should
shielded edge followed by 4033 photosensitive not be used for a dark reference level. Use the
pixels and finally 19 more light shielded pixels dark columns on the left or right side of the image
from the right edge of the sensor. The first 12 and sensor as a dark reference.
last 13 photosensitive pixels are buffer pixels
giving a total of 4008 pixels of image data. Of the dark columns, the first and last dark
columns should not be used for determining the
In the dual output mode the clocking of the right zero signal level. Some light does leak into the first
half of the horizontal CCD is reversed. The left half and last dark columns.
of the image is clocked out Video L and the right

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IMAGE SENSOR SOLUTIONS

Pixel
Top View
Cross Section Down Through VCCD
Direction

V1
of V1 V2 V1
Charge
Transfer
Photodiode 9.0
µm Direction of
Transfer Charge
n- n- n-
Gate
V2 n Transfer

p Well (GND)

9.0
µm n Substrate
True Two Phase Burried Channel VCCD
Lightshield over VCCD not shown

Cross Section Through Cross Section Through Photodiode

Photodiode and VCCD Phase 1 and VCCD Phase 2 at Transfer Gate
Photo Light Shield Light Shield
Transfer
diode
V1 Gate V2

p p+ p n p p p+ n p
n p n p

p p

n n
Substrate Substrate

Cross Section Showing Lenslet

Drawings not scale

Lenslet

Red Color Filter

Light Shield Light Shield

VCCD VCCD
Photodiode

Figure 2 - Pixel Architecture

An electronic representation of an image is formed the number of photoelectrons collected at each
when incident photons falling on the sensor plane pixel is linearly dependant upon light level and
create electron-hole pairs within the individual exposure time and non-linearly dependant on
silicon photodiodes. These photoelectrons are wavelength. When the photodiodes charge
collected locally by the formation of potential wells capacity is reached, excess electrons are
at each photosite. Below photodiode saturation, discharged into the substrate to prevent blooming.

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IMAGE SENSOR SOLUTIONS

Vertical to Horizontal Transfer

Top View
Direction of
Vertical
Charge V1
Transfer
Photo
diode
Transfer
Gate V2

V1

Fast
Line V2
Dump

Lightshield
not shown

H H
H2 H1S
1 2
S
B B

Direction of
Horizontal
Charge Transfer

Figure 3 - Vertical to Horizontal Transfer Architecture

When the V1 and V2 timing inputs are pulsed, Charge is transferred from the last vertical CCD
charge in every pixel of the VCCD is shifted one phase into the H1S horizontal CCD phase. Refer
row towards the HCCD. The last row next to the to Figure 24 for an example of timing that
HCCD is shifted into the HCCD. When the VCCD accomplishes the vertical to horizontal transfer of
is shifted, the timing signals to the HCCD must be charge.
stopped. H1 must be stopped in the high state and
H2 must be stopped in the low state. The HCCD If the fast line dump is held at the high level (FDH)
clocking may begin THD µs after the falling edge during a vertical to horizontal transfer, then the
of the V1 and V2 pulse. entire line is removed and not transferred into the
horizontal register.

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IMAGE SENSOR SOLUTIONS

Horizontal Register to Floating Diffusion

RD R OG H1 H2S H2B H1S H1B H2S

n- n- n-
n+ n n+ n (burried channel)

Floating
Diffusion p (GND)

n (SUB)

Figure 4 - Horizontal Register to Floating Diffusion Architecture

The HCCD has a total of 4080 pixels. The 4072 When the HCCD is shifting valid image data, the
vertical shift registers (columns) are shifted into timing inputs to the electronic shutter (SUB),
the center 4072 pixels of the HCCD. There are 4 VCCD (V1, V2), and fast line dump (FD) should be
pixels at both ends of the HCCD, which receive no not be pulsed. This prevents unwanted noise from
charge from a vertical shift register. The first 4 being introduced. The HCCD is a type of charge
clock cycles of the HCCD will be empty pixels coupled device known as a pseudo-two phase
(containing no electrons). The next 20 clock cycles CCD. This type of CCD has the ability to shift
will contain only electrons generated by dark charge in two directions. This allows the entire
current in the VCCD and photodiodes. The next image to be shifted out to the video L output, or to
4033 clock cycles will contain photo-electrons the video R output (left/right image reversal). The
(image data). Finally, the last 19 clock cycles will HCCD is split into two equal halves of 2040 pixels
contain only electrons generated by dark current in each. When operating the sensor in single output
the VCCD and photodiodes. Of the 20 dark mode the two halves of the HCCD are shifted in
columns at the start of the line and the 19 dark the same direction. When operating the sensor in
columns at the end of the line, the first and last dual output mode the two halves of the HCCD are
dark columns should not be used for determining shifted in opposite directions. The direction of
the zero signal level. Some light does leak into the charge transfer in each half is controlled by the
first and last dark columns. Only use the center 18 H1BL, H2BL, H1BR, and H2BR timing inputs.
columns of the 20 column dark reference at the
start of the line. Only use the center 17 columns of
the 19 column dark reference at the end of the
line.

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IMAGE SENSOR SOLUTIONS

Horizontal Register Split

H1 H2 H2 H1 H1 H2 H2 H1 H1 H2

H1BL H2SL H2BL H1SL H1BL H2SL H1BR H1SR H2BR H2SR

Pixel Pixel
2040 2041
Single Output

H1 H2 H2 H1 H1 H2 H1 H1 H2 H2

H1BL H2SL H2BL H1SL H1BL H2SL H1BR H1SR H2BR H2SR

Pixel Pixel
2040 2041
Dual Output

Figure 5 - Horizontal Register

output mode to change the direction of charge
Single Output Operation transfer of the right side horizontal shift register. In
When operating the sensor in single output mode dual output mode both VDDL and VDDR (pins 3,
all pixels of the image sensor will be shifted out 18) should be connected to 15 V. The H1 timing
the Video L output (pin 2). To conserve power and from the timing diagrams should be applied to
lower heat generation the output amplifier for H1SL, H1BL, H1SR, H1BR, and the H2 timing
Video R may be turned off by connecting VDDR should be applied to H2SL, H2BL, H2SR, and
(pin 18) and VOUTR (pin 19) to GND (zero volts). H2BR. The clock driver generating the H1 timing
should be connected to pins 8, 9, 13, and 12. The
The H1 timing from the timing diagrams should be clock driver generating the H2 timing should be
applied to H1SL, H1BL, H1SR, H2BR, and the H2 connected to pins 7, 10, 14, and 11. The
timing should be applied to H2SL, H2BL, H2SR, horizontal CCD should be clocked for 4 empty
and H1BR. In other words, the clock driver pixels plus 20 light shielded pixels plus 2016
generating the H1 timing should be connected to photoactive pixels for a total of 2040 pixels. If the
pins 8, 9, 13, and 11. The clock driver generating camera is to have the option of dual or single
the H2 timing should be connected to pins 7, 10, output mode, the clock driver signals sent to H1BR
14, and 12. The horizontal CCD should be clocked and H2BR may be swapped by using a relay.
for 4 empty pixels plus 20 light shielded pixels plus Another alternative is to have two extra clock
4032 photoactive pixels plus 20 light shielded drivers for H1BR and H2BR and invert the signals
pixels for a total of 4076 pixels. H1BINL and in the timing logic generator. If two extra clock
H1BINR use the H1 timing, but should be drivers are used, care must be taken to ensure the
generated from a separate clock driver for optimal rising and falling edges of the H1BR and H2BR
performance. clocks occur at the same time (within 3ns) as the
other HCCD clocks.
Dual Output Operation
In dual output mode the connections to the H1BR
and H2BR pins are swapped from the single

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IMAGE SENSOR SOLUTIONS

Output

H1B
HCCD
Charge
H1S
Transfer
H2B

H2S

31 KΩ

H1BIN
VDD
OG

RD

Floating
Diffusion VOUT

Source Source Source

Follower Follower Follower
#1 #2 #3

Figure 6 - Output Architecture

Charge packets contained in the horizontal gain. The translation from the charge domain to
register are dumped pixel by pixel onto the floating the voltage domain is quantified by the output
diffusion (fd) output node whose potential varies sensitivity or charge to voltage conversion in terms
linearly with the quantity of charge in each packet. of microvolts per electron (µV/e-). After the signal
The amount of potential charge is determined by has been sampled off chip, the reset clock (R)
the expression ∆Vfd=∆Q/Cfd. A three-stage removes the charge from the floating diffusion and
source-follower amplifier is used to buffer this resets its potential to the reset drain voltage (RD).
signal voltage off chip with slightly less than unity

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Physical Description

Pin Description and Device Orientation

VRDR
VRDL

GND

GND
GND

GND
GND
GND
GND

GND

OGR
OGL

SUB

ESD
FD

FD
V1
V2

V1
V2
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Pixel 1,1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
H2BR
H1BR

H1SR
H2SR

H1BINR

VDDR
VOUTR

RR
RL
VOUTL

GND

GND
VDDL

H2SL
H1SL

H1BL
H2BL

GND

GND
H1BINL

Pin Name Description Pin Name Description

1 RL Reset Gate, Left 40 OGL Output Gate, Left
2 VOUTL Video Output, Left 39 FD Fast Line Dump Gate
3 VDDL Vdd, Left 38 RDL Reset Drain, Left
4 GND Ground 37 V1 Vertical Clock, Phase 1
5 H1BINL H1 Last Phase, Left 36 V2 Vertical Clock, Phase 2
6 GND Ground 35 GND Ground
7 H2SL H2 Storage, Left 34 SUB Substrate
8 H1SL H1 Storage, Left 33 GND Ground
9 H1BL H1 Barrier, Left 32 GND Ground
10 H2BL H2 Barrier, Left 31 GND Ground
11 H2BR H2 Barrier, Right 30 GND Ground
12 H1BR H1 Barrier, Right 29 GND Ground
13 H1SR H1 Storage, Right 28 GND Ground
14 H2SR H2 Storage, Right 27 ESD ESD Protection
15 GND Ground 26 GND Ground
16 H1BINR H1 Last Phase, Right 25 V1 Vertical Clock, Phase 1
17 GND Ground 24 V2 Vertical Clock, Phase 2
18 VDDR Vdd, Right 23 RDR Reset Drain, Right
19 VOUTR Video Output, Right 22 FD Fast Line Dump Gate
20 RR Reset Gate, Right 21 OGR Output Gate, Right

The pins are on a 0.07” spacing

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PERFORMANCE

Power - Estimated

Right Output Disabled

500
450
400
350
Power (mW)

300
250
200
150
100
50
0
0 5 10 15 20 25 30
Horizontal Clock Frequency (MHz)

Output Pow er One Output(mW) Horizonatl Pow er (mW)

Vertical Pow er One Output(mW) Total Pow er One Output (mW)

Figure 7 - Power

Frame Rates – Continuous Mode

4.5
Dual output
4

3.5
Frame Rate (fps)

3
Single output
2.5

1.5

0.5

0
0 5 10 15 20 25 30
Pixel Clock (MHz)

Figure 8 - Frame Rates

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Imaging Performance

Image Performance Operational Conditions

Unless otherwise noted, the Imaging Performance Specifications are measured using the following
conditions:

Description Condition Notes

Frame time 1732 msec 1

Horizontal clock
10 MHz
frequency
Continuous red, green
and blue illumination
Light source (LED) 2, 3
centered at 450, 530 and
650 nm
Nominal operating
Operation
voltages and timing

Notes:
1. Electronic shutter is not used. Integration time equals frame time.
2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP-8115.
3. For monochrome sensor, only green LED used.

Imaging Performance Specifications

KAI-11000M and KAI-11000CM
Tempera-
Samp-
ture(s)
Description Symbol Min. Nom. Max. Units ling Notes Test
Tested At
Plan
(°C)

Maximum
Photoresponse NL n/a 2 % Design 2, 3
Nonlinearity
Maximum Gain
Difference Between ∆G n/a 10 % Design 2, 3
Outputs
Max. Signal Error due
∆NL n/a 1 % Design 2, 3
to Nonlinearity Dif.
Horizontal CCD Charge
HNe 139 ke- Design
Capacity
Vertical CCD Charge
VNe 90 91 ke- Die
Capacity
Photodiode Charge
PNe 58 60 ke- Die
Capacity
Horizontal CCD Charge
HCTE 0.99999 n/a Design
Transfer Efficiency
Vertical CCD Charge
VCTE 0.99999 n/a Design
Transfer Efficiency

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Tempera-
Samp-
ture(s)
Description (cont) Symbol Min. Nom. Max. Units ling Notes Test
Tested At
Plan
(°C)

Photodiode Dark
Ipd n/a 800 e/p/s Die 27, 40
Current
Photodiode Dark
Ipd n/a 0.15 nA/cm2 Die 27, 40
Current
Vertical CCD Dark
Ivd n/a 3800 e/p/s Die 27, 40
Current
Vertical CCD Dark
Ivd n/a 0.5 nA/cm2 Die 27, 40
Current
Image Lag Lag n/a <10 50 e- Design
Antiblooming Factor Xab 100 300 n/a Design
Vertical Smear Smr n/a -85 -75 dB Design
-
Total Noise ne-T 30 e rms Design 4
Dynamic Range DR 66 dB Design 5
Output Amplifier DC
Vodc 4 9 14 V Die
Offset
Output Amplifier
F-3db 106 MHz Die 6
Bandwidth
Output Amplifier
ROUT 100 150 200 Ohms Die
Impedance
Output Amplifier
∆V/∆N 13 µV/e- Design
Sensitivity

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KAI-11000M
Tempera-
Samp-
ture(s)
Description Symbol Min. Nom. Max. Units ling Notes Test
Tested At
Plan
(°C)

Peak Quantum
QEmax 45 50 n/a % Design
Efficiency
Peak Quantum
λQE n/a 500 n/a nm
Efficiency Wavelength

KAI-11000CM
Tempera-
Samp-
ture(s)
Description Symbol Min. Nom. Max. Units ling Notes Test
Tested At
Plan
(°C)

Peak Red 34 n/a

Quantum Green QEmax 37 n/a % Design
Efficiency Blue 42 n/a
Peak Red
630 n/a
Quantum Green
λQE 550 n/a nm Design
Efficiency Blue
470 n/a
Wavelength
n/a: not applicable

Notes:
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 30 MHz.
5. Uses 20LOG(PNe/ ne-T)
6. Last stage only, Cload=10pF. Then f-3db = (1 / (2π*Rout*Cload))

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Defect Definitions

Class S Class 1 Class 2 Class 2

Maximum Maximum Maximum Maximum
Tempera
Monochro Color or Color Monochro
ture(s) Note
Description Definition me Monochrom Only me Only Test
tested at s
e
with with or with or (°C)
microlens with or with without without
only microlens microlens microlens

Major dark
field
Defect >= 239 mV 1 1
defective
pixel
100 100 200 200 27, 40
Major bright
field
Defect >= 15 % 1 2
defective
pixel
Minor dark
field
Defect >= 123 mV 1000 1000 2000 2000 27, 40 1 1
defective
pixel
A group of 2 to “N”
contiguous major 1 20 20 20
Cluster defective pixels, but
N=10 N=10 N=10 N=12 27, 40 1
defect no more than “W”
adjacent defects W=3 W=3 W=3 W=5
horizontally
A group of more than
Column 10 contiguous major
0 0 10 2 27, 40 1
defect defective pixels along
a single column

Notes:
1. There will be at least two non-defective pixels separating any two major defective pixels.

Defect Map
The defect map supplied with each sensor is based upon testing at an ambient (27°C) temperature.
Minor point defects are not included in the defect map. All pixels are referenced to
pixel 1,1 in the defect map.

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Quantum Efficiency
Color with Microlens Quantum Efficiency

0.45

0.40
Absolute Quantum Efficiency

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00
400 500 600 700 800 900 1000
Wavelength (nm )

Red Green Blue

Figure 9 - Color with Microlens Quantum Efficiency Using AR Glass

Color without Microlens Quantum Efficiency

0.18

0.16
Absolute Quantum Efficiency

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00
400 500 600 700 800 900 1000
Wavelength (nm )

Red Green Blue

Figure 10 - Color without Microlens Quantum Efficiency Using AR Glass

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Monochrome with Microlens Quantum Efficiency

0.60

0.50
Absolute Quantum Efficiency

0.40

0.30

0.20

0.10

0.00
300 400 500 600 700 800 900 1000
Wavelength (nm )

Figure 11 - Monochrome with Microlens Quantum Efficiency

Monochrome without Microlens Quantum Efficiency

0.20

0.18

0.16
Absolute Quantum Efficiency

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00
400 500 600 700 800 900 1000
Wavelength (nm )

Figure 12 - Monochrome without Microlens Quantum Efficiency

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Angular Quantum Efficiency

For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Lenslets

100%

90%
Vertical
Relative Quantum Efficiency (%)

80%

70%

60%

50%
Horizontal
40%

30%

20%

10%

0%
0 5 10 15 20 25 30
Angle (degress)

Figure 13 – Monochrome with Lenslets Angular Quantum Efficiency

Color with Lenslets

100%
Red
90% Vertical
Green
80% Blue
Vertical
Relative Quantum Efficiency

70%

60%

50%

40%
Horizontal
30%

20%

10%

0%
-25 -20 -15 -10 -5 0 5 10 15 20 25
Angle (degress)

Figure 14 - Color with Lenslets Angular Quantum Efficiency

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TEST DEFINITIONS

Test Regions of Interest

Active Area ROI: Pixel 1, 1 to Pixel 4008,2672

Center 100 by 100 ROI: Pixel 1954,1336 to Pixel 2053,1435

Only the active pixels are used for performance and defect tests.

OverClocking

The test system timing is configured such that the sensor is overclocked in both the vertical and
horizontal directions. See Figure 15 for a pictorial representation of the regions.

Pixel 1,1

Horizontal Overclock
V

Vertical Overclock

Figure 15 - Overclock Regions of Interest

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Tests
1. Dark field defect test
This test is performed under dark field conditions. The sensor is partitioned into 384 sub regions of
interest, each of which is 167 by 167 pixels in size. In each region of interest, the median value of all
pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to
the median value of that region of interest plus the defect threshold specified in the “Defect
Definitions” section.

2. Bright field defect test

This test is performed with the imager illuminated to a level such that the output is at approximately
40,000 electrons. Prior to this test being performed the substrate voltage has been set such that the
charge capacity of the sensor is 60,000 electrons. The average signal level of all active pixels is
found. The bright and dark thresholds are set as:
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold

The sensor is then partitioned into 384 sub regions of interest, each of which is 167 by 167 pixels in
size. In each region of interest, the average value of all pixels is found. For each region of interest, a
pixel is marked defective if it is greater than or equal to the median value of that region of interest plus
the bright threshold specified or if it is less than or equal to the median value of that region of interest
minus the dark threshold specified.
Example for major bright field defective pixels:
• Average value of all active pixels is found to be 520 mV (40,000 electrons).
• Dark defect threshold: 520mV * 15% = 78 mV
• Bright defect threshold: 520mV * 15% = 78 mV
• Region of interest #1 selected. This region of interest is pixels 1,1 to pixels 167,167.
o Median of this region of interest is found to be 520 mV.
o Any pixel in this region of interest that is >= (520+78 mV) 598 mV in intensity will be
marked defective.
o Any pixel in this region of interest that is <= (520-78 mV) 442 mV in intensity will be
marked defective.
• All remaining 384 sub regions of interest are analyzed for defective pixels in the same
manner.

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OPERATION

Maximum Ratings
Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per
the description. If the level or the condition is exceeded, the device will be degraded and may be
damaged.

Description Symbol Minimum Maximum Units Notes

Operating Temperature TOP -50 70 °C 1

Humidity RH 5 90 % 2
Output Bias Current Iout 0.0 -40 mA 3
Off-chip Load CL 10 pF

Notes:
1. Noise performance will degrade at higher temperatures.
2. T=25ºC. Excessive humidity will degrade MTTF.
3. Total for both outputs. Current is -20 mA for each output. Avoid shorting output pins to ground or any low
impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance
at the expense of reduced gain (sensitivity). Operation at these values will reduce MTTF.

Maximum Voltage Ratings Between Pins

Description Minimum Maximum Units Notes
RL, RR, H1BINL, H1BINR,
H2SL, H1SL, H1BL, H2BL,
0 17 V
H2BR, H1BR, H1SR, H2SR,
OGL, OGR to ESD
Pin to Pin with ESD Protection -17 17 V 1
VDDL, VDDR to GND 0 25 V

Notes:
1. Pins with ESD protection are: RL, RR, H1BINL, H1BINR, H2SL, H1SL, H1BL, H2BL, H2BR, H1BR, H1SR,
H2SR, OGL, and OGR.

Caution: This device contains limited protection against Electrostatic Discharge (ESD)
Devices should be handled in accordance with strict ESD procedures for Class 0 devices (JESD22
Human Body Model) or Class A (Machine Model). Refer to Application Note MTD/PS-0224, “Electrostatic
Discharge Control”

Caution: Improper cleaning of the cover glass may damage these devices.
Refer to Application Note MTD/PS-0237, “Cover Glass Cleaning for Image Sensors”

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DC Bias Operating Conditions

Maximum DC
Description Symbol Minimum Nominal Maximum Units Notes
Current (mA)

Output Gate OG -3.0 -2.5 -2.0 V 1 µA

Reset Drain RD 10.5 11.5 12.0 V 1 µA
Output Amplifier Supply VDD 14.5 15.0 15.5 V 2 mA 4
Ground GND 0.0 0.0 0.0 V
Substrate SUB 8.0 TBD 17.0 V 1
ESD Protection ESD -9.0 -8.0 -7.0 V 2
Output Bias Current Iout -5 -10 mA 3

Notes:
1. The operating of the substrate voltage, Vab, will be marked on the shipping container for each device. The value
of Vab is set such that the photodiode charge capacity is 60,000 electrons.
2. VESD must be at least 1 V more negative than H1L and H2L during sensor operation AND during camera power
turn on.
3. An output load sink must be applied to Vout to activate output amplifier.
4. The maximum DC current is for one output unloaded. This is the maximum current that the first two stages of
one output amplifier will draw. This value is with Vout disconnected.

Power Up Sequence
1. Substrate
2. ESD Protection
3. All other biases and clocks.

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AC Operating Conditions

Clock Levels
Description Symbol Minimum Nominal Maximum Units Notes

Vertical CCD Clock High V2H 7.5 8.0 8.5 V

Vertical CCD Clocks Midlevel V1M, V2M -0.2 0.0 0.2 V
Vertical CCD Clocks Low V1L, V2L -9.5 -9.0 -8.5 V
Horizontal CCD Clocks Amplitude H1H, H2H 5.8 6.0 6.2 V
Horizontal CCD Clocks Low H1L, H2L -4.2 -4.0 -3.8 V
Reset Clock High RH 1.3 1.5 1.7 V
Reset Clock Low RL -3.7 -3.5 -3.3 V
Electronic Shutter Voltage Vshutter 39 40 48 V
Fast Dump High FDH 4.5 5.0 5.5 V
Fast Dump Low FDL -9.5 -9.0 -8.5 V 1
Notes:
1. FDL can use the same supply as Vertical CCD Clocks Low if desired.

Clock Line Capacitances

Clocks Capacitance Units Notes

V1 to GND 108 nF 1
V2 to GND 118 nF 1
V1 to V2 56 nF
H1S to GND 27 pF 2
H2S to GND 27 pF 2
H1B to GND 13 pF 2
H2B to GND 4 pF 2
H1S to H2B and H2S 13 pF 2
H1B to H2B and H2S 13 pF 2
H2S to H1B and H1S 13 pF 2
H2B to H1B and H1S 13 pF 2
H1BIN to GND 20 pF 2
R to GND 10 pF
FD to GND 20 pF

Notes:
1. Gate capacitance to GND is voltage dependent. Value is for nominal VCCD clock voltages.
2. For nominal HCCD clock voltages, these values are for half of the imager (H1SL, H1BL, H2SL, H2BL and
H1BINL or H1SR, H1BR, H2SR, H2BR and H1BINR).

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Timing Requirements

Description Symbol Minimum Nominal Maximum Units Notes

HCCD Delay THD 3.0 3.5 10.0 µs

VCCD Transfer time TVCCD 3.0 3.5 20.0 µs
Photodiode Transfer time TV3rd 8.0 10.0 15.0 µs
VCCD Pedestal time T3P 100.0 120.0 200.0 µs
VCCD Delay T3D 15.0 20.0 80.0 µs
Reset Pulse time TR 2.5 5.0 ns
Shutter Pulse time TS 3.0 4.0 10.0 µs
Shutter Pulse delay TSD 1.0 1.5 10.0 µs
HCCD Clock Period TH 33 200 ns
VCCD rise/fall time TVR 0.0 0.1 1.0 µs
Fast Dump Gate delay TFD 0.5 µs
Vertical Clock Edge Alignment TVE 0.0 100 ns

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Main Timing – Continuous Mode

Vertical Frame
Timing

Line Timing

Repeat for 2721

Lines

Figure 16 - Main Timing - Continuous Mode

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Frame Timing – Continuous Mode

Frame Timing without Binning

V1M
V1
V1L
V1H
TL TV3rd TL

V2M
V2
V2L
T3P T3D
2720 Line 2721 Line 1
H1H, H1BINH
H1, H1BIN
H1L, H1BINL
H2H
H2
H2L

Figure 17 - Framing Timing without Binning

Frame Timing for Vertical Binning by 2

V1

TL TV3rd TL 3 x TVCCD

V2

T3P T3D
Line 1360 Line 1361 Line 1

H1, H1BIN

H2

Figure 18 - Frame Timing for Vertical Binning by 2

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Frame Timing Edge Alignment

V1M
V1

V1L
V2H

V2M

V2
TVE V2L

Figure 19 - Frame Timing Edge Alignment

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Line Timing – Continuous Mode

Line Timing Single Output

TL

V1

TVCCD
V2

THD

H1, H1BIN
H2
R

pixel count
1
2
3
4
5
6

23
24
25
26
27
28

4053
4054
4055
4056
4057
4058

4073
4074
4075
4076
Figure 20 - Line Timing Single Output

Line Timing Dual Output – Left Output

TL

V1

TVCCD
V2

THD

H1, H1BIN
H2
R

pixel count
1
2
3
4
5
6

23
24
25
26
27
28

2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040

Figure 21 - Line Timing Dual Output – Left Output

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Line Timing Dual Output – Right Output

TL

V1

TVCCD
V2

THD

H1, H1BIN
H2
R

pixel count
1
2
3
4
5
6

23
24
25
26
27
28

2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
Figure 22 – Line Timing Dual Output – Right Output

Line Timing Vertical Binning by 2

TL

V1
TVCCD
V2

THD

H1, H1BIN
H2
R

pixel count
1
2
3
4
5

23
24
25
26
27
28

4053
4054
4055
4056
4057
4058

4073
4074
4075
4076

Figure 23 - Line Timing Vertical Binning by 2

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Line Timing Detail

V1

TVCCD
V2
TH THD

H1, H1BIN

H2

Figure 24 - Line Timing Detail

Line Timing Binning by 2 Detail

V1

TVCCD
V2
TH THD

H1, H1BIN

H2

Figure 25 - Line Timing by 2 Detail

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Line Timing Edge Alignment

TVCCD

V1

V2

TVE TVE

Figure 26 - Line Timing Edge Alignment

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Pixel Timing – Continuous Mode

V1

V2

H1,
H1BIN
H2

Pixel
Count
1 2 3 4 5 23 24 25 26

Vout

Dummy Pixels Light Shielded Pixels Photosensitive Pixels

Figure 27 - Pixel Timing

Pixel Timing Detail

tR
RH
R
RL
H1, H1H, H1BINH
H1BIN H1L, H1BINL
H2H
H2
H2L

VOUT

Figure 28 - Pixel Timing Detail

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Fast Line Dump Timing

φFD

φV1

φV2

TFD TVCCD TFD

TVCCD

φH1
φH2

Figure 29 - Fast Line Dump Timing

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Electronic Shutter

Electronic Shutter Line Timing

φV1
TVCCD
φV2

THD
VShutter

TS

VSUB
TSD

φH1
φH2
φR

Figure 30 - Electronic Shutter Line Timing

Electronic Shutter – Integration Time Definition

φV2

Integration Time
VShutter

VSUB
Figure 31 - Integration Time Definition

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Electronic Shutter Description

The voltage on the substrate (SUB) determines VSUB voltage provides lower dynamic range and
the charge capacity of the photodiodes. When maximum antiblooming protection. The optimal
SUB is 8 volts the photodiodes will be at their setting of VSUB is written on the container in
maximum charge capacity. Increasing VSUB which each KAI-11000 is shipped. The given
above 8 volts decreases the charge capacity of VSUB voltage for each sensor is selected to
the photodiodes until 40 volts when the provide antiblooming protection for bright spots at
photodiodes have a charge capacity of zero least 100 times saturation, while maintaining at
electrons. Therefore, a short pulse on SUB, with a least 60 ke- of dynamic range.
peak amplitude greater than 40 volts, empties all
photodiodes and provides the electronic shuttering The electronic shutter provides a method of
action. precisely controlling the image exposure time
without any mechanical components. If an
It may appear the optimal substrate voltage setting integration time of TINT is desired, then the
is 8 volts to obtain the maximum charge capacity substrate voltage of the sensor is pulsed to at
and dynamic range. While setting VSUB to 8 volts least 40 volts TINT seconds before the photodiode
will provide the maximum dynamic range, it will to VCCD transfer pulse on V2. Use of the
also provide the minimum antiblooming protection. electronic shutter does not have to wait until the
previously acquired image has been completely
The KAI-11000 VCCD has a charge capacity of read out of the VCCD.
90,000 electrons (90 ke-). If the SUB voltage is set
such that the photodiode holds more than 90 ke-,
then when the charge is transferred from a full
photodiode to VCCD, the VCCD will overflow. This
overflow condition manifests itself in the image by
making bright spots appear elongated in the
vertical direction. The size increase of a bright
spot is called blooming when the spot doubles in
size.

The blooming can be eliminated by increasing the

voltage on SUB to lower the charge capacity of the
photodiode. This ensures the VCCD charge
capacity is greater than the photodiode capacity.
There are cases where an extremely bright spot
will still cause blooming in the VCCD. Normally,
when the photodiode is full, any additional
electrons generated by photons will spill out of the
photodiode. The excess electrons are drained
harmlessly out to the substrate. There is a
maximum rate at which the electrons can be
drained to the substrate. If that maximum rate is
exceeded, (for example, by a very bright light
source) then it is possible for the total amount of
charge in the photodiode to exceed the VCCD
capacity. This results in blooming.

The amount of antiblooming protection also

decreases when the integration time is decreased.
There is a compromise between photodiode
dynamic range (controlled by VSUB) and the
amount of antiblooming protection. A low VSUB
voltage provides the maximum dynamic range and
minimum (or no) antiblooming protection. A high
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STORAGE AND HANDLING

Storage Conditions

Description Symbol Minimum Maximum Units Notes

Storage
TST -20 80 °C 1
Temperature
Humidity RH 5 90 % 2

Notes:
1. Long-term exposure toward the maximum temperature will accelerate color filter degradation.
2. T=25ºC. Excessive humidity will degrade MTTF.

ESD
1. This device contains limited protection against Electrostatic Discharge (ESD). CCD image
sensors can be damaged by electrostatic discharge. Failure to do so may alter device
performance and reliability.
2. Devices should be handled in accordance with strict ESD procedures for Class 0 (<250V per
JESD22 Human Body Model test), or Class A (<200V JESD22 Machine Model test) devices.
Devices are shipped in static-safe containers and should only be handled at static-safe
workstations.
3. See Application Note MTD/PS-0224 “ Electrostatic Discharge Control for Image Sensors” for
proper handling and grounding procedures. This application note also contains recommendations
for workplace modifications for the minimization of electrostatic discharge.
4. Store devices in containers made of electro-conductive materials.

Cover Glass Care and Cleanliness

1. The cover glass is highly susceptible to particles and other contamination. Perform all assembly
operations in a clean environment.
2. Touching the cover glass must be avoided
3. Improper cleaning of the cover glass may damage these devices. Refer to Application Note
MTD/PS-0237 “Cover Glass Cleaning for Image Sensors”

Environmental Exposure
1. Do not expose to strong sun light for long periods of time. The color filters and/or microlenses
may become discolored. Long time exposures to a static high contrast scene should be avoided.
The image sensor may become discolored and localized changes in response may occur from
color filter/microlens aging.
2. Exposure to temperatures exceeding the absolute maximum levels should be avoided for storage
and operation. Failure to do so may alter device performance and reliability.
3. Avoid sudden temperature changes.
4. Exposure to excessive humidity will affect device characteristics and should be avoided. Failure
to do so may alter device performance and reliability.
5. Avoid storage of the product in the presence of dust or corrosive agents or gases.

Long-term storage should be avoided. Deterioration of lead solderability may occur. It is advised
that the solderability of the device leads be re-inspected after an extended period of storage, over
one year.

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Soldering Recommendations
1. The soldering iron tip temperature is not to exceed 370ºC. Failure to do so may alter device
performance and reliability.
2. Flow soldering method is not recommended. Solder dipping can cause damage to the glass and harm
the imaging capability of the device. Recommended method is by partial heating. Kodak recommends
the use of a grounded 30W soldering iron. Heat each pin for less than 2 seconds duration.

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MECHANICAL DRAWINGS

Package

Figure 32 - Package Drawing

Note: See Available Part Configurations for a description of the marking code.

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Die to Package Alignment

Figure 33 - Die to Package Alignment

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Glass

Coat Both Sides

0.020R [0.50] (Typ. 8 plcs.)

Chamfer 0.020" [0.50] (Typ. 4 plcs.)

Ref. AR coat area

Epoxy: NC0-150 HB
Thk. 0.002" - 0.005"

Chamfer 0.008" [0.20] (Typ.

8 plcs.)

NOTES:

1. Multi-Layer Anti-Reflective Coating on 2 sides:

Double Sided Reflectance:
Range (nm)
420 - 450 nm < 2%
450 - 630 nm < 1%
630 - 680 nm < 2%
2. Dust, Scratch specification - 20 microns max.
3. Substrate - Schott D-263 or Equivalent

4. Epoxy: NCO-150HB
Thickness: 0.002" - 0.005"

Figure 34 - Glass Drawing

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Glass Transmission

100

90

80

70
Transmission (%)

60

50

40

30

20

10

0
200 300 400 500 600 700 800 900

Wavelength (nm )

Figure 35 – AR Glass Transmission

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QUALITY ASSURANCE AND RELIABILITY

Quality Strategy: All image sensors will conform to the specifications stated in this document. This will
be accomplished through a combination of statistical process control and inspection at key points of the
production process. Typical specification limits are not guaranteed but provided as a design target. For
further information refer to ISS Application Note MTD/PS-0292, Quality and Reliability.

Replacement: All devices are warranted against failure in accordance with the terms of Terms of Sale.
This does not include failure due to mechanical and electrical causes defined as the liability of the
customer below.

Liability of the Supplier: A reject is defined as an image sensor that does not meet all of the
specifications in this document upon receipt by the customer.

Liability of the Customer: Damage from mechanical (scratches or breakage), electrostatic discharge
(ESD) damage, or other electrical misuse of the device beyond the stated absolute maximum ratings,
which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer.

ESD Precautions: Devices are shipped in static-safe containers and should only be handled at static-
safe workstations. See ISS Application Note MTD/PS-0224, Electrostatic Discharge Control, for handling
recommendations.

Reliability: Information concerning the quality assurance and reliability testing procedures and results are
available from the Image Sensor Solutions and can be supplied upon request. For further information
refer to ISS Application Note MTD/PS-0292, Quality and Reliability.

Test Data Retention: Image sensors shall have an identifying number traceable to a test data file. Test
data shall be kept for a period of 2 years after date of delivery.

Mechanical: The device assembly drawing is provided as a reference. The device will conform to the
published package tolerances.

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ORDERING INFORMATION

Available Part Configurations

Type Description Glass Configuration Marking Code

KAI-11000
KAI-11000 Monochrome without microlens Taped on Cover Glass
Serial Number
KAI-11000M
KAI-11000M Monochrome with microlens Sealed AR Coated Both Sides
Serial Number
KAI-11000C
KAI-11000C Color without microlens Sealed AR Coated Both Sides
Serial Number
KAI-11000 CM
KAI-11000CM Color with microlens Sealed AR Coated Both Sides
Serial Number

Please contact Image Sensor Solutions for available part numbers.

Address all inquiries and purchase orders to:

Image Sensor Solutions

Eastman Kodak Company
Rochester, New York 14650-2010
Phone : (585) 722-4385
Fax : (585) 477-4947
E-mail : [email protected]

Kodak reserves the right to change any information contained herein without notice. All information
furnished by Kodak is believed to be accurate.

WARNING: LIFE SUPPORT APPLICATIONS POLICY

Kodak image sensors are not authorized for and should not be used within Life Support Systems without
the specific written consent of the Eastman Kodak Company. Product warranty is limited to replacement
of defective components and does not cover injury or property or other consequential damages.

45 KAI-11000 Rev 4.0

www.kodak.com/go/imagers 585-722-4385 Email: [email protected]
IMAGE SENSOR SOLUTIONS

REVISION CHANGES

Revision
Description of Changes
Number

1 Initial formal release

2 Page 16 - Addition of class 1 defect description.
Removed Low Dark Current Mode
Removed IR Glass option
Page 16: Defect class definitions changed
Class 1: Monochrome or Color
Class 2: Color only
3
Page 23: Changed VCCD Pedastal time, T3p values
was (50,60,80), now (100,120,200) for min, nom, max
Page 21: A caution was added for cover glass protective tape that is used on
each sensor.
Page 38: Changed glass drawing from IR to MAR.
Page 6 – Updated architecture. The right buffer columns were incorrectly
labeled 12. The correct count is 13. The right light shield columns
were incorrectly labeled as 20. The correct count is 19. The number
of dark rows above the fast line dump was incorrectly labeled as 16.
The correct count is 17. Note: the device has not physically
changed; the drawing was only incorrectly labeled.
Added paragraphs concerning use of dark rows and columns.
Page 17: Updated defect definitions table.
Page 18: Added color without microlens quantum efficiency graph.
Page 19 Added monochrome without microlens quantum efficiency graph.
Page 20: Updated angular quantum efficiency figures.
Page 23: Added Maximum Voltage Ratings Between Pins table.
4 Page 23: Removed note concerning cover glass protective tape.
Page 24: Updated Rd maximum bias voltage. Added power up sequence.
Page 24 – Added note 4.
Pages 27 to 31 – Updated all timing diagrams with respect to changes in
architecture as shown on page 6.
Page 37 – 5th paragraph – changed 70ke to 60ke.
Page 38: Updated storage and handling section.
Page 40: Updated package drawing.
Page 41: Updated die to package alignment drawing.
Page 44: Updated quality assurance and reliability section.
Page 45: Updated available part configuration table

46 KAI-11000 Rev 4.0

www.kodak.com/go/imagers 585-722-4385 Email: [email protected]