Design of Analog CMOS Integrated Circuits Behzad Razavi Professor of Electrical Engineering University of California, Los Angeles Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco St. Louis Bangkok Bogoté Caracas Lisbon London Madrid Mexico City Milan New Delhi Seoul Singapore Sydney Taipei TorontoMcGraw-Hill Higher Education 82 A Division of The McGraw Hill Companies DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS Published by McGraw-Hill, an imprint of The McGraw-Hill companies, Inc, 1221 Avenue of the Americas, ‘New York, NY, 10020. Copyright © 2001, by The McGraw-Hill Companies, Inc. All rights reserved. no part of. this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written consent of The McGraw-Hill Companies, Inc., including, but not limited to, in any network or other electronic storage or transmission, or broadcast for distance learning, ‘Some Ancillaries, including electronic and print components, may not be available to customers outside the United. States. ‘This book is printed on acid-free paper. 1234567890 FGRIFGR 909876543210 ISBN 0-07-238032-2 Vice president/Editor-in-chief: Kevin T: Kane Publisher: Thomas Casson Sponsoring editor: Catherine Fields Developmental editor: Michelle L. Flomenhoft Senior marketing manager: John T: Wannemacher Project manager: Jim Labeots Production supervisor: Gina Hangos Senior designer: Kierd Cunningham New media: Phillip Meek Compositor: Interactive Composition Corporation ‘Typeface: 10/12 Times Roman Printer: Quebecor Printing Book Company/Fairfeld Library of Congress Cataloging-in-Publication Data Razavi, Behzad. Design of analog CMOS integrated circuits / Behzad Razavi. pcm, ISBN 0-07-238032-2 (alk. paper) 1, Linear integrated circuits—Design and construction. 2. Metal oxide semiconductors, Complementary. 1. Title ‘TK7874.654. R39 2001 621,39'732-de21 00-044789About the Author Behzad Razavi received the B.Sc. degree in electrical engineering from Sharif University of Technology in 1985 and the M.Sc. and Ph.D. degrees in electrical engineering from Stan- ford University in 1988 and 1992, respectively. He was with AT&T Bell Laboratories and subsequently Hewlett-Packard Laboratories until 1996. Since September 1996, he has been an Associate Professor and subsequently a Professor of electrical engineering at University of California, Los Angeles. His current research includes wireless transceivers, frequency synthesizers, phase-locking and clock recovery for high-speed data communications, and data converters, Professor Razavi served as an Adjunct Professor at Princeton University, Princeton, NJ, from 1992 to 1994, and at Stanford University in 1995, He is a member of the Technical Program Committees of the Symposium on VLSI Circuits and the International Solid-State Circuits Conference (ISSCC), in which he is the chair of the Analog Subcommittee. He has also served as Guest Editor and Associate Editor of the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems, and International Journal of High Speed Electronics. Professor Razavi received the Beatrice Winner Award for Editorial Excellence at the 1994 ISSCC, the best paper award at the 1994 European Solid-State Circuits Conference, the best panel award at the 1995 and 1997 ISSCC, the TRW Innovative Teaching Award in 1997, and the best paper award at the IEEE Custom Integrated Circuits Conference in 1998, He is the author of Principles of Data Conversion System Design (IEEE Press, 1995), and RF Microelectronics (Prentice Hall, 1998), and the editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits (IEEE Press, 1996). viiPreface In the past two decades, CMOS technology has rapidly embraced the field of analog inte- grated circuits, providing low-cost, high-performance’ solutions and rising to dominate the market. While silicon bipolar and III-V devices still find niche applications, only CMOS Processes have emerged as a viable choice for the integration of today’s complex mixed- signal systems. With channel lengths projected to scale down to 0.03 zm, CMOS technology will continue to serve circuit design for probably another two decades. Analog circuit design itself has evolved with the technology as well. High-voltage, high- power analog circuits containing a few tens of transistors and processing small, continuous- time signals have gradually been replaced by low-voltage, low-power systems comprising thousands of devices and processing large, mostly discrete-time signals. For example, many analog techniques used only ten years ago have been abandoned because they do not lend themselves to low-voltage operation. This book deals with the analysis and design of analog CMOS integrated circuits, em- phasizing fundamentals as well as new paradigms that students and practicing engineers need to master in today’s industry. Since analog design requires both intuition and rigor, each concept is first introduced from an intuitive perspective and subsequently treated by careful analysis. The objective is to develop both a solid foundation and methods of ana- lyzing circuits by inspection so that the reader learns what approximations can be made in which circuits and how much error to expect in each approximation. This approach also enables the reader to apply the concepts to bipolar circuits with little additional effort. Thave taught most of the material in this book both at UCLA and in industry, polishing the order, the format, and the content with every offering. As the reader will see throughout the book, I follow four “golden rules” in writing (and teaching): (1) Iexplain why the reader needs to know the concept that is to be studied; (2) I put myself in the reader's position and predict the questions that he/she may have while reading the material for the first time; (3) With Rule 2 in mind, I pretend to know only as much as the (first-time) reader and try to “grow” with him/her, thereby experiencing the same through process; (4) I begin with the “core” concept in a simple (even imprecise) language and gradually add necessary modifications to arrive at the final (precise) idea. The last rule is particularly important in teaching circuits because it allows the reader to observe the evolution of a topology and hence learn both analysis and synthesis. ‘The text comprises 18 chapters whose contents and order are carefully chosen to provide a natural flow for both self-study and classroom adoption in quarter or semester systems. ixPreface Unlike some other books on analog design, we cover only a bare minimum of MOS device physics at the beginning, leaving more advanced properties and fabrication details for later chapters. To an expert, the elementary device physics treatment may appear oversimplified, but my experience suggests that (a) first-time readers simply do not absorb the high-order device effects and fabrication technology before they study circuits because they do not see the relevance; (b) if properly presented, even the simple treatment proves adequate for a substantial coverage of basic circuits; (c) readers learn advanced device phenomena and processing steps much more readily after they have been exposed to a significant amount of circuit analysis and design. Chapter 1 provides the reader with motivation for learning the material in this book. ‘Chapter 2 describes basic physics and operation of MOS devices. Chapters 3 through 5 deal with single-stage and differential amplifiers and current mir- rors, respectively, developing efficient analytical tools for quantifying the behavior of basic circuits by inspection, Chapters 6 and 7 introduce two imperfections of circuits, namely, frequency response and noise. Noise is treated at an early stage so that it “sinks in” as the reader accounts for its effects in subsequent circuit developments. Chapters 8 through 10 describe feedback, operational amplifiers, and stability in feed- back systems, respectively. With the useful properties of feedback analyzed, the reader is motivated to design high-performance, stable op amps and understand the trade-offs between speed, precision, and power dissipation, Chapters 11 through 13 deal with more advanced topics: bandgap references, elemen- tary switched-capacitor circuits, and the effect of nonlinearity and mismatch. These three subjects are included here because they prove essential in most analog and mixed-signal systems today. Chapters 14 and 15 concentrate on the design of oscillators and phase-locked loops, respectively. In view of the wide usage of these circuits, a detailed study of their behavior and many examples of their operation are provided. Chapter 16 is concerned with high-order MOS device effects and models, emphasizing the circuit design implications. If preferred, this chapter can directly follow Chapter 2 as well. Chapter 17 describes CMOS fabrication technology with a brief overview of layout design rules. Chapter 18 presents the layout and packaging of analog and mixed-signal circuits. Many practical issues that directly impact the performance of the circuit are described and various techniques are introduced, The reader is assumed to have a basic knowledge of electronic circuits and devices, e. pn junctions, the concept of small-signal operation, equivalent circuits, and simple biasing. For a senior-level elective course, Chapters 1 through 8 can be covered in a quarter and Chapters | through 10 in a semester. For a first-year graduate course, Chapters 1 through 11 plus one of Chapters 12 through 15 can be taught in one quarter, and the first 16 chapters in one semester. The problem sets at the end of each chapter are designed to extend the reader's un- derstanding of the material and complement it with additional practical considerations. A solutions manual is available for instructors. Behzad Razavi July 2000Acknowledgments Writing a book begins with a great deal of excitement. However, after two years of relent- less writing, drawing, and revising, when the book exceeds 600 pages and it is almost im- possible to make the equations and subscripts and superscripts in the last chapter consistent with those in the first, the author begins to feel the streaks of insanity, realizing that the book will never finish without the support of many other people. This book has benefited from the contributions of many individuals. A number of UCLA students read the first draft and the preview edition sentence by sentence. In particu- lar, Alireza Zolfaghari, Ellie Cijvat, and Hamid Rafati meticulously read the book and found several hundred errors (some quite subtle). Also, Emad Hegazi, Dawei Guo, Alireza Razzaghi, Jafar Savoj, and Jing Tian made helpful suggestions regarding many chapters, I thank all. Many experts in academia and industry read various parts of the book and provided useful feedback. Among them are Brian Brandt (National Semiconductor), Matt Corey (National Semiconductor), Terri Fiez (Oregon State University), Ian Galton (UC San Diego), Ali Hajimiri (Caltech), Stacy Ho (Analog Devices), Yin Hu (Texas Instruments), Shen-luan Liu (National Taiwan University), Joe Lutsky (National Semiconductor), Amit Mehrotra (University of Ilinois, Urbana-Champaign), David Robertson (Analog Devices), David Su (T-Span), Tao Sun (National Semiconductor), Robert Taft (National Semiconductor), and Masoud Zargari (T-Span). Jason Woo (UCLA) patiently endured and answered my questions about device physics. I thank all, Ramesh Harjani (University of Minnesota), John Nyenhius (Purdue University), Norman Tien (Cornell University), and Mahmoud Wagdy (California State University, Long Beach) reviewed the book proposal and made valuable suggestions. I thank all My wife, Angelina, has made many contributions to this book, from typing chapters to finding numerous errors and raising questions that made me reexamine my own understand- ing. Iam very grateful to her. The timely production of the book was made possible by the hard work of the staff at McGraw-Hill, particularly, Catherine Fields, Michelle Flomenhoft, Heather Burbridge, Denise Santor-Mitzit, and Jim Labeots. I thank all.xii Acknowledgments I learned analog design from two masters: Mehrdad Sharif-Bakhtiar (Sharif University of Technology) and Bruce Wooley (Stanford University) and it is only appropriate that I express my gratitude to them here, What I inherited from them will be inherited by many generations of students, Bebzad Razavi July 2000Brief Contents 1 Introduction to Analog Desi; 1 2 Basic MOS Device Physics . 9 3. Single-Stage Amplifiers . 47 4. Differential Amplifiers . 100 5 Passive and Active Current rs 135 6 Frequency Response of Amplifiers 166 7 Noise. 201 8 Feedback. 246 9 Operational Amplifiers. . 291 10 Stability and Frequency Comper 345 11 Bandgap References .... 377 12 Introduction to Switched-Capacitor Circuits 405 13 Nonlinearity and Mismatch 448 14 Oscillators. . 482 15 Phase-Locked Loops . . 532 16 Short-Channel Effects and Device 579 17 CMOS Processing Technology . 604 18 Layout and Packaging Index xiiContents Acknowledgments. 1 Introduction to Analog Design... 1.1. Why Analog? 1.2. Why Integrated’ 1.3 Why CMOS? 1.4 Why This Book’ 1,5 General Concepts 1.5.1 Levels of Abstraction . 1.5.2 Robust Analog Design 2 Basic MOS Device Physics 9 2.1 General Considerations . 10 2.1.1 MOSFET as a Switch. 10 2.1.2 MOSFET Structure . 10 2.1.3 MOS Symbols . 12 2.2. MOS I/V Characteristics 13 2.2.1 Threshold Voltage. . 13 2.2.2: Derivation of I/V Characteristics . 15 2.3. Second-Order Effects . 23 2.4 MOS Device Models . 28 2.4.1 MOS Device Layout. 28 2.4.2. MOS Device Capacitances 29 2.4.3 MOS Small-Signal Model . 33 2.4.4 MOS SPICE models... 36 2.4.5 NMOS versus PMOS Devices . EL 2.4.6 Long-Channel versus Short-Channel Devices 38xvi Contents Single-Stage Amplifiers . 47 3.1 Basic Concepts .. 47 3.2 Common-Source Stage 48 3.2.1 Common-Source Stage with Resistive Load, 48 3.2.2 CS Stage with Diode-Connected Load . ae 3.2.3. CS Stage with Current-Source Load. 58 3.2.4 CS Stage with Triode Load . 59 3.2.5 CS Stage with Source Degeneration. . 60 3.3. Source Follower. 67 3.4 Common-Gate Stage 76 3.5 Cascode Stage .... 83 3.5.1 Folded Cascode . 90 3.6 Choice of Device Models 2 Differential Amplifiers . . 4.1 Single-Ended and Differential Operation. 4.2 Basic Differential Pair . - 103 4.2.1 Qualitative Analysis » 104 4.2.2 Quantitative Analysis . 107 4.3 Common-Mode Response A118 44 Differential Pair with MOS Loads. ae 45 Gilbert Cell. Passive and Active Current Mirrors . . 135 5.1 Basic Current Mirrors . 135 5.2 Cascode Current Mirrors . . 139 5.3 Active Current Mirrors. . 145 - 149 — » 51 5.3.3 Common-Mode Properties .........6..0.00e0cesseeeeeeeeeeeeeeee, 154 Frequency Response of Amplifiers... 166 6.1 General Considerations - 6.1.1 Miller Effect. . . 166 6.1.2. Association of Poles with Nodes . 169 6.2 Common-Soutce Stage .. - 172 6.3 Source Followers... . 178 6.4 Common-Gate Stage . 183 65 Cascode Stage + 185 6.6 Differential Pair. . 187 Appendix A: Dual of Miller's Theorem. - 193Contents. 7 Noise.. 7.1 Statistical Characteristics of Noise 7.1.1 Noise Spectrum... 7.1.2 Amplitude Distribution 7.1.3 Correlated and Uncorrelated Sources 7.2. Types of Noise... 7.2.1 Thermal Noise... 7.2.2 Flicker Noise . 7.3. Representation of Noise in Circuits 74 Noise in Single-Stage Amplifiers 7.4.1 Common-Source Stage . 7.4.2. Common-Gate Stage. 7.43 Source Followers... 7.44 Cascode Stage 75. Noise in Differential Pai 7.6 Noise Bandwidth 8 Feedback... 8.1 General Considerations 8.1.1 Properties of Feedback Circuits. 8.1.2 Types of Amplifiers. : 5 . : 8.2 Feedback Topologies ...... A 258 8.2.1 Voltage-Voltage Feedback 258 8.2.2 Current-Voltage Feedback... 263 8.2.3. Voltage-Current Feedback. . 8.2.4 Current-Current Feedback, 8.3 Effect of Loading .. 270 8.3.1. Two-Port Network Models . . 270 8.3.2 Loading in Voltage-Voltage Feedback 2m 3. Loading in Curremt-Voltage Feedback ... 215 8.3.4 Loading in Voltage-Current Feedback 28 8.3.5 Loading in Current-Current Feedback 281 8.3.6 Summary of Loading Effects 283 8.4 Effect of Feedback on Noise. . 284 9 Operational Amplifiers 291 9.1 General Considerations . = 291 9.1.1 Performance Parameters 291 9.2 One-Stage Op Amps. 296 9.3" Two-Stage Op Amps . 307 9.4 Gain Boosting . 309 9.5 Comparison . 313 9.6 Common-Mode Feedback 314xviii 10 i 12 13 Contents 9.7 Input Range Limitations . 9.8 Slew Rate... 9.9 Power Supply Rejection .. 9.10. Noise in Op Amps ..... Stability and Frequency Compensation 10.1, General Considerations . 10.2 Multipole Systems ... 10.3. Phase Margin 10.4 Frequency Compensation . 10.5 Compensation of Two-Stage Op Amps . 10.5.1 Slewing in Two-Stage Op Amps 10.6 Other Compensation Techniques. Bandgap References . 11,1 General Considerations . 11.2 Supply-Independent Biasing 11.3 Temperature-Independent References 11.3.1 Negative-TC Voltage .2. Positive-TC Voltage . 3.3 Bandgap Reference. 114 PTAT Current Generation . 11.5 Constant-G,, Biasing . 11.6 Speed and Noise Issues . 11.7 Case Study .... Introduction to Switched-Capacitor Circuits 12.1 General Considerations . 12.2 Sampling Switches . 12.2.1 MOSFETS as Switches 12.2.2 Speed Considerations 12.2.3 Precision Considerations. 12.2.4. Charge Injection Cancellation .... 12.3 Switched-Capacitor Amplifiers ....... 12.3.1 Unity-Gain Sampler/Buffer 12.3.2 Noninverting Amplifier 12.3.3 Precision Multiply-by-Two Circuit 12.4 Switched-Capacitor Integrator . 12.5. Switched-Capacitor Common-Mode Feedback Nonlinearity and Mismatch 13.1 Nonlinearity .. 13.1.1 General Considerations ..........-.-+-22222222e2202eeeeteees : . 325 . 326 . 334 - 336 345 . 349 - 351 - 355 . 361 . 368 . 369 . 377 . 377 .377 381 . 381 - 382 » 384 - 390 + 392 » 393 . 397 - 405 . 410 . 410 - 414 - 417 . 421 - 423 424 . 432 ++ 438 - 439 442Contents 14 15 16 xix 13.1.2 Nonlinearity of Differential Circuits. 452 13.1.3 Effect of Negative Feedback on Nonlinearity 454 13.1.4 Capacitor Nonlinearity . . 457 13.1.5 Linearization Techniques . 458 13.2 Mismatch 463 13.2.1, Offset Cancellation Techniques... . : 13.2.2. Reduction of Noise by Offset Cancellation. 13.2.3 Alternative Definition of CMRR 47 476 - 478 Oscillators... 14.1 General Considerations 14.2 Ring Oscillators..... 482 484 14.3. LC Oscillators .. 495 14.3.1. Crossed-Coupled Oscillator 499 14.3.2 Colpitts Oscillator. . 502 14.3.3. One-Port Oscillators. 505 14.4 Voltage-Controlled Oscillators 510 14.4.1. Tuning in Ring Oscillators . . 512 14.4.2 Tuning in LC Oscillators 14.5 Mathematical Model of VCOs.. Phase-Locked Loop: . 532 15.1 Simple PLL . . 532 15.1.1 Phase Detector. 532 15.1.2 Basic PLL Topology - 533 15.1.3 Dynamics of Simple PLL ~ 542 15.2 Charge-Pump PLLs .. . 549 15.2.1 Problem of Lock Acquisition. . 549 15.2.2. Phase/Frequency Detector and Charge Pump. - 550 15.2.3 Basic Charge-Pump PLL. 556 15.3. Nonideal Effects in PLLs . - 562 15.3.1 PFD/CP Nonidealities . . 562 15.3.2 Jitter in PLLs . +. 567 15.4 Delay-Locked Loops . - 569 15.5. Applications . 572 15.5.1 Frequency Multiplication and Synthesis . . 52 15.5.2. Skew Reduction 574 15.5.3. Jitter Reduction. . 516 Short-Channel Effects and Device Models. . 579 16.1 Scaling Theory .... 579 16.2. Short-Channel Effects - 58317 18 Contents 16.2.1 Threshold Voltage Variation... 16.2.2 Mobility Degradation with Vertical Field . 16.2.3. Velocity Saturation........ : 16.2.4 Hot Carrier Effects 16.2.5 Output Impedance Variation with Drain-Source Voltage. 16.3 MOS Device Models . 589 591 592 593 595 596 Bod 163.1 BSIM Series. Other Models Charge and Capacitance Modeling . ‘Temperature Dependence 16.4 Process Comers... CMOS Processing Technology 17.1 General Considerations ...... 17.2. Wafer Processing ......... 173. Photolithography 17.4 Oxidation ...... 175 Ton Implantation 17.6 Deposition and Etching 17.7 Device Fabrication 17.7.1 Active Devices... 17.7.2 Passive Devices 17.7.3 Interconnects 17.8 Latch-Up... Layout and Packaging 18.1 General Layout Considerations 18.1.1 Design Rules... 18.1.2 Antenna Effect. 18.2. Analog Layout Techniques 18.2.1. Multifinger Transistors 18.2.2 Symmetry... 18.2.3 Reference Distribution. 18.2.4 Passive Devices .. 18.2.5. Interconnects 18.3. Substrate Coupling. . . 634 635 653 Index. .Chapter 1 Introduction to Analog Design 1.1 Why Analog? It was in the early 1980s that many experts predicted the demise of analog circuits. Digital signal processing algorithms were becoming increasingly more powerful while advances in integrated-circuit (IC) technology provided compact, efficient implementation of these algorithms in silicon. Many functions that had traditionally been realized in analog form were now easily performed in the digital domain, suggesting that, with enough capability in IC fabrication, all processing of signals would eventually occur digitally. The future looked quite bleak to analog designers and they were seeking other jobs. But, why are analog designers in such great demand today? After all, digital signal processing and IC technologies have advanced tremendously since the early 1980s, making it possible to realize processors containing millions of transistors and performing billions of operations per second. Why did this progress not confirm the earlier predictions? While many types of signal processing have indeed moved to the digital domain, analog circuits have proved fundamentally necessary in many of today’s complex, high- performance systems. Let us consider a few applications where it is very difficult or even impossible to replace analog functions with their digital counterparts regardless of advances in technology. Processing of Natural Signals Naturally occurring signals are analog—at least at a macroscopic level. A high-quality microphone picking up the sound of an orchestra gener- ates a voltage whose amplitude may vary from a few microvolts to hundreds of millivolts. The photocells in a video camera produce a current that is as low as a few electrons per microsecond. A seismographic sensor has an output voltage ranging from a few microvolts for very small vibrations of the earth to hundreds of millivolts for heavy earthquakes. Since all of these signals must eventually undergo extensive processing in the digital domain, we observe that each of these systems consists of an analog-to-digital converter (ADC) and a digital signal processor (DSP) (Fig. 1.1(a)]. The design of ADCs for high speed, high precision, and low power dissipation is one of many difficult challenges in analog design. In practice, the electrical version of natural signals may be prohibitively small for direct, digitization by the ADC. The signals are also often accompanied by unwanted, out-of-band 1Chap. 1 Introduction to Analog Design Amplifier WWD EEE] @) Figure 1.1 (a) Digitization of a natural signal, (b) addition of amplifica- tion and filtering for higher sensitivity 0 1 1 0 son0 eeeo interferers. The front end of Fig. 1.1(a) may therefore be modified as shown in Fig. 1.1(b), where an amplifier boosts the signal level and an analog filter suppresses the out-of-band components. The design of high-performance amplifiers and filters is also a topic of active research today. Digital Communications Binary data generated by various systems must often be transmitted over long distances. For example, computer networks in large office buildings may transmit the data over cables that are hundreds of meters long. ‘What happens if a high-speed stream of binary data travels through a long cable? As illustrated in Fig. 1.2, the signal experiences both attenuation and “distortion,” no longer re- sembling a digital waveform. Thus, a receiver similar to that of Fig. 1.1(b) may be necessary here. Lossy Cable Vine — Vout "JU UU LIL You SINS Figure 1.2 Attentustion and distor- tion of data through a lossy cable. In order to improve the quality of communication, the above system may incorporate “multi-level”—rather than binary—signals. For example, if, as shown in Fig. 1.3, every two consecutive bits in the sequence are grouped and converted to one of four levels, thenSec. 1.1 Why Analog? 3 Binary Data 4Level Data en t Figure 1.3 Use of multi-level signalling to reduce the re- quired bandwidth. each level is twice as long as a bit period, demanding only half the bandwidth required for transmission of the binary stream. Utilized extensively in today’s communication systems, multi-level signals necessitate a digital-to-analog converter (DAC) in the transmitter to pro- duce multiple levels from the grouped binary data and an ADC in the receiver to determine which level has been transmitted. The key point here is that increasing the number of levels relaxes the bandwidth requirements while demanding a higher precision in the DAC and the ADC. Disk Drive Electronics The data stored magnetically on a computer hard disk is in binary form. However, when the data is read by a magnetic head and converted to an electrical signal, the result appears as shown in Fig. 1.4. The amplitude is only a few millivolts, the noise content is quite high, and the bits experience substantial distortion. Stored Data Figure 1.4 Data stored in and retrieved from a hard disk. ‘Thus, as illustrated in Fig. 1.1, the signal is amplified, filtered, and digitized for further processing. Depending on the overall system architecture, the analog filter in this case may in fact serve to remove a significant portion of the noise and the distortion of the signal. The design of each of these building blocks poses great chiallenges as the speed of computers and their storage media continues to increase every year. For example, today’s disk drives require a speed of 500 Mb/s, Wireless Receivers The signal picked up by the antenna of a radio-frequency (RF) receiver, e.g., a pager or a cellular telephone, exhibits an amplitude of only a few microvolts and a center frequency of 1 GHz or higher. Furthermore, the signal is accompanied by largeChap. 1 Introduction to Analog Design Interferers Desired Signal Figure 1.5 Signal and interferers re- ceived by the antenna of a wireless fy f receiver. interferers (Fig. 1.5). The receiver must therefore amplify the low-level signal with minimal noise, operate at a high frequency, and withstand large unwanted components. Note that these requirements are necessary even if the desired signal is not in “analog” form. The trade-offs between noise, frequency of operation, tolerance of interferers, power dissipation, and cost constitute the principal challenge in today’s wireless industry. Optical Receivers Fortransmission of high-speed data over very long distances, cables generally prove inadequate because of their limited bandwidth and considerable attenuation. Thus, as illustrated in Fig. 1.6, the data is converted to light by means of a laser diode and transmitted over an optical fiber, which exhibits an extremely wide band and a very low Optical Fiber pe fe] Laser Diode Photodiode Figure 1.6 Optical fiber system, loss. At the receive end, the light is converted to a small electrical current by a photodiode. The receiver must then process a low-level signal at a very high speed, requiring low-noise, broadband circuit design. For example, state-of-the-art optical receivers operate in the range of 10 to 40 Gbis. Sensors Mechanical, electrical, and optical sensors play a critical role in our lives. For example, video cameras incorporate an array of photodiodes to convert an image to current and ultrasound systems use an acoustic sensor tb generate a voltage proportional to the amplitude of the ultrasound waveform, Amplification, filtering, and A/D conversion are essential functions in these applications. An interesting example of sensors is the accelerometers employed in automobiles to activate air bags. When the vehicle hits an obstacle, the drop in the speed is measured as acceleration and, if exceeding a certain threshold, it triggers the air bag release mechanism. Modern accelerometers are based on a variable capacitor consisting of a fixed plate and a deflectable plate [Fig. 1.7(a)]. The deflection and hence the value of the capacitor are proportional to the acceleration, requiring a circuit that accurately measures the change in capacitance. The design of such interface circuits is quite difficult because for typicalSec. 1.1 Why Analog? 5 Fixed C, — Deflectable C, C Plate / Plate dee Insulator @) b) Figure 1.7 (a) Simple accelerometer, (b) differential accelerometer. accelerations, the interplate capacitance may change by less than 1%, demanding a high precision in the measurement. In practice, the structure of Fig, 1.7(b) is used to provide two capacitors that change in opposite directions, reducing the task to the measurement of the difference between two capacitances rather than the absolute value of one, Microprocessors and Memo ‘Today's microprocessors and memories draw upon a great deal of analog design expertise. Many issues related to the distribution and timing of data and clocks across a large chip or among chips mandate that high-speed signals be viewed as analog waveforms. Furthermore, nonidealities in signal and power interconnects on the chip as well as package parasitics require a solid understanding of analog design. In addition, semiconductor memories émploy high-speed “sense amplifiers” extensively, necessitating many analog techniques. For these reasons, itis often said “high-speed digital design is in fact analog design.” The foregoing applications demonstrate the wide and inevitable spread of analog circuits inmodern industry. But, why is analog design difficult? We make the following observations, (1) Whereas digital circuits entail primarily one trade-off between speed and power dissipa- tion, analog design must deal with a multi-dimensional trade-off consisting of speed, power dissipation, gain, precision, supply voltage, etc. (2) With the speed and precision required in processing analog signals, analog circuits are much more sensitive to noise, crosstalk, and other interferers than are digital circuits. (3) Second-order effects in devices influence the performance of analog circuits much more heavily than that of digital circuits. (4) The design of high-performance analog circuits can rarely be automated, usually requiring that every device be “hand-crafted.” By contrast, many digital circuits are automatically syn- thesized and laid out, (5) Despite tremendous progress, modeling and simulation of many effects in analog circuits continue to pose difficulties, forcing the designers to draw upon experience and intuition when analyzing the results of a simulation. (6) An important thrust in today’s semiconductor industry is to design analog circuits in mainstream IC technolo gies used to fabricate digital products. Developed and characterized for digital applications,6 Chap. 1 Introduction to Analog Design such technologies do not easily lend themselves to analog design, requiring novel circuits and architectures to achieve a high performance, 1.2 Why Integrated? The idea of placing multiple electronic devices on the same substrate was conceived in the late 1950s. In 40 years, the technology has evolved from producing simple chips containing a handful of components to fabricating memories accommodating more than one billion transistors as well as microprocessors comprising more than 10 million devices. As Gordon Moore (one of the founders of Intel) predicted in the early 1970s, the number of transistors per chip has continued to double approximately every one and a half years. At the same time, the minimum dimension of transistors has dropped from about 25 jzm in 1960 to about 0.18 zm in the year 2000, resulting in a tremendous improvement in the speed of integrated circuits, Driven by primarily the memory and microprocessor market, integrated-circuit tech- nologies have also embraced analog design extensively, affording a complexity, speed, and precision that would be impossible to achieve using discrete implementations. Analog and mixed analog/digital integrated circuits containing tens of thousands of devices now rou- tinely appear in consumer products. We can no longer build a discrete prototype to predict the behavior and performance of modern analog circuits. 1.3 Why CMOS? The idea of metal-oxide-silicon field-effect transistors (MOSFETs) was patented by J. E. Lilienfeld in the early 1930s—well before the invention of the bipolar transistor. Owing to fabrication limitations, however, MOS technologies became practical much later, in the early 1960s, with the first several generations producing only n-type transistors. It was in the mid-1960s that complementary MOS (CMOS) devices (i.e., both n-type and p-type transistors) were introduced, initiating a revolution in the semiconductor industry. CMOS technologies rapidly captured the digital market: CMOS gates dissipated power only during switching and required very few devices, two attributes in sharp contrast to their bipolar or GaAs counterparts. It was also soon discovered that the dimensions of MOS devices could be scaled down more easily than those of other types of transistors, Furthermore, CMOS circuits proved to have a lower fabrication cost. The next obvious step was to apply CMOS technology to analog design. The low cost of fabrication and the possibility of placing both analog and digital circuits on the same chip 80 as to improve the overall performance and/or reduce the cost of packaging made CMOS technology attractive, However, MOSFETs were quite slower and noisier than bipolar tran- sistors, finding limited application, How did CMOS technology come to dominate the analog market as well? The principal force was device scaling because it continued to improve the speed of MOSFETs. The intrinsic speed of MOS transistors has increased by more than three orders of magnitude in the past 30 years, becoming comparable with that of bipolar devices even though the latterSec. 1.4 Why This Book? 7 have also been scaled (but not as fast). Multi-gigahertz, analog CMOS circuits are now in production. 1.4 Why This Book? The design of analog circuits itself has evolved together with the technology and the per- formance requirements. As the device dimensions shrink, the supply voltage of integrated circuits drops, and analog and digital circuits are fabricated on one chip, many design issues arise that were unimportant only a decade ago. Such trends demand that the analysis and design of circuits be accompanied by an in-depth understanding of their advantages and disadvantages with respect to new technology-imposed limitations. Good analog design requires intuition, rigor, and creativity. As analog designers, we must wear our engineer's hat for a quick and intuitive understanding of a large circuit, our ‘mathematician’s hat for quantifying subtle, yet important effects in a circuit, and our artist's hat for inventing new circuit topologies. This book describes modern analog design from both intuitive and rigorous angles. It also fosters the reader's creativity by carefully guiding him/her through the evolution of each circuit and presenting the thought process that occurs during the development of new cireuit techniques. 1.5 General Concepts 1.5.1 Levels of Abstraction Analysis and design of integrated circuits often require thinking at various levels of ab- straction. Depending on the effect or quantity of interest, we may study a complex circuit at device physics level, transistor level, architecture level, or system level. In other words, we may consider the behavior of individual devices in terms of their internal electric fields and charge transport [Fig. 1.8(a)], the interaction of a group of devices according to their electrical characteristics [Fig. 1.8(b)], the function of several building blocks operating as a unit [Fig. 1.8(¢)], or the performance of the system in terms of that of its constituent subsystems [Fig. 1.8(d)]. Switching between levels of abstraction becomes necessary in both understanding the details of the operation and optimizing the overall performance. In fact, in today’s IC industry, the interaction between all groups, from device physicists to system designers, is essential to achieving a high performance and a low cost. In this book, wwe begin with device physics and develop increasingly more complex circuit topologies. 1.5.2 Robust Analog Design Many device and circuit parameters vary with the fabrication process, supply voltage, and ambient temperature. We denote these effects by PVT and design circuits such that their performance remains in an acceptable range for a specified range of PVT variations. For example, the supply voltage may vary from 2.7 V to 3.3 V and the temperature from 0° to 70°. Robust analog design in CMOS technology is a challenging task because device Parameters vary significantly from wafer to wafer.Chap. 1 Introduction to Analog Design Device Circuit @ © Architecture t od © @ Figure 1.8 Abstraction levels in circuit design: (a) device level, (b) citcuit level, (c) architecture level, (@ system level. 1.5.3 Notations ‘The voltages and currents in integrated circuits typically contain a bias component and a signal component. While it is desirable to employ a notation that distinguishes between these quantities, in practice other difficulties arise. For example, if the drain bias current of a transistor is denoted by Ip and the drain signal current by ip, then the Laplace transform of ip, [p(s), may be confused with Ip unless it is always accompanied by s. Furthermore, it is confusing to write the low-frequency gain of a circuit as Uous/vin = —&mRp and the high-frequency gain as Vous/Vin = —&mRo/(1 + RoC1s). Tin this book, we denote most voltages and currents by uppercase letters, making it clear from the context which component they represent. For example, Ip, Vas, and Vx denote bias, signal, or bias+signal quantities. For input and output voltages, we use Vin and Vouts respectively.Chapter 2 Basic MOS Device Physics In studying the design of integrated circuits, one of two extreme approaches can be taken: (2) begin with quantum mechanics and understand solid-state physics, semiconductor device physics, device modeling, and finally the design of circuits; (2) treat each semiconductor device as a black box whose behavior is described in terms of its terminal voltages and currents and design circuits with little attention to the internal operation of the device. Experience shows that neither approach is optimum, In the first case, the reader cannot see the relevance of all of the physics to designing circuits, and in the second, he/she is constantly mystified by the contents of the black box. In today’s IC industry, a solid understanding of semiconductor devices is essential, more so in analog design than in digital design because in the former, transistors are not considered as simple switches and many of their second-order effects directly im- pact the performance. Furthermore, as each new generation of IC technologies scales the devices, these effects become more significant. Since the designer must often decide which effects can be neglected in a given circuit, insight into device operation proves invaluable, In this chapter, we study the physics of MOSFETs at an elementary level, covering the bare minimum that is necessary for basic analog design. The ultimate goal is still to develop a circuit model for each device by formulating its operation, but this is ac- complished with a good understanding of the underlying principles. After studying many analog circuits in Chapters 3 through 13 and gaining motivation for a deeper understanding of devices, we return to the subject in Chapter 16 and deal with other aspects of MOS operation, We begin our study with the structure of MOS transistors and derive their V/V char- acteristics. Next, we describe second-order effects such as body effect, channel-length modulation, and subthreshold conduction. We then identify the parasitic capacitances of MOSFETs, derive a small-signal model, and present a simple SPICE model. We as- sume that the reader is familiar with such basic concepts as doping, mobility, and pn junctions.10 Chap.2 Basic MOS Device Physics 2.1 General Considerations 2.1.1 MOSFET as a Switch Before delving into the actual operation of the MOSFET, we consider a simplistic model of the device so as to gain a feeling for what the transistor is expected to be and which aspects of its behavior are important. ‘Shown in Fig. 2.1 is the symbol for an n-type MOSFET, revealing three terminals: gate (G), source (S), and drain (D). The latter two are interchangeable because the device is Gate He Figure 2.1 Simple view of a MOS Source s—¥ L—. prain device. symmetric. When operating as a switch, the transistor “connects” the source and the drain together if the gate voltage, Vo, is “high” and isolates the source and the drain if Va is “low.” Even with this simplified view, we must answer several questions. For what value of Vg does the device turn on? In other words, what is the “threshold” voltage? What is the resistance between S and D when the device is on (or off)? How does this resistance depend on the terminal voltages? Can we always model the path between S and D by a simple linear resistor? What limits the speed of the device? While all of these questions arise at the circuit level, they can be answered only by analyzing the structure and physics of the transistor. 2.1.2 MOSFET Structure Fig. 2.2 shows a simplified structure of an n-type MOS (NMOS) device. Fabricated on a p-type substrate (also called the “bulk” or the “body”), the device consists of two heavily- doped n regions forming the source and drain terminals, a heavily-doped (conductive) piece G Poly D Oxide Figure 2.2. Structure of a MOS device.Sec. 2.1 General Considerations " of polysilicon! (often simply called “poly”) operating as the gate, and a thin layer of silicon dioxide (SiO) insulating the gate from the substrate. The useful action of the device occurs in the substrate region under the gate oxide, Note that the structure is symmetric with respect to Sand D. The dimension of the gate along the source-drain path is called the length, L, and that perpendicular to the length is called the width, W. Since during fabrication the $/D junc- tions “side-diffuse.” the actual distance between the source and the drain is slightly less than L. To avoid confusion, we write, Les = Larawn — 2L.p, where Lers is the “effective” length, Léraun is the total length,? and Lp is the amount of side diffusion. As we will see later, Lery and the gate oxide thickness, t.., play an important role in the performance of MOS circuits. Consequently, the principal thrust in MOS technology development is to reduce both of these dimensions from one generation to the next without degrading other Parameters of the device. Typical values at the time of this writing are Ley * 0.15 xm and fox © 50 A. In the remainder of this book, we denote the effective length by L. If the MOS structure is symmetric, why do we call one n region the source and the other the drain? This becomes clear if the source is defined as the terminal that provides the charge carriers (electrons in the case of NMOS devices) and the drain as the terminal that collects them. Thus, as the voltages at the three terminals of the device vary, the source and the drain may exchange roles. These concepts are practiced in the problems at the end of the chapter. We have thus far ignored the substrate on which the device is fabricated. In reality, the substrate potential greatly influences the device characteristics. That is, the MOSFET is a four-terminal device. Since in typical MOS operation the $/D junction diodes must be reverse-biased, we assume the substrate of NMOS transistors is connected to the most negative supply in the system. For example, if a circuit operates between zero and 3 volts, Veub.waos = 0. The actual connection is usually provided through an ohmic p* region, as. depicted in the side view of the device in Fig. 2.3. p-substrate igure 2.3 Substrate connection. In complementary MOS (CMOS) technologies, both NMOS and PMOS transistors are available. From a simplistic view point, the PMOS device is obtained by negating all of 'Polysilicon is silicon in amorphous (non-crystal) form. As explained in Chapter 17, when the gate silicon is ‘grown on top of the oxide, it cannot form a crystal. 2 The subscript “drawn” is used because this is the dimension that we draw in the layout of the transistor (Section 2.4.1).12 Chap.2 Basic MOS Device Physics n-substrate @) p-substrate (b) Figure 2.4 (a) Simple PMOS device, (b) PMOS inside an n-well. the doping types (including the substrate) [Fig. 2.4(a)], but in practice, NMOS and PMOS devices must be fabricated on the same wafer, ie, the same substrate. For this reason, one device type can be placed in a “local substrate,” usually called a “well.” In most of today’s CMOS processes, the PMOS device is fabricated in an n-well [Fig. 2.4(b)]. Note that the n-well must be connected to a potential such that the S/D junction diodes of the PMOS transistor remain reverse-biased under all conditions. In most circuits, the n-well is tied to the most positive supply voltage. For the sake of brevity, we sometimes call NMOS and PMOS devices “NFETs” and “PFETs,” respectively. Fig. 2.4) indicates an interesting difference between NMOS and PMOS transistors: while all NFETs share the same substrate, each PFET can have an independent n-well. This flexibility of PFETs is exploited in some analog circuits. 2.1.3 MOS Symbols The circuit symbols used to represent NMOS and PMOS transistors are shown in Fig. 2.5. The symbols in Fig. 2.5(a) contain all four terminals, with the substrate denoted by “B” (bulk) rather than “S” to avoid confusion with the source. The source of the PMOS device is positioned on top as a visual aid because it has a higher potential than its gate. Since in most circuits the bulk terminals of NMOS and PMOS devices are tied to ground and Vpp, respectively, we usually omit these connections in drawing [Fig. 2.5(b)]. In digital circuits, itis customary to use the “switch” symbols depicted in Fig. 2.5(c) for the two types, but we prefer those in Fig. 2.5(b) because the visual distinction between S and D proves helpful in understanding the operation of circuits.Sec.2.2 MOS I/V Characteristics 13 NMOS PMos NMos PMOS NMos PMOs D s D s D D Go Go—]| Goer « = s D s D 8 8 @ o © Figure 2.5 MOS symbols. 2.2 MOS IV Characteristics Inthis section, we analyze the generation and transport of charge in MOSFET as a function of the terminal voltages. Our objective is to derive equations for the I/V characteristics such that we can elevate our abstraction from device physics level to circuit level. 2.2.1 Threshold Voltage Consider an NFET connected to external voltages as shown in Fig. 2.6(a). What happens as the gate voltage, Vg, increases from zero? Since the gate and the substrate form a capacitor, 40.1V Eu in 0 py Figure 2.6 (a) A MOSFET driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion, (d) formation » of inversion layer,14 Chap.2 Basic MOS Device Physics as Vq becomes more positive, the holes in the p-substrate are repelled from the gate area, leaving negative ions behind so as to mirror the charge on the gate. In other words, a depletion region is created [Fig. 2.6(b)]. Under this condition, no current flows because no charge carriers are available. As Ve increases, so do the width of the depletion region and the potential at the oxide- silicon interface. In a sense, the structure resembles two capacitors in series: the gate oxide capacitor and the depletion region capacitor [Fig. 2.6(c)]. When the interface potential teaches a sufficiently positive value, electrons flow from the source to the interface and eventually to the drain. Thus, a “channel” of charge carriers is formed under the gate oxide between S and D, and the transistor is “turned on.” We also say the interface is “inverted.” The value of Vg for which this occurs is called the “threshold voltage,” Vri. If Vo rises further, the charge in the depletion region remains relatively constant while the channel charge density continues to increase, providing a greater current from S to D. In reality, the turn-on phenomenon is a gradual function of the gate voltage, making it difficult to define Vrj unambiguously. In semiconductor physics, the Vrx of an NFET is usually defined as the gate voltage for which the interface is “as much n-type as the substrate is p-type.” It can be proved [1] that? Day Vr = ys +20¢ + (2.1) where ®ys is the difference between the work functions of the polysilicon gate and the silicon substrate, ®- = (kT/q)In(Nyup/m:), q is electron charge, Nrub is the doping con- centration of the substrate, Qzep is the charge in the depletion region, and Cyr is the gate oxide capacitance per unit area. From pn junction theory, Ozep = /4q€il PF Newby Where €si denotes the dielectric constant of silicon. Since C., appears very frequently in device and circuit calculations, it is helpful to remember that for for * 50 A, Coy © 6.9 fF/pum2, The value of C,, can then be scaled proportionally for other oxide thicknesses. In practice, the “native” threshold value obtained from the above equation may not be suited to circuit design, ¢.g., Vr = 0 and the device does not tum off for V¢ > 0. For this reason, the threshold voltage is typically adjusted by implantation of dopants into the channel area during device fabrication, in essence altering the doping level of the substrate near the oxide interface. For example, as shown in Fig. 2.7, if a thin sheet of p* is created, the gate voltage required to deplete this region increases. ee p-substrate Figure 2.7 Implantation of p* dopants to alter the threshold. ‘The above definition isnot directly applicable tothe measurement of Vr.In Fig. 2.62), only the drain current can indicate whether the device is “on” or “off,” thus failing to reveal at what Vas the interface is as much n-type as the bulk is p-type. As aesult, the calculationSeo.2.2 MOS IV Characteristics 15 of Vr from I/V measurements is somewhat ambiguous. We return to this point later but assume in our preliminary analysis that the device turns on abruptly for Ves = Vr. ‘The turn-on phenomenon in a PMOS device is similar to that of NFETs but with all of the polarities reversed. As shown in Fig. 2.8, ifthe gate-source voltage becomes sufficiently Va n-substrate Holes -01V Figure 2.8 Formation of inversion layer in a PFET. negative, an inversion layer consisting of holes is formed at the oxide- providing a conduction path between the source and the drain. 2.2.2 Derivation of I/V Characteristics In order to obtain the relationship between the drain current of a MOSFET and its terminal voltages, we make two observations. First, consider a semiconductor bar carrying a current / (Fig. 2.9(a)]. Ifthe charge density along the direction of current is Q4 coulombs per meter and the velocity of the charge is v meters per second, then 1=Qa-v. (2.2) To understand why, we measure the total charge that passes through a cross section of the bar in unit time. With a velocity v, all of the charge enclosed in v meters of the bar must flow through the cross section in one second [Fig. 2.9(b)]. Since the charge density is Qu, the total charge in v meters equals Qy--v. This lemma proves useful in analyzing semiconductor devices. V meters > = | I e » ‘One second later @ @) Figure 2.9 (a) A semiconductor bar carrying a current 1, (b) snapshots of the carriers one second apart.Chap.2 Basic MOS Device Physics Figure 2.10 Channel charge with (a) equal source and drain voltages, (b) unequal source and drain voltages. Second, consider an NFET whose source and drain are connected to ground [Fig. 2.10(a)]. What is the charge density in the inversion layer? Since we assume the onset of inversion occurs at Vos = Vriv the inversion charge density produced by the gate oxide capacitance is proportional to Ves — Vr. For Ves > Vru, any charge placed on the gate must be mirrored by the charge in the channel, yielding a uniform channel charge density (charge per unit length) equal to Qu = WCox(Ves — Vru) (2.3) where Co. is multiplied by W to represent the total capacitance per unit length, Now suppose, as depicted in Fig. 2.10(b), the drain voltage is greater than zero. Since the channel potential varies from zero at the source to Vp at the drain, the local voltage difference between the gate and the channel varies from Vg to Vg — Vp. Thus, the charge density at a point x along the channel can be written as Qa(x) = WCorLVes — VX) — Vr), (2.4) where V(x) is the channel potential at x. From (2.2), the current is given by Ip = —WCorlVas — V(x) ~ Vrulv, 2.5)Sec. 2.2 MOS IV Characteristics 17 where the negative sign is inserted because the charge carriers are negative and v denotes the velocity of the electrons in the channel. For semiconductors, v = 1E, where yt is the mobility of charge carriers and E is the electric field. Noting that E(x) = —dV/dx and representing the mobility of electrons by j1,, we have aV(x) dx” subject to boundary conditions V(0) = 0 and V(L) = Vps. While V(x) can be easily found from this equation, the quantity of interest is in fact Jp. Multiplying both sides by dV and performing integration, we obtain Tp = WCoxL Ves — V(x) — Vrultn (2.6) L Vos [ Indx = f WCorttnlVes — V(x) — VrnldV. Qn rao v0 Since Jp is constant along the channel: (2.8) Ww 1 Io = bnCor [eves ~VrwVos — 5s] Note that L is the effective channel length. Triode Region Vos Figure 2.11 Drain current versus drain-source voltage in the triode region Ves ~ Vu Voso-Vrw Voss Vu Fig. 2.11 plots the parabolas given by (2.8) for different values of Vos, indicating that the “current capability” of the device increases with Vs. Calculating 3 /Vps, the reader can show that the peak of each parabola occurs at Vps = Ves — Vr and the peak current is 1 Ww Tmax = 5HnCox—(Ves — Vr). 2.9) Ds ghnC TS ‘es — Vrn)’ (2.9) ‘We call Ves — Vru the “overdrive voltage and W/L the “aspect ratio.” If Vps < Vos — Vr. we say the device operates in the “triode region.”> “Sometimes called the “effective voltage.” SThis is also called the “linear region.”18 Chap.2 Basic MOS Device Physics Equations (2.8) and (2.9) serve as the foundation for analog CMOS design, describing the dependence of Zp upon the constant of the technology, 12,Cox, the device dimensions, W and L, and the gate and drain potentials with respect to the source. Note that the integration in (2.7) assumes jt» and Vry are independent of x and the gate and drain voltages, an approximation that we will revisit in Chapter 16. If in (2.8), Vos « 2(Vas — Vr), we have w Ip © UnCox Wes — Ven Vos, (2.10) that is, the drain current is a linear function of Vps. This is also evident from the character- istics of Fig. 2.11 for small Vps: as shown in Fig, 2.12, each parabola can be approximated by a straight line. The linear relationship implies that the path from the source to the drain can be represented by a linear resistor equal to 1 Ron = . (11 WwW UnCos (Vos — Vr) A MOSFET can therefore operate as a resistor whose value is controlled by the overdrive voltage [so long as Vps < 2(Ves ~ Vru)}. This is conceptually illustrated in Fig. 2.13, Note that in contrast to bipolar transistors, a MOS device may be on even if it carries no Figure 2.12 Linear operation in deep triode region. G 1 Vas s-4L.ip > —{. D Figure 2.13 MOSFET asacontrolled linear resistor. Current. With the condition Vos < 2(Vas~ Vr), we say the device operates in deep triode region. Example 2.1 For the arrangement in Fig. 2.14(a), plot the on-resistance of My as a function of Vg. Assume HnCox = 50 HAIV?, W/L = 10, and Vr = 0.7 V. Note that the drain terminal is open,Sec, 2.2 MOS IV Characteristics 19 Figure 2.14 Solution Since the drain terminal is open, Ip = 0 and Vps = 0. Thus, if the device is on, it operates in the deep triode region. For Vg < 1 V + Wri, M1 is off and Ron = 00. For Vg > 1 V + Vr, we have i * 50 uA/V? x 10(Ve 1 V—0.7 Vy" a Ron ‘The result is plotted in Fig. 2.14(b). ‘The utility of MOSFETs as controllable resistors and hence switches plays a crucial role in many analog circuits. This is studied in Chapter 12. What happens if in Fig. 2.11 the drain-source voltage exceeds Vos — Vrir? In reality, the drain current does not follow the parabolic behavior for Vos > Vas — Vra. In fact, as shown in Fig. 2.15, Zp becomes relatively constant and we say the device operates in the “saturation” region.° To understand this phenomenon, recall from (2.4) that the local Saturation Region Figure 2.15 Saturation of drain current, Note the difference between saturation in bipolar and MOS devices.20 Chap.2 Basic MOS Device Physics Ve Vps2> Yost V(x4) = Vas—Vrw V(x2) = Veg-VrH Figure 2.16 Pinch-off behavior. density of inversion layer charge is proportional to Ves — V(x) — Vru. Thus, if V(x) approaches Ves — Vra, then Q4(x) drops to zero. In other words, as depicted in Fig. 2.16, if Vps is slightly greater than Vos — Vr, then the inversion layer stops at x < L, and we say the channel is “pinched off” As Vps increases further, the point at which Q, equals zero gradually moves toward the source. Thus, at some point along the channel, the local potential difference between the gate and the oxide-silicon interface is not sufficient to support an inversion layer. With the above observations, we re-examine (2.7) for a saturated device. Since Qg is the density of mobile charge, the integral on the left-hand side of (2.7) must be taken from x = Otox = L’, where L’ is the point at which Q4 drops to zero, and that on the right from V(x) = 010 V(x) = Vos — Vr. As a result: 1 Ww Tp = 5HtnConZ;(Vas — Vr) (2.13) indicating that Ip is relatively independent of Vps if L’ remains close to L. For PMOS devices, Eqs. (2.8) and (2.13) are respectively written as w lie Ip = ~MtpCoxz | (Vos — Vr Vos ~ 3Vbs (2.14) and 1 Ww Ip = ~5H4pCox p (Vas — Ven). 2.15) ‘The negative sign appears here because we assume Ip flows from the drain to the source, whereas holes flow in-the reverse direction. Since the mobility of holes is about one-half to one-fourth of the mobility of electrons, PMOS devices suffer from lower “current drive” capability.Sec. 2.2 MOS W/V Characteristics 21 Yoo Yoo 1 “e > & wt ‘> f. L Figure 2.17 Saturated MOSFETs operating as current sources. With the approximation L ~ L’, a saturated MOSFET can be used as a current source connected between the drain and the source (Fig. 2.17), an important component in analog design, Note that the current sources inject current into ground or draw current from Vp. In other words, only one terminal of each current source is “floating.” Since a MOSFET operating in saturation produces a current in response to its gate- source overdrive voltage, we may define a figure of merit that indicates how well a device converts a voltage to a current. More specifically, since in processing signals we deal with the changes in voltages and currents, we define the figure of merit as the change in the drain current divided by the change in the gate-source voltage. Called the “transconductance” and denoted by gm, this quantity is expressed as: alp a 2.16) Bm BV vos cot er) w = MnCox7-(Vos — Vr). 2.17) Ina sense, gm represents the sensitivity of the device: for a high gm, a small change in Ves results in a large change in Ip. Interestingly, gm in the saturation region is equal to the inverse of Ron in deep triode region, The reader can prove that gm can also be expressed as, Ww ‘m inCox (2. 8 2UnCox Io (2.18) 2p =. (2.19) = Ves — Vrn Plotted in Fig. 2.18, each of the above expressions proves useful in studying the behavior Of gm asa function of one parameter while other parameters remain constant. For example, (2.17) suggests that gm increases with the overdrive if W/L is constant whereas (2.19) im- plies that gn decreases with the overdrive if p is constant. The concept of transconductanceChap.2 Basic MOS Device Physics Im Im Im t _ a NN — Ves Vr Ip Vas- Vn W/L Constant ‘WIL Constant 'p Constant Figure 2.18 MOS transconductance as a function of overdrive and drain current. can also be applied to a device operating in the triode region, as illustrated in the following example. Example 2.2 For the arrangement shown in Fig. 2.19, plot the transconductance as a function of Vos. Mo~ Vin Yos Figure 2.19 Solution It is simpler to study gm a8 Vps decreases from infinity. So long as Vps > Vb — Vrx, M1 is in saturation, Ip is relatively constant, and, from (2.18), 50 i8 gm. For Vos < Vo — Vr, My isin the triode region and: _ 3 ~ 8Ves (2! Ww fn tiCox" [2V05 ~ Vrad¥os ~ VBs]]} 2.20) = tnCox Vos em Thus, as plotted in Fig, 2.19, the transconductance drops if the device enters the triode region. For amplification, therefore, we usually employ MOSFETs in saturation. The distinction between saturation and triode regions can be confusing, especially for PMOS devices: Intuitively, we note that the channel is pinched off if the difference between the gate and drain voltages is not sufficient to create an inversion layer. As depicted concep- tually in Fig. 2.20, as Vg — Vp of an NFET drops below Vr, pinch-off occurs. Similarly,Sec. 2.3 Second-Order Effects 23 Saturation Edge of Triode Region Saturation Edge of Triode Region + sdold oli wep od $ - [Mine @ o Figure 2.20 Conceptual visualization of saturation and triode regions. if Vp — Vg of a PFET is not large enough (< |Vrizp|), the device is saturated. Note that this view does not require knowledge of the source voltage. This means we must know a priori which terminal operates as the drain. 2.3 Second-Order Effects Our analysis of the MOS structure has thus far entailed various simplifying assumptions, some of which are not valid in many analog circuits. In this section, we describe three second-order effects that are essential in our subsequent circuit analyses. Other phenomena that appear in submicron devices are studied in Chapter 16. Body Effect In the analysis of Fig. 2.10, we tacitly assumed that the bulk and the source of the transistor were tied to ground. What happens if the bulk voltage of an NFET drops below the source voltage (Fig. 2.21)? Since the S and D junctions remain reverse-biased, wwe surmise that the device continues to operate properly but certain characteristics may vey p-substrate OF vp<0 Figure 2.21 NMOS device with negative bulk voltage. change. To understand the effect, suppose Vs = Vp = 0, and Vg is somewhat less than Vr 80 that a depletion region is formed under the gate but no inversion layer exists. As Vp becomes more negative, more holes are attracted to the substrate connection, leaving a larger negative charge behind, i.e., as depicted in Fig. 2.22, the depletion region becomes wider, Now recall from Eq. (2.1) that the threshold voltage is a function of the total charge in the depletion region because the gate charge must mirror Q, before an inversion layer is24 Chap.2 Basic MOS Device Physics Vg<0 a p-substrate Q p-substrate Figure 2.22 Variation of depletion region charge with bulk voltage. formed. Thus, as Vz drops and Q, increases, Vr also increases. This is called the “body effect” or the “backgate effect.” Itcan be proved that with body effect: Ven = Vrno+y (V2@e + Vee! — VBOri) 2.22) where Vryo is given by (2.1), y = /2qeiNran/Cox denotes the body effect coefficient, and Vsp is the source-bulk potential difference [1]. The value of y typically lies in the range of 0.3 00.4 V1, Example 2.3 In Fig. 2.23(a), plot the drain current if Vy. varies from —co to 0. Assume Vryo = 0.6 V, VIP, and 2 = 0.7 V. Vit OK (b) Figure 2.23 Solution If Vx is sufficiently negative, the threshold voltage of M; exceeds 1.2 V and the device is off. That is, 12V=06 +04 (Y0.7= Vii - vO7), 223)Sec.2.3 Second-Order Effects 25 and hence Vx1 = 4.76 V. For V1 < Vx <0, Ip increases according to In = AuaCoxe [Vas — Ven —y (V2 7 — Va - vaer)y 224) Fig. 2.23(b) shows the resulting behavior. For body effect to manifest itself, the bulk potential, V,,2, need not change: if the source voltage varies with respect to Vzy2, the same phenomenon occurs. For example, consider the cireuit in Fig. 2.24(a), first ignoring body effect. We note that as Vin varies, Vou closely follows the input because the drain current remains equal to /,. In fact, we can write 7 1, = 5 laCox Vin ~ Vous ~ Ven? (2.28) concluding that Vi, — Vour is constant if J; is constant [Fig. 2.24(b)]. () fo) Figure 2.24 (a) A circuit in which the source-bulk voltage varies with input level, (b) input and output voltages with no body effect, (c) input and output voltages with body effect. Now suppose the substrate is tied to ground and body effect is significant. Then, as Vin and hence Voy become more positive, the potential difference between the source and the bulk increases, raising the value of Vr. Eq. (2.25) therefore implies that Vig — Vour must increase so as to maintain [p constant (Fig. 2.24(c)]. Body effect is usually undesirable. The change in the threshold voltage, e.g., as in Fig. 2.24(a), often complicates the design of analog (and even digital) circuits. Device technologists balance N,,» and Co. to obtain a reasonable value for y- Channel-Length Modulation In the analysis of channel pinch-off in Section 2.2, we noted that the actual length of the inverted channel gradually decreases as the potential difference between the gate and the drain increases. In other words, in (2.13), L’ is in fact a function of Vps. This effect is called “channel-length modulation.” Writing L’ — AL, ie., 1/L' * (1 + AL/L)/L, and assuming a first-order relationship between AL/L and Vps.such as AL/L = AVps, we have, in saturation, 1 Ww Tn © 5 HnCox Wass ~ Vr + 2V ps). (2.26)26 Chap.2 Basic MOS Device Physics Figure 2.25 Finite saturation region slope resulting from channel-length modulation. where 2 is the channel-length modulation coefficient. Illustrated in Fig. 2.25, this phe- nomenon results in a nonzero slope in the Ip/Vps characteristic and hence a nonideal current source between D and S in saturation. The parameter A represents the relative variation in length for a given increment in Vps. Thus, for longer channels, 2 is smaller. With channel-length modulation, some of the expressions derived for gm must be mod- ified. Equations (2.17) and (2.18) are respectively rewritten as Ww 8m = MnCox (Vas — Val + AVps)- (2.27) 2nCox(W/L)Ip (2.28) 1+AVps while Eq. (2.19) remains unchanged. ‘Enna 24 eee Keeping all other parameters constant, plot Ip/Vps characteristic of a MOSFET for L = Ly and La. Solution © Writing = bd ZHnCox Was — Vru +2¥ps) (2.29) Ib= and A 0 1/L, we note that ifthe length is doubled, the slope of Ip vs. Vp is divided by four because 81p/8Vps & A/L « 1/L? (Fig. 2.26). For a given gate-source overdrive, a larger L gives a more Figure 2.26 Effect of doubling chan- Vos nel length. ideal current source while degrading the current capability of the device. Thus, W may need to be increased proportionally. eeSec.2.3 Second-Order Effects 27 ‘The linear approximation AL/L « Vps becomes less accurate in short-channel transis- tors, resulting in a variable slope in the saturated Ip/Vps characteristics. We return to this issue in Chapter 16. The dependence of Ip upon Vps in saturation may suggest that the bias current of a MOSFET can be defined by the proper choice of the drain-source voltage, allowing freedom in the choice of Vgs — Vr. However, since the dependence on Vps is much weaker, the drain-source voltage is not used to set the current. The effect of Vps on Ip is usually considered an error and itis studied in Chapter 5. Subthreshold Conduction _ In our analysis of the MOSFET, we have assumed that the device turns off abruptly as Ves drops below Vry. In reality, for Vos © Vr, a “weak” inversion layer still exists and some current flows from D to S. Even for Ves < Vr, Ip is finite, but it exhibits an exponential dependence on Ves (2, 3}. Called “subthreshold conduction,” this effect can be formulated for Vps greater than roughly 200 mV as, Vas = =, (2.30) Ip = Inexp [Vr (2.30) where £ > 1 is a nonideality factor and Vr = kT'/q. We also say the device operates in “week inversion.” Except for £, (2.30) is similar to the exponential [c/Vge relationship in a bipolar transistor. The key point here is that as Ves falls below Vry, the drain current drops at a finite rate. With typical values of £, at room temperature Ves must decrease by approximately 80 mV for Ip to decrease by one decade (Fig. 2.27). For example, if a ‘Square Law ‘09/07 exponential a Ss; Figure 2.27 MOS subthreshold char- somvy) | Mtn Vos acteristics. threshold of 0.3 V is chosen in a process to allow low-voltage operation, then when Ves is reduced to zero, the drain current decreases by only a factor of 10°”5. Especially problematic in large circuits such as memories, subthreshold conduction can result in significant power dissipation (or loss of analog information). It is appropriate at this point to return to the definition of the threshold voltage. One definition is to plot the inverse on-resistance of the device R;;! = 1Cox(W/L\(Ves — Vru) as a function of Vos and extrapolate the result to zero, for which Ves = Vru. In rough calculations, we often view Vry as the gate-source voltage yielding Ip/W = 1A/um in saturation, For example, if a device with W = 100 jum operates with Jp = 100 2A, it is in the vicinity of the subthreshold region. This view is nonetheless vague, especially as device length scales down in every technology generation.28 Chap.2 Basic MOS Device Physics We now re-examine Eq. (2.18) for the transconductance of a MOS device operating in the subthreshold region. Is it possible to achieve an arbitrarily high transconductance by increasing W while maintaining Jp constant? Is it possible to obtain a higher transconduc- tance than that of a bipolar transistor ([c/ Vr) biased at the same current? Equation (2.18) was derived from the square-law characteristics Ip = (1/2)f4nCox(W/L)(Vos — Vru)*. However, if W increases while Jp remains constant, then Vas + Vru and the device enters the subthreshold region. As a result, the transconductance is calculated from (2.30) to be 8m = Ip/(f Vr), revealing that MOSFETs are inferior to bipolar transistors in this respect. ‘The exponential dependence of Zp upon Vgs in subthreshold operation may suggest the use of MOS devices in this regime so as to achieve a higher gain. However, since such conditions are met by only a large device width or low drain current, the speed of subthreshold circuits is severely limited. Voltage Limitations MOSFETs experience various breakdown effects if their terminal voltage differences exceed certain limits. Athigh gate-source voltages, the gate oxide breaks down irreversibly, damaging the transistor. In short-channel devices, an excessively large drain-source voltage widens the depletion region around the drain so much that it touches that around the source, creating a very large drain current. (This effect is called “punchthrough.”) Other limitations relate to “hot electron effects” and are described in Chapter 16. 2.4 MOS Device Models 2.4.1 MOS Device Layout For the developments in subsequent sections, itis beneficial to have some understanding of the layout of a MOSFET. We describe only a simple view here, deferring the fabrication details and structural subtleties to Chapters 17 and 18. The layout of a MOSFET is determined by both the electrical properties required of the device in the circuit and the “design rules” imposed by the technology. For example, W/L is chosen to set the transconductance or other circuit parameters, while the minimum L is dictated by the process. In addition to the gate, the source and drain areas must be defined properly as well. Shown in Fig. 2.28 are the “bird eye's view” and the top view of a MOSFET. The gate polysilicon and the source and drain terminals are typically tied to metal (aluminum) wires that serve as interconnects with low resistance and capacitance. To accomplish this, one or more “contact windows” must be opened in each region, filled with metal, and connected to the upper metal wires. Note that the gate poly extends beyond the channel area by some amount to ensure reliable definition of the “edge” of the transistor. ‘The source and drain junctions play an important role in the performance. To minimize the capacitance of S and D, the total area of each junction must be minimized. We see from Fig. 2.28 that one dimension of the junctions is equal to W. The other dimension must be large enough to accommodate the contact windows and is specified by the technology design rules.” ‘This dimension is typically three to four times the minimum allowable channel length.Sec.2.4 MOS Device Models 29 Channel Area w| Contact Windows aw Leen @ ® Figure 2.28 Bird's eye and vertical views of a MOS device. Example 2.5 Draw the layout of the circuit shown in Fig. 2.29(a). E F E_ Aluminum Ao—bhm, aa MM, Gs Ms aaa Bom, N @ () © Figure 2.29 Solution Noting that Mfy and Mp share the same S/D junctions at node C and Mz and M3 also do so at node NY, we surmise that the three transistors can be laid out as shown in Fig. 2.29(b). Connecting the remaining terminals, we obtain the layout in Fig. 2.29(c). Note that the gate polysilicon of Ms cannot be directly tied to the source material of M1, thus requiring a metal interconnect. 2.4.2 MOS Device Capacitances The basic quadratic IV relationships derived in the previous section along with corrections for body effect and channel-length modulation provide a reasonable model for understand ing the “de” behavior of CMOS circuits. In many analog circuits, however, the capacitances yb associated with the devices must also be taken into account so as to predict the “ac” behavior : as well.Chap.2 Basic MOS Device Physics D Can | oa F 1 G poB Ly He Cos Csp E Con s Figure 2.30 MOS capacitances. ‘We expect that a capacitance exists between every two of the four terminals of a MOSFET (Fig. 2.30). Moreover, the value of each of these capacitances may depend on the bias con- ditions of the transistor. Considering the physical structure in Fig. 2.31(a), we identify the following. (1) Oxide capacitance between the gate and the channel, C) = WLCox; (2) De~ pletion capacitance between the channel and the substrate, Cr = WL/GéiNuw/(@Or)s (3) Capacitance due to the overlap of the gate poly with the source and drain areas, C3 and Cs. Owing to fringing electric field lines, C3 and C, cannot be simply written as WL pCox, and are usually obtained by more elaborate calculations. The overlap capacitance per unit width is denoted by Cy; (4) Junction capacitance between the source/drain areas and the substrate, As shown in Fig. 2.31(b), this capacitance is usually decomposed into two compo- nents; bottom-plate capacitance associated with the bottom of the junction, C, and sidewall capacitance due to the perimeter of the junction, Cj... The distinction is necessary because different transistor geometries yield different area and perimeter values for the S/D junctions. We typically specify C; and C js as capacitance per unit area and unit length, respectively. Note that each junction capacitance can be expressed as C; = Cjo/[1 + Ve/®a)", where Vp is the reverse voltage across the junction, ®g is the junction built-in potential, and m is a power typically in the range of 0.3 and 0.4. "The capacitance between S and D is negligible. 3 Tee Inversion Depletion *, p-substrate Layer Layer zo, Ciew @) ©) Figure 2.31 (a) MOS device capacitances, (b) decomposition of S/D junction capacitance into bottom-plate and sidewall components.Bec. 2.4 MOS Device Models 31 Example 2.6 Calculate the source and drain junction capacitances of the two structures shown in Fig. 2.32. Drain Terminal Source a Terminal 1 cy an —bd5> (a) (b) Figure 2.32 Solution For the transistor in Fig. 2.32(a), we have Cop = Csp = WEC] +2W + E)Cjsw, (231) whereas for that in Fig. 2.32(b), Ww Coa= Fee; 42(F +2) Cw (232) Ww Csp =a Fac, +2(F +2) ‘ne (233) = WEC; +2(W +2E)Cjow (234) Called a “folded” structure, the geometry in Fig. 2.32(b) exhibits substantially less drain junction capacitance than that in Fig. 2.32(a) while providing the same W/L. In the above calaculations, we have assumed that the total source or drain perimeter, 2(W + E), is multiplied by Cs. In reality, the capacitance of the sidewall facing the channel may be less than that of the other three sidewalls because of the channel-stop implant (Chapter 17). Nonetheless, we typically assume all four sides have the same unit capacitance. The error resulting from this assumption is negligible because each node in a circuit is connected to a number of other device capacitances as, well32 Chap.2 Basic MOS Device Physics 2WLCox+WCov ‘> 2WLCoxt WC. Woes Wey Triode “ot = Vas Figure 2.33 Variation of gate-source and gate-drain capacitances versus Vos. ‘We now derive the capacitances between terminals of a MOSFET in different regions of operation. If the device is off, Cop = Cas = Coy W, and the gate-bulk capacitance consists of the series combination of the gate oxide capacitance and the depletion region capac- itance, ie., Cos = (WLCox)Cu/(WLCox + Ca), where L is the effective length and Ca = WL GesiNewo/(@®;). The value of Csp and Cpp is a function of the source and drain voltages with respect to the substrate. If the device is in deep triode region, i.e., if S and D have approximately equal volt- ages, then the gate-channel capacitance, WLCyz, is divided equally between the gate and source terminals and the gate and drain terminals. This is because a change AV in the gate voltage draws equal amounts of charge from S and D. Thus, Cen = Cos = WLC o_/2 + WCoy. If in saturation, a MOSFET exhibits a gate-drain capacitance of roughly WC,y. The potential difference between the gate and the channel varies from Vas at the source to Ves — Vrn at the pinch-off point, resulting in a nonuniform vertical electric field in the gate oxide along the channel. It can be proved that the equivalent capacitance of this structure excluding the gate-source overlap capacitance equals 2W LCox/3 [1]. Thus, Cas = 2WLeypCox/3-+ W Cop. The behavior of Cgp and C¢s in different regions of opera- tion is plotted in Fig. 2.33. Note that the above equations do not provide a smooth transition from one region of operation to another, creating convergence difficulties in simulation programs. This issue is revisited in Chapter 16. The gate-bulk capacitance is usually neglected in the triode and saturation regions be- cause the inversion layer acts as a “shield” between the gate and the bulk. In other words, if the gate voltage varies, the charge is supplied by the source and the drain rather than the bulk. Example 2.7 Sketch the capacitances of M; in Fig. 2.34 as Vx varies from zero to 3 V. Assume Viz = 0.6 V and A=y=0. Solution To avoid confusion, we label the three terminals as shown in Fig. 2.34. For Vx ~ 0, Mi is in the triode region, Ce © Cer = (1/2)WLCox + WCov, and Crp is maximum, The value of Cwa is independent of Vx. As Vx exceeds 1 V, the role of the source and drain is exchanged [Fig. 2.35(a)],Sec. 2.4 MOS Device Models 33 = Figure2.34 2WLCox+ WCov}-~ Wi Gor. Woy WCov-~ 14 VW) (a) (b) Figure 2.35 eventually bringing M; out ofthe triode region for Vx > 2.V— 0.6 V. The variation of the capacitances is plotted in Figs. 2.35(b) and (c). 2.4.3 MOS Small-Signal Model ‘The quadratic characteristics described by (2.8) and (2.9) along with the voltage-dependent capacitances derived above form the large-signal model of MOSFETs. Such a model proves essential in analyzing circuits in which the signal significantly disturbs the bias points, particularly if nonlinear effects are of concern. By contrast, if the perturbation in bias conditions is small, a small-signal model, i.c., an approximation of the large-signal model around the operating point, can be employed to simplify the calculations. Since in many analog circuits, MOSFETs are biased in the saturation region, we derive the corresponding small-signal model here. For transistors operating as switches, a linear resistor given by (2.11) together with device capacitances serves as a rough small-signal equivalent. We derive the small-signal model by producing a small increment in a bias point and calculating the resulting increment in other bias parameters. Since the drain current is a function of the gate-source voltage, we incorporate a voltage-dependent current source equal to gm Vas [Fig. 2.36(a)]. Note that the low-frequency impedance between G and Sis very high. This is the small-signal model of an ideal MOSFET. Owing to channel-length modulation, the drain current also varies with the drain-source voltage. This effect can also be modeled by a voltage-dependent current source [Fig.2.36(b)], but a current source whose value linearly depends on the voltage across it is equivalent toChap.2 Basic MOS Device Physics Go—_ D Go—>— oD Ss s @ (b) Go—_ oD es Ves Ve + © @ Figure 2.36 (a) Basic MOS small-signal model, (b) channel-length modulation represented by a dependent current source, (c) channel-length modulation represented by a resistor, (d) body effect represented by a dependent current source. a linear resistor [Fig. 2.36(c)]. Tied between D and S, the resistor is given by _ aVps o= ap (2.35) —— (2.36) = alp/aVps" : 1 => 237) I W a 4 Co Wes — , qlnCox las — Vrny +h E (2.38) ay ‘As seen throughout this book, the outpat resistance, ro, impacts the performance of many analog cireuits. For example, ro limits the maximum voltage gain of most amplifiers. Now recall that the bulk potential influences the threshold voltage and hence the gate~ source overdrive. As demonstrated in Example 2.3, with all other terminals held at a constant voltage, the drain current is a function of the bulk voltage. That is, the bulk behaves as a second gate. Modeling this dependence by a current source connected between D and S [Fig, 2.36(4)], we write the value as gnoVbs, Where 8m = 81p/8Vas. In the saturation region, gmp can be expressed as: alp ny = ee 2. 8nd = Fy 55 (239)Sec.2.4 MOS Device Models 35 w aVrn = Un Cor —(Ves — . 2.44 HnCor (Vos ew ( we) (2.40) We also have OVrn 8Vrn Vas OVse @an = 00, + Vs8)", (2.42) Thus, fmb = Bn ee (2.43) 2/20¢ + Vee = 18m: (2.44) where 1 = gnb/8m- As expected, gmp is proportional to y. Equation (2.43) also suggests that incremental body effect becomes less pronounced as Vsp increases. Note that gm Vos and gmsVas have the same polarity, i., raising the gate voltage has the same effect as raising the bulk potential. The model in Fig. 2.36(d) is adequate for most low-frequency small-signal analyses. In reality, each terminal of a MOSFET exhibits finite ohmic resistance resulting from the resis- tivity of the material (and the contacts), but proper layout can minimize such resistances, For example, consider the two structures of Fig. 2.32, repeated in Fig. 2.37 along with the gate distributed resistance. We note that folding reduces the gate resistance by a factor of four. es : Figure 2.37 Reduction of gate resis- (@) () tance by folding. Shown in Fig. 2.38, the complete small-signal model includes the device capacitances as well. The value of each capacitance is calculated according to the equations derived in Section 2.4.2. The reader may wonder how a complex circuit is analyzed intuitively if each transistor must be replaced by the model of Fig. 2.38. The first step is to determineChap.2 Basic MOS Device Physics Figure 2.38 Complete MOS small-signal model. the simplest device model that can represent the role of each transistor with reasonable accuracy. We provide some guidelines for this task at the end of Chapter 3. Exar 2.8 ame Sketch gm and gms of Mi in Fig. 2.39 as a function of the bias current I. 9m, 9mb © Figure 2.39 Solution Since gm = J2inCox(W7L)Ip, we have gm « «Tj. The dependence of gmp upon 1; is less straightforward. As J; increases, Vx decreases and so does Vp. ———— Unless otherwise stated, in this book we assume the bulk of all NFETS is tied to the most negative supply (usually the ground) and that of PFET to the most positive supply (usually Vp). 2.4.4 MOS SPICE models In order to represent the behavior of transistors in circuit simulations, SPICE requires an accurate model for each device. Over the last two decades, MOS modeling has made tremendous progress, reaching quite sophisticated levels so as to represent high-order effects in short-channel devices.Sec.2.4 MOS Device Models 37 Table 2.1 Level 1 SPICE Models for NMOS and PMOS Devices. NMOS Model VT0=0.7 PHI=09 LD =0.08e-6 LAMBDA = 0.1 TOX=90-9 PB=09 CJSW = 0350-11 MJ = 0.45 MISW = 0.2 JS = 1.0e-8 PMOS Model LEVEL vTo = -08 PHI=08 LD = 0.09e-6 LAMBDA PB=09 CSW = 0.320-11 MISW =03 In this section, we describe the simplest MOS SPICE model, known as “Level 1,” and provide typical values for each parameter in the model corresponding to a 0.5-jum tech- nology. Chapter 16 describes more accurate SPICE models. Table 2.1 shows the model parameters for NMOS and PMOS devices. The parameters are defined as below: VTO: threshold voltage with zero Vs (unit: V) GAMMA: body effect coefficient (unit: V'/) PHI: 2 (unit: V) ‘TOX: gate oxide thickness (unit: m) NSUB: substrate doping (unit: cm~*) LD: source/drain side diffusion (unit: m) UO: channel mobility (unit: em?/V/s) LAMBDA: channel-length modulation coefficient (unit: V-") CE: source/drain bottom-plate junction capacitance per unit area (unit: F/m?) CISW: source/drain sidewall junction capacitance per unit length (unit: F/m) PB: source/drain junction built-in potential (unit: V) ‘MB: exponent in CI equation (unitless) ‘MISW: exponent in CJSW equation (unitless) CGDO: gate-drain overlap capacitance per unit width (unit: F/m) CGSO: gate-source overlap capacitance per unit width (unit: F/m) JS: source/drain leakage current per unit area (unit: A/m?) 2.4.5 NMOS versus PMOS Devices In most CMOS technologies, PMOS devices are quite inferior to NMOS transistors. For example, due to the lower mobility of holes, {1pCox * 0.25}nCox in modem processes, yielding low current drive and transconductance. Moreover, for given dimensions and bias currents, NMOS transistors exhibit a higher output resistance, providing more ideal current sources and higher gain in amplifiers. For these reasons, itis preferred to incorporate NFETS rather than PFETs wherever possible.Chap.2 Basic MOS Device Physics 2.4.6 Long-Channel versus Short-Channel Devices In this chapter, we have employed a very simple view of MOSFETs so as to understand the basic principles of their operation. Most of our treatment is valid for “long-channel” devices, e.g., transistors having a minimum length of about 4 zm, Many of the relationships derived here must be reexamined and revised for short-channel MOSFETS. Furthermore, the SPICE models necessary for simulation of today's devices need to be much more sophis- ticated than the Level 1 model, For example, the intrinsic gain, gro, calculated from the device parameters in Table 2.1 is quite higher than actual values. These issues are studied in Chapter 16, The reader may wonder why we begin with a simplistic view of devices if such a view does not lead to a high accuracy in predicting the performance of circuits. The key point is that the simple model provides a great deal of intuition that is necessary in analog design. As ‘we will see throughout this book, we often encounter a trade-off between intuition and rigor, and our approach is to establish the intuition first and gradually complete our understanding 80 as to achieve rigor as well. Appendix A: Behavior of MOS Device as a Capacitor In this chapter, we have limited our treatment of MOS devices to a basic level. However, the behavior of a MOSFET as a capacitor merits some attention. Recall that if the source, drain, and bulk of an NFET are grounded and the gate voltage rises, an inversion layer begins to form for Ves © Via. We also noted that for 0 < Vos < Vriz the device operates in the subthreshold region. Now consider the NFET of Fig. 2.40. The transistor-can be considered a two-terminal Vq<0 Figure 2.40 NMOS operating in ac- cumulation mode. device and hence its capacitance can be examined for different gate voltages. Let us be- gin with a very negative gate-source voltage. The negative potential on the gate attracts the holes in the substrate to the oxide interface. We say the MOSFET operates in the “accumulation” region. The two-terminal device can be viewed as a capacitor having a unit-area capacitance of Co; because the two “plates” of the capacitor are separated by fox. As Vos rises, the density of holes at the interface falls, a depletion region begins to form under the oxide, and the device enters weak inversion, In this mode, the capacitance consists of the series combination of C,, and Cyep. Finally, as Ves exceeds Vr, the oxide-silicon interface sustains a channel and the unit-area capacitance returns to Coy. Figure 2.41 plots the behavior.Problems. 39 Accumulation Strong Inversion ron Ves Figure 2.41 Capacitance-voltage characteristic of an NMOS device. Unless otherwise stated, in the following problems, use the device data shown in Table 2. and assume Vp = 3 V where necessary. 2d. 2.2. 23. 24. 25. For W/L = 50/0.5, plot the drain current of an NFET and a PFET as a function of |V¢s| as Ves| vaties from 0 to 3 V. Assume |Vns| = 3 V. For W/L = 50/05, and |p| = 0.5 mA, calculate the transconductance and output impedance of both NMOS and PMOS devices. Also, find the “intrinsic gain,” defined as gnro. Derive expressions for gmro in terms of Ip and W/L. Plot gmro as a function of Ip with L as a parameter. Note that 4. 1/L. Plot Ip versus Ves for an MOS transistor (a) with Vps as a parameter, (b) with Vag as a parameter, Identify the break points in the characteristics. ‘Sketch and the transconductance of the transistor as a function of Vx for each circuit in ig. 2.42 as Vx varies from 0 to Vpp. For part (a), assume Vx varies from 0 to 1.5 V. Figure 2.42Chap.2 Basic MOS Device Physics Yoo Yoo Ry Ix Ry Ix My My Re Re On On @ © Ix My 42 + Vy Ry hy Vy @ Figure 2.43 2.6, Sketch Ix and the transconductance of the transistor as a function of Vx for each circuit in Fig. 2.43 as Vx varies from 0 to Vpp. 2.7. Sketch Vous as a function of Viy for each circuit in Fig. 2.44 as Vin varies from 0 to Vpp. 2.8, Sketch Vous as a function of Vin for each circuit in Fig. 2.45 as Vin varies from 0 to Vp. 29, Sketch Vx and Zy as a function of time for each circuit in Fig. 2.46. The initial voltage of C1 is equal to 3 V. 2.10, Sketch Vx and Jy as a function of time for each circuit in Fig. 2.47, The initial voltages of C, and C2 are equal to 1 V and 3 V, respectively. 2L1. Sketch Vx a8 function of time for each circuit in Fig. 2.48. The initial voltage of each capacitor is shown, 2.12, Sketch Vx asa function of time for each circuitin Fig. 2.49. The initial voltage of each capacitor is shown, 2.13. The transit frequency, fr, of a MOSFET is defined as the frequency at which the small-signal current gain of the device drops to unity while the source and drain terminals are held at ac ground. (a) Prove that 8m ft Cap Co) (2.45) Note that fr does not include the effect of the $/D junction capacitance.Problems a @ ©) © Figure 2.45 (b) Suppose the gate resistance, Rg, is significant and the device is modeled as a distributed set of n transistors each with a gate resistance equal to R¢/n. Prove that the fr of the device is independent of Rg and still equal to the value given above. (©) For a given bias current, the minimum allowable drain-source voltage for operation in saturation can be reduced only by increasing the width and hence the capacitances of the transistor. Using square-law characteristics, prove that tin Vos ~ Ven = fe “Gs TE. 2.46 fr= 2.46) This relation indicates how the speed is limited as a device is designed to operate with lower supply voltages.Chap.2 Basic MOS Device Physics Ix Ix vq % My To ) ) Ix Ix VK Mx YWHbM, =c, Yew, Fe a ly @ © Figure 2.46 Ix U3 VK Vx 2V Co 2V. Cy svi, T +2VeE My, Te Te ©) © Figure 2.47 2.14, Calculate the fr of aMOS device in the subthreshold region and compare the result with those obtained in Problem 2.13. 2.15, For a saturated NMOS device having W = 50 um and L = 0.5 um, calculate all of the capacitances. Assume the minimum (lateral) dimension of the $/D areas is 1.5 um and the device is folded as shown in Fig. 2.32(b). What is the fr if the drain current is 1 mA? 2.16. Consider the structure shown in Fig. 2.50. Determine Ip as a function of Vos and Vps and prove that the structure can be viewed as a single transistor having an aspect ratio W/(2L). Assume A= y = 0. 2.17. Foran NMOS device operating in saturation, plot W/L versus Ves — Vr if (a) Ip is constant, () 8m is constant.Problems 43 @ w C hy 2v My © @ Figure 2.48 Figure 2.49Chap.2 Basic MOS Device Physics : L Vos = ~ Figure2.50 2.18. Explain why the structures shown in Fig. 2.51 cannot operate as current sources even though the transistors are in saturation, 4 ! fa) (b) Figure 2.51 2.19. Considering the body effect as “backgate effect,” explain intuitively why y is directly propor- tional to Neb and inversely proportional to Cox 2.20, A “ring” MOS structure is shown in Fig. 2.52. Explain how the device operates and estimate its equivalent aspect ratio. Compare the drain junction capacitance of this structure with that of the devices shown in Fig. 2.32. Gate — w Figure 2.52 2.21. Suppose we have received an NMOS transistor in a package with four unmarked pins. Describe the minimum number of de measurement steps using an ohmmeter necessary to determine the gate, source/drain, and bulk terminals of the device, 2.22, Repeat Problem 2.21 if the type of the device (NFET or PFET) is not known.Problems 2.23, 2.24, 2.25, 2.26. 2.27. 2.28. 45 For an NMOS transistor, the threshold voltage is known but jtnCox and W/L are riot. Assume a 0. If we cannot measure Cox independently, is it possible to devise a sequence of de measurement tests to determine jinCox and W/L? What if we have two transistors and we know one has twice the aspect ratio of the other? Sketch Ix versus Vx for each of the composite structures shown in Fig. 2.53 with Vo as a parameter. Also, sketch the equivalent transconductance. Assume A = y = 0. Figure 2.53 AnNMOS current source with Zp = 0.5 mA must operate with drain-source voltages as low as 0.4 V. If the minimum required output impedance is 20 k®, determine the width and length of the device. Calculate the gate-source, gate-drain, and drain-substrate capacitance if the device is folded as in Fig. 2.32 and E = 3 jum. Consider the circuit shown in Fig. 2.54, where the initial voltage at node X is equal to Vpp. Assuming 4 = y = 0 and neglecting other capacitances, plot Vy and Vy versus time if (a) Vin is a positive step with amplitude Vo > Vr, (b) Vin is a negative step with amplitude Vo = Vrx. Figure 2.54 An NMOS device operating in the subthreshold region has a ¢ of 1.5. What variation in Ves results in a ten-fold change in 1p? If Ip = 10 A, what is gn? Consider an NMOS device with Vg = 1.5 V and Vs = 0. Explain what happens if we continually decrease Vp below zero or increase V,yp above zero.Chap.2 Basic MOS Device Physics . RS, Muller and T. L Kamins, Device Electronics for Integrated Circuits, Second Ed., New York: Wiley, 1986. .Y. Tsividis, Operation and Modeling of the MOS Transistor, Second Ed., Boston: McGraw-Hill, 1999, .Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, New York: Cambridge University Press, 1998.Chapter 3 Single-Stage Amplifiers Amplification is an essential function in most analog (and many digital) circuits. We amplify an analog or digital signal because it may be too small to drive a load, overcome the noise of a subsequent stage, or provide logical levels to a digital circuit. Amplification also plays accritical role in feedback systems (Chapter 8). In this chapter, we study the low-frequency behavior of single-stage CMOS amplifiers. Analyzing both the large-signal and the small-signal characteristics of each circuit, we develop intuitive techniques and models that prove useful in understanding more complex systems, An important part of a designer’s job is to use proper approximations $0 as to create a simple mental picture of a complicated circuit. The intuition thus gained makes it possible to formulate the behavior of most circuits by inspection rather than by lengthy calculations. Following a brief review of basic concepts, we describe in this chapter four types of amplifiers: common-source and common-gate topologies, source followers, and cascode configurations. In each case, we begin with a simple model and gradually add second-order phenomena such as channel-length modulation and body effect. 3.1 Basic Concepts The input-output characteristic of an amplifier is generally a nonlinear function (Fig. 3.1) that can be approximated by a polynomial over some signal range: W(t) © a Fay x(t) + anx7(1) +++ +a,x"C) XS XS G.I) ‘The input and output may be current or voltage quantities, For a sufficiently narrow range ofx, y(t) © a + ox(r), G2) where ao can be considered the operating (bias) point and ar the small-signal gain. So long as x(t) < ao, the bias point is disturbed negligibly, (3.2) provides a reasonable 4748 Chap.3 — Single-Stage Amplifiers Figure 3.1 Input-output characteristic of a nonlinear system. approximation, and higher order terms are insignificant. In other words, Ay = a Ax, indicating a linear relationship between the increments at the input and output. As x(¢) increases in magnitude, higher order terms manifest themselves, leading to nonlinearity and necessitating large-signal analysis. From another point of view, if the slope of the characteristic the incremental gain) varies with the signal level, then the system is nonlinear. These concepts are described in detail in Chapter 13, What aspects of the performance of an amplifier are important? In addition to gain and speed, such parameters as power dissipation, supply voltage, linearity, noise, or maximum voltage swings may be important. Furthermore, the input and output impedances determine how the circuit interacts with preceding and subsequent stages. In practice, most of these parameters trade with each other, making the design a multi-dimensional optimization problem. Illustrated in the “analog design octagon” of Fig. 3.2, such trade-offs present many challenges in the design of high-performance amplifiers, requiring intuition and experience to arrive at an acceptable compromise. Input/Output .. Impedance ‘speed——> 4" ut ‘Swings Figure 3.2 Analog design octagon. 3.2 Common-Source Stage 3.2.1 Common-Source Stage with Resistive Load By virtue of its transconductance, a MOSFET converts variations in its gate-source voltage to a small-signal drain current, which can pass through a resistor to generate an output voltage. Shown in Fig. 3.3(a), the common-source (CS) stage performs such an operation.Common-Source Stage 49 Yoo Ro Vout Vine My @ o) Yoo Ry Vout nV rie Im) =A Yin} Fon + My = © @ Figure 3.3 (a) Common-source stage, (b) input-output characteristic, (c) equivalent circuit in deep triode region, (4) small-signal model for the saturation region. We study both the large-signal and the small-signal behavior of the circuit. Note that the input impedance of the circuit is very high at low frequencies, If the input voltage increases from zero, M1 is off and Vow = Vop [Fig. 3.3(b)]. AS Vin approaches Vr, M; begins to tur on, drawing current from Rp and lowering Vour. If Vop is not excessively low, M; turns on in saturation, and we have Vour = Voo — Rox zHnCon oun —Vruy. 3.3) where channel-length modulation is neglected. With further increase in Vin, Vour drops more and the transistor continues to operate in saturation until Vi, exceeds Vous by Vrw [point A in Fig. 3.3(b)]. At this point, 1 Ww Ven = Voo ~ RoxHnCox (Vint — Ven), G4) from which Vinx — Vr and hence Voy can be calculated. For Vin > Vini, My is in the triode region: 1 Vou = Voo — Roz tnCor [2(Vin — Veet) Vou — V2] - i)Chap.3 Single-Stage Amplifiers If Vin is high enough to drive My into deep triode region, Vous < 2(Vin — Vriz), and, from the equivalent circuit of Fig. 3.3(c), 3.6) Sv G2) T+ Mn Cox Ro(Vin —Vru) Since the transconductance drops in the triode region, we usually ensure that Vow > Vin — Vrn, operating to the left of point A in Fig, 3.3(b). Using (3.3) as the input-output characteristic and viewing its slope as the small-signal gain, we have: Vout ave 8) w = —RotenCos T-(Vin ~ Vru) 3.9) =-&nRo. .10) This result can be directly derived from the observation that Mj converts an input volt- age change AVi, to a drain current change g»,AViq, and hence an output voltage change 8m RoAVin. The small-signal model of Fig. 3.3(d) yields the same result. Even though derived for small-signal operation, the equation Ay = —gmRp predicts certain effects if the circuit senses a large signal swing. Since gq itself varies with the input signal according to gm = -nCox(W/L)(Vos — Vr), the gain of the circuit changes substantially if the signal is large. In other words, if the gain of the circuit varies significantly with the signal swing, then the circuit operates in the large-signal mode. The dependence of the gain upon the signal level leads to nonlinearity (Chapter 13), usually an undesirable effect. A key result here is that to minimize the nonlinearity, the gain equation must be a weak function of signal-dependent parameters such as gm. We present several examples of this concept in this chapter and in Chapter 13. Example 3.1 ee Sketch the drain current and transconductance of M; in Fig. 3.3(a) as a function of the input voltage. Solution ‘The drain current becomes significant for Vin > Vix, eventually approaching Vpp/Rp if Ron < Ro [Fig. 3.4(@)]. Since in saturation, gm = nCor(W/L)(Vin — Vin) the transconductance begins to rise for Vin > Vrw. In the triode region, gm = sinCox(W/L)Vps, falling as Vin exceeds Vint FFig. 3.4()]. How do we maximize the voltage gain of a common-source stage? Writing (3.10) as RD. Ay =~ 2ttnCor Io, 3.1L HnCox Flo GB)Seo. 3.2 Common-Source Stage 51 @ Figure 3.4 where Vep denotes the voltage drop across Rp, we have (3.12) ‘Thus, the magnitude of A, can be increased by increasing W/L or Vap or decreasing Ip if other parameters are constant. It is important to understand the trade-offs resulting from this equation. A larger device size leads to greater device capacitances, and a higher Vap limits the maximum voltage swings. For example, if Vpp — Vap = Vin — Vr. then My is at the edge of the triode region, allowing only very small swings at the output (and input). If Vep remains constant and Jp is reduced, then Rp must increase, thereby leading to a greater time constant at the output node. In other words, as noted in the analog design octagon, the circuit exhibits trade-offs between gain, bandwidth, and voltage swings. Lower supply voltages further tighten these trade-offs, For large values of Rp, the effect of channel length modulation in M; becomes significant, Modifying (3.4) to include this effect, Ww Vou = Vow ~ RostaCox Vin ~ Vee )*U + WV, G13) we have OV our Ww = —RotnCox (Vin — Vr (1 + AVour Tp = —RotinCox Vin = Ven + Vo) 1 w 2, 9Vour Roz teCon 7 Vin ~ Ven PAS, a) Using the approximation Ip ~ (1/2)4nCox(W/L) Vin — Vrx)®, we obtain: A, —Ro8m — RplphAy (3.15)52 Chap.3 —Single-Stage Amplifiers and hence &nRo . (3.16) 1+ Rpilp a Since Alp = I/ro, roRp eeeee eeeee ceeeeee 3.17) Bm ro + Rb eu The small-signal model of Fig. 3.5 gives the same result with much less effort. That is, since Figure 3.5 Small-signal model of CS stage including the transistor output re- sistance. 8mVi(rollRp) = —Vou and Vi = Vin, we have Vow /Vin = —&n(rol| Rp). Note that, as mentioned in Chapter 1, Vin, Vj, and V,,, in this figure denote small-signal quantities. Example 3.2 Assuming My in Fig. 3.6 is biased in saturation, calculate the small-signal voltage gain of the circuit, Figure3.6 Solution ‘Since 1; introduces an infinite impedance, the gain is limited by the output resistance of My Ay = ~8mro. 3.18) Called the “intrinsic gain” of a transistor, this quantity represents the maximum voltage gain that can bbe achieved using a single device. In today's CMOS technology, gmro of short-channel devices is between roughly 10 and 30. Thus, we usually assume 1/m Veni, Eq. (3.30) holds and Voy, follows an approximately straight line. As V;, exceeds Vy, + Vrizi (beyond point A), Mj enters the triode region, and the characteristic becomes nonlinear. ‘The diode-connected load of Fig. 3.9 can be implemented with a PMOS device as well. Shown in Fig. 3.12, the circuit is free from body effect, providing a small-signal voltage gain equal to (W/L) Mp(W/L)2" 2 where channel-length modulation is neglected. Ay56 Chap. 3 Single-Stage Amplifiers @ Figure 3.10 (a) Diode-connected device with stepped bias current, (b) variation of source voltage versus time. Vout A Voo~VrH2 Figure 3.11 input-output characteris- tic of a CS stage with diode-connected load. Vout Vino M, Figure 3.12. CS stage with diode- = connected PMOS device. Equations (3.28) and (3.33) indicate that the gain of a common-source stage with diode- connected load is a relatively weak function of the device dimensions. For example, to achieve a gain of 10, ,(W/L)i/{Hp(W/L)2) = 100, implying that, with 41, © 2j1p, we musthave (W/L), ~ 50(W/L)o. Ina sense, a high gain requires “strong” input device and “weak” load device. In addition to disproportionately wide or long transistors (and hence a large input or load capacitance), a high gain translates to another important limitation: reduction in allowable voltage swings. Specifically, since in Fig. 3.12, Ip1 = [Ial, Ww Ww Hn (¥) (Vest — Vrms)" © Up (Z) (eso — Vriny, (3.34) 1 2Sec.3.2 Common-Source Stage 37 revealing that Wasa — Veil. 4, (3.35) Vos: — Vrui In the above example, the overdrive voltage of Mz must be 10 times that of Mj. For example, with Vs1 — Vri1 = 200 mV, and |Vri2| = 0.7 V, we have |Ves2| = 2.7 V, severely limiting the output swing. This is another example of the trade-offs suggested by the analog design octagon. Note that, with diode-connected loads, the swing is constrained by both the required overdrive voltage and the threshold voltage. That is, even with a small overdrive, the output level cannot exceed Vip — |Vri An interesting paradox arises here if we write gm = Cox(W/L)|Vos — Vri|. The voltage gain of the circuit is then given by A, = 2 (3.36) Bm2 — HnCor(W/L) Vest — Veni) = Batol gs Ta (3.37) UpCox(W/L)a|Ves2 — Vru2l Equation (3.37) implies that A, is inversely proportional to |Vgs2 — Vrw2|- Itis left for the reader to resolve the seemingly opposite trends suggested by (3.35) and (3.37). Example 3.3 —————________ In the circuit of Fig. 3.13, Mj is biased in saturation with a drain current equal tof. The current source fs = 0.75/; is added to the circuit. How is (3.35) modified for this case? Solution Since |/p2| = 11/4, we have Ay 69 SB (3.38) Bn 4ptn(W/L)i (3.39) V pW D2” . Yoo = ts Vout Yn fh My = Figure 3.13Chap.3 —Single-Stage Amplifiers Moreover, w 5 w o He (Z) Wasi — Vein = 4up (5) (Vase ~ Vena). 8.40) Ly 2 yielding Wosa~Vrual . Av em 3.41) Vest — Vran 2 : ‘Thus, for a gain of 10, the overdrive of Mz need be only 2.5 times that of Mj. Alternatively, fora given overdrive voltage, this circuit achieves a gain four times that of the stage in Fig. 3.12. Intuitively, this is because for a given |Vosz ~ Vrna|, if the current decreases by a factor of 4, then (W/L)2 must decrease proportionally, and gm2 = /24pCax(W/L)2Tp2 is lowered by the same factor. ‘We should also mention that in today’s CMOS technology, channel-length modulation is quite significant and, more importantly, the behavior of transistors notably departs from the square law (Chapter 16). Thus, the gain of the stage in Fig. 3.9 must be expressed as, 1 Ay = —8mi (Ztroutros) . (3.42) m2 where gm and gq2 must be obtained as described in Chapter 16, 3.2.3 CS Stage with Current-Source Load In applications requiring a large voltage gain in a ingle stage, the relationship A, = —gmRp suggests that we increase the load impedance of the CS stage. With a resistor or diode- connected load, however, increasing the load resistance limits the output voltage swing. A more practical approach is to replace the load with a current source. Described briefly in Example 3.2, the resulting circuit is shown in Fig. 3.14, where both transistors operate in saturation. Since the total impedance seen at the output node is equal to ro, Iro2, the gain is Yoo YoeE mu, Vout Vinem, Figure 3.14 CS stage with current- source load. —8mi(rorllro2). (3.43) The key point here is that the output impedance and the minimum required |Vps| of ‘Mp are less strongly coupled than the value and voltage drop of a resistor. The voltageSec.3.2 Common-Source Stage 59 [Voszmin| = |Vas2 — Vrnzl can be reduced to even a few hundred millivolts by simply increasing the width of Mz. If ro2 is not sufficiently high, the length and width of Mo can be increased to achieve a smaller 4 while maintaining the same overdrive voltage. The penalty is the large capacitance introduced by Mz at the output node. We should remark that the output bias voltage of the circuit in Fig. 3.14 is not well- defined. Thus, the stage is reliably biased only if a feedback loop forces Voy, to a known value (Chapter 8). The large-signal analysis of the circuit is left as an exercise for the reader. ‘As explained in Chapter 2, the output impedance of MOSFETs at a given drain current can be scaled by changing the channel length, ie., to the first order, 4 o 1/L and hence ro % L/Ip. Since the gain of the stage shown in Fig. 3.14 is proportional to ro1||roz, we may surmise that longer transistors yield a higher voltage gain. Let us consider M; and Mz separately. If Ly is scaled by a factor a (> 1), then W; may need to be scaled proportionally as well. This is because, for a given drain current, Vgsi — Vrai & 1/(W/L)i ie., if W; is not scaled, the overdrive voltage increases, limiting the output voltage swing. Also, since gm x (W/E), scaling up only L; lowers gmi- In applications where these issues are unimportant, W; can remain constant while Ly increases, Thus, the intrinsic gain of the transistor can be written as Ww 1 mi 2 inCos . 3.44) 8miO1 (3), ih (3.44) indicating that the gain increases with L because 1 depends more strongly on L than 8m does. Also, note that gmro decreases as Ip increases. Increasing Lz while keeping W2 constant increases ro2 and hence the voltage gain, but at the cost of higher | Vpso| required to maintain M; in saturation. 3.2.4 CS Stage with Triode Load AMOS device operating in deep triode region behaves as a resistor and can therefore serve as the load in a CS stage. Illustrated in Fig. 3.15, such a circuit biases the gate of Mz at a sufficiently low level, ensuring the load is in deep triode region for all output voltage swings. Yoo Yoo = e Figure3.15 CSstagewith triode load.Chap. 3 Single-Stage Amplifiers Since Ron2 = (3.45) fpCodW]L)Voo — Vo —\Wrnel)” the voltage gain can be readily calculated. ‘The principal drawback of this circuit stems from the dependence of Ron2 UPON pCox, Vo» and Vryp. Since 1 pCox and Vr p vary with process and temperature and since generating a precise value for Vs, requires additional complexity, this circuit is difficult to use. Triode loads, however, consume less voltage headroom then do diode-connected devices because in Fig. 3.15 Voumax = Von whereas in Fig. 3.12, Vou,max © Vo — |Vrupl- 3.2.5 CS Stage with Source Degeneration In some applications, the square-law dependence of the drain current upon the overdrive voltage introduces excessive nonlinearity, making it desirable to “soften” the device charac- teristic. In Section 3,2.2, we noted the linear behavior of a CS stage using a diode-connected load. Alternatively, as depicted in Fig. 3.16, this can be accomplished by placing a “degen- eration” resistor in series with the source terminal. Here, as Vin increases, so do Ip and the Yop 'p Rp + " mM, Vout Vi b Yy IM Vino t Ip Rs Rs (@) ©) Figure 3.16 CS stage with source degeneration, voltage drop across Rs. That is, a fraction of V;,, appears across the resistor rather than as the gate-source overdrive, thus leading to a smoother variation of [p. From another perspective, we intend to make the gain equation a weaker function of gm. Since Vow: = —IpRp, the nonlinearity of the circuit arises from the nonlinear dependence of Ip upon Vin. We note that 8Voue/8Vin = —(81p/8Vin)Rp, and define the equivalent transconductance of the circuit 8 Gy, = 1p /OVin. Now, assuming Ip = f(Vos), we write (3.46) G47)Seo. 3.2 Common-Source Stage 61 Since Ves = Vin — IpRs, we have 9Ves/4Vin = 1 — Rs91p/4Vin, obtaining af A ) Ves oe But, 9/8 Ves is the transconductance of My, and 8m Gn = 22, 3.49) T+ gmRs Gay The small-signal voltage gain is thus equal to GmRp (3.50) =8mRo —_——— 3.51. 1+ amRs Gov The same result can be derived using the small-signal model of Fig. 3.16(b). Equation (3.49) implies that as Rs increases, G,, becomes a weaker function of gm and hence the drain current. In fact, for Rs >> 1/gm, we have Gy * 1/Rs, ie, Alp © AVin/Rs, indicating that most of the change in V;, appears across Rs. We say the drain current is a “linearized” function of the input voltage. The linearization is obtained at the cost of lower gain [and higher noise (Chapter 7)]. Tout — 1 Vin “u @® to D 9moMbs x As Figure 3.17 Small-signal equivalent circuit of a degenerated CS stage. For our subsequent calculations, itis useful to determine G., in the presence of body effect and channel-length modulation. With the aid of the equivalent circuit shown in Fig. 3.17, we recognize that the current through Rs equals Jou; and, therefore, Vin = Vi + lous Rs. Summing the currents at node X, we have Tous R Tout = BmVi ~ BmbVx — (3.52) To Tous R = Bin(Vin — lot Rs) + Bt(—lout Rs) — S. 3.53) It follows that Tous Gee ce (3.54) oe (3.55) ~ RSF Gm + BnodRsIro™Chap.3 Single-Stage Amplifiers Let us now examine the large-signal behavior of the CS stage with Rs = 0 and Rs ¢ 0. For Rs = 0, our derivations in Chapter 2 indicate that p and gq vary as shown in Fig. 3.18(a). For Rs # 0, the tum-on behavior is si Hig. 3.18(a) because, _ _ _ Vn Yin Vow Vin Von Vin @ () Figure 3.18 Drain current and transconductance of a CS device (a) without and (b) with source degeneration, at low current levels, 1/gm >> Rs and hence Gm * gm [Fig. 3.18(b)]. As the overdrive and therefore gm increase, the effect of degeneration, 1 + gm Rs in (3.49), becomes more significant. For large values of Vi, (if My is still saturated), Ip is approximately linear and Gp, approaches 1/Rs. Example 3.4 Plot the small-signal voltage gain of the circuit in Fig. 3.16 as a function of the input bias voltage. Solution Using the results derived above for the equivalent transconductance of Mi and Rs, we arrive at the plot shown in Fig, 3.19, For Vin slightly greater than Vrjz, 1/gm >> Rs and Ay * —gqRp. Vm Vin Figure 3.19 As Vin increases, degeneration becomes more significant and Ay = —gmRp/( + gmRs). For large values of Vin, Gm * 1/Rs and Ay = —Rp/Rs. However, if Vin > Vour + Vrir, that is, if Rolp > Vr + Vop ~ Vin, Mj enters the triode region and Ay, drops. LL Equation (3.51) can be rewritten as (3.56)Sec. 3.2 Common-Source Stage 63 This result allows formulating the gain by inspection. First, let us examine the denominator of (3.56). The expression is equal to the series combination of the inverse transconduc- tance of the device and the explicit resistance seen from the source to ground. We call the denominator “the resistance seen in the source path” because if, as shown in Fig. 3.20, we disconnect the bottom terminal of Rs from ground and calculate the resistance seen “looking up” (while setting the input to zero), we obtain Rs + 1/&m- Vino all om Rs reed Figure 3.20 Resistance seen in the 9m source path, Noting that the numerator of (3.56) is the resistance seen at the drain, we view the magnitude of the gain as the resistance seen at the drain node divided by the total resistance in the source path. This method greatly simplifies the analysis of more complex circuits. Example 3.5 Assuming A = y = 0, calculate the small-signal gain of the circuit shown in Fig. 3.21(a).. Yoo Yoo Ap Rp Vout Vout Vinee, Vine, 7 lees Tan @ © Figure 3.21 Solution Noting that Mp is a diode-connected device and simplifying the circuit to that shown in Fig. 3.21(b), we use the above rule to write @.57)64 Chap.3 Single-Stage Amplifiers Another important consequence of source degeneration is the increase in the output resistance of the stage. We calculate the output resistance first with the aid of the equivalent circuit shown in Fig. 3.22. Note that body effect is also included to arrive at a general result. Figure 3.22. Equivalentcircuit forcal- culating the output resistance of a degen- erated CS stage. Since the current through Rs is equal to Ix, Vi = —I Rs and the current flowing through ro is given by Ix — (m+ 8mb)Vi = Lx +(8m + 8ms) Rs 1x. Adding the voltage drops across ro and Rs, we obtain rollx + (8m + 8mb)RsIx] + IxRs = Vx. 3.58) It follows that Rou = [+ (8m + &mo)RsIro + Rs (3.59) = 1+ (8m + BmorolRs + ro. (3.60) Since typically (gm + 8ms)ro > 1, we have Rour © (8m + Bmb)roRs + ro. 3.61) = 1+ Wm + 8mb)Rslro, (3.62) indicating that the output resistance has increased by a factor 1 + (gm ++ 8mo)Rs. This is an important and useful result. To gain more insight, let us consider the circuit of Fig. 3.22 with Rs = O and Rs > 0.1If Rs = 0, then &mVi = 8mbVbe = Oand Ix = Vx/ro. On the other hand, if Rs > 0, we have IRs > Oand V; <0, obtaining negative gm Vi and gmbVbs. Thus, the current supplied by Vy is less than Vx/ro. The relationships in (3.60) and (3.62) can also be derived by inspection. As shown in Fig. 3.23(a), we apply a voltage to the output node, change its value by AV, and measure the resulting change, AJ, in the output current. Since the current through Rs must change by AJ, we first compute the voltage change across Rs. To this end, we draw the circuit as shown in Fig. 3.23(b) and note that the resistance seen looking into the source of M; is equal to 1/(m + Sms) [Eq. (3.24)], thus arriving at the equivalent circuit in Fig. 3.23(c).Sec.3.2 Common-Source Stage 65 al av av > Pav Sav to 1 " t " r ri hd mi Fre Gat Imo D Dl Weg Rs Rs 7 Rs fa) (b) © Figure 3.23 (a) Change in drain current in response to change in applied voltage to drain, (b) equivalent of (a), (¢) small-signal model. The voltage change across Rs is therefore equal to : relies AVas = AV—Sn ¥ Sn __ 3.63) Smrgewa Re ee Bm + Bmb The change in the current is AVrs Al= i 3.64) =AV i (3.65) "Gn + &mv)RsIro + Rs" " that is, AV Al = LU + (8m + &mo)RsIro + Rs. (3.66) With the foregoing developments, we can now compute the gain of a degenerated CS stage in the general case, taking into account both body effect and channel-length modulation. In the equivalent circuit depicted in Fig. 3.24, the current through R's must equal that through Rp, i€., —Vou/ Rp. Thus, the source voltage with respect to ground (and the bulk) is equal 10 ~VourRs/ Rp and hence Vi = Vin + VourRs/Rp. The current through ro can therefore be written as Iro = ~~ (8mVi + BnbVos) (3.67) Vout Rs Rs = Bo — | Bm (Vin + Vou = ) + &mbVous =~ | - 3.68) [« ( + #) +8 Vo z| G.68)Chap. 3 Single-Stage Amplifiers Figure 3.24 Small-signal model of degenerated CS stage with finite output resistance. Since the voltage drop across ro and Rs must add up to Vour, we have Vout Vou = roto ~ Rs 3.69) (3.70) It follows that Vout =8mtoRd @.71) Vin Ro+Rs+ro + Bm + kmodRsro™ To gain more insight into this result, we recognize that the last three terms in the denom- inator, namely, Rs +70 + (8m +8mb)Rsro, represent the output resistance of a MOS device degenerated by a resistor Rs, as originally derived in (3.60). Let us now rewrite (3.71) as =8mroRoIRs + ro + (Gm + 8ms)Rsrol 1 om Rot Rs+ro+ (Gm + Bm)Rsro | Rs tro+ (8m + Bme)Rsro = Snlo RolRs + ro + (8m + &mb)Rsrol G73) “Rs +10 + Bm + 8no)Rsro Ry + Rs +ro + Bn + &ma)Rsro The two fractions in (3.73) represent two important parameters of the circuit: the first is identical to that in (3.55), i., the equivalent transconductance of a degenerated MOSFET; and the second denotes the parallel combination of Rp and Rs + ro + (8m + 8ns)Rstos ice, the overall output resistance of the circuit, ‘The above discussion suggests that in some circuits it may be easier to calculate the voltage gain by exploiting the following lemma. Lemma. Ina linear circuit, the voltage gain is equal to —Gm Rous, Where Gp, denotes the transconductance of the circuit when the output is shorted to ground and Rous represents the output resistance of the circuit when the input voltage is set to zero [Fig. 3.25(a)]. The lemma can be proved with the aid of Fig. 3.25 by noting that the output port of a linear circuit can be modeled by a Norton equivalent. That is, the output voltage is equal to ~Iou; Rout, and Toy; can be obtained by measuring the short-circuit current at the output.Sec. 3.3 Source Follower 67 i = Yin Dour = Rout] 4 tour Fou} Rout y Figure 3.25 Modeling output port of an amplifier by a Norton equivalent. Defining Gy = Jour/ Vin, We have Vou and Rou; can be determined by inspection. Grn Vin Rout: This lemma proves useful if Gm Example 3.6 Calculate the voltage gain of the circuit shown in Fig. 3.26, Assume Jo is ideal. = Figure 3.26 Solution ‘The transconductance and output resistance of the stage are given by Eqs. (3.55) and (3.60), respec tively. Thus, Bnro "RS FTF Gm + 8mb)RsIro oe (3.75) {L1 + Gn + Sn)rolRs +70) G74) Interestingly, the voltage gain is equal to the intrinsic gain of the transistor and independent of Rs Thisis because, if Jo is ideal, the current through Rs cannot change and hence the small-signal voltage drop across Rs is zero—as if Rs were zero itself. 3.3 Source Follower ‘Our analysis of the common-source stage indicates that, to achieve a high voltage gain with limited supply voltage, the load impedance must be as large as possible. If such a stage is to drive a low-impedance load, then a “buffer” must be placed after the amplifier so as to drive the load with negligible loss of the signal level. The source follower (also called the “common-drain” stage) can operate as a voltage buffer. Ulustrated in Fig. 3.27(a), the source follower senses the signal at the gate and drivesChap.3 — Single-Stage Amplifiers Yoo Vout Vine am, Vout Rs VtH Vin @ © Figure 3.27 (a) Source follower, and (b) its input-output charac- teristic. the load at the source, allowing the source potential to “follow” the gate voltage. Beginning with the large-signal behavior, we note that for Vi, < Vr, Mj is off and Voy = 0. AS Vin exceeds Viz, M; turns on in saturation (for typical values of Vpp) and Ip; flows through Rs (Fig. 3.27(b)]. As Vig increases further, Vou: follows the input with a difference (level shift) equal to Vc.s. We can express the input-output characteristic as: FHCs Win ~ Vr — Vout)’ Rs = Vour- (3.76) Let us calculate the small-signal gain of the circuit by differentiating both sides of (3.76) with respect to Vin: low Vin 8Veu Vout glenCox 7 2Vin — Vr — Vout) (1 — 3, )®s= oy, 87 gnCor 7 2Vin — View 0( 2Vin an) ® an, OTD Since 8Vri/8Vin = 19 Vour/9Vin, Ww Vp Hn Cox Vin ~ Vrwe — Vous) Rs ay, Ww . (3.78) "+ MnCor (Vin Vr — Vou)Rs(l +n) Also, note that Ww 8m = HaCox (Vin — Vein — Vout)- 3.79) Consequently, 8&mRs (3.80) 1+ (Gm + 8mp)Rs” ‘The same result is more easily obtained with the aid of a small-signal equivalent circuit. From Fig. 3.28, we have Vig — Vi = Vours Vis = —Vours and &mVi — &mbVour = Vour/ Rs.Sec. 3.3 Source Follower 69 Figure 3.28 Small-signal equivalent circuit of source follower. Figure 3.29 Voltage gain of source follower versus input voltage. Thus, Vour/ Vin = 8m Rs/U1 + (Gm + &mb)Rs] Sketched in Fig. 3.29 vs. Vin, the voltage gain begins from zero for Vi, * Vry (that is, 8m * 0) and monotonically increases. As the drain current and g,, increase, A, approaches 8m/(8m + 8mb) = 1/(1 +n). Since 7 itself slowly decreases with Vou;, A, would eventually become equal to unity, but for typical allowable source-bulk voltages, n remains greater than roughly 0.2. Animportant result of (3.80) is that even if Rs = 00, the voltage gain of a source follower is not equal to one. We return to this point later. Note that M, in Fig. 3.27 does not enter the triode region if V;,, remains below Vpp. In the source follower of Fig. 3.27, the drain current of M; heavily depends on the input de level. For example, if Vin changes from 1.5 V to 2 V, Ip may increase by a factor of 2 and hence Ves — Vr by V2, thereby introducing substantial nonlinearity in the input-output characteristic. To alleviate this issue, the resistor can be replaced by a current source as shown in Fig. 3.30(a). The current source itself is implemented as an NMOS transistor operating in the saturation region [Fig. 3.30(b)] Yop Yoo Yin oB My Vine My Vout Vout n Yoho, @ () Figure 3.30 Source follower using an NMOS transistor as current source,70 Chap.3 Single-Stage Amplifiers Example 3.7 ‘Suppose in the source follower of Fig. 3.30(a), (W/L), = 20/0.5, fy = 200 #A, Vrxo = 0.6 V, 2p =0.7V, UnCox = 50 WAIV?, and y = 0.4 V? (@) Caleulate Vous for Vin = 1.2 V. (b) If His implemented as Mz in Fig. 3.30(b), find the minimum value of (W/L)) for which Mp remains saturated. Solution (a) Since the threshold voltage of My depends on Vous, we perform a simple iteration. Noting that 2h Win Ven ~ Vou)? = Po, G81) inCox “ ( z ) we first assume Vrq * 0.6 V, obtaining Voy; = 0.153 V. Now we calculate a new Vz #7 a8 Ven = Vruo + v(/2®r + Vsp ~ 2p) 3.82) = 0.635 V. (3.83) This indicates that Voy: is approximately 35 mV less than that calculated above, ie., Vous ~ 0.119 V. (b) Since the drain-source voltage of Mp is equal to 0.119 V, the device is saturated only if (Vas — Vri)z = 0.119 V. With Ip = 200 A, this gives (W/L)z = 283/05. Note the substantial drain junction and overlap capacitance contributed by Mz to the output node. To gain a better understanding of source followers, let us calculate the small-signal output resistance of the circuit in Fig. 3.31(a). Using the equivalent circuit of Fig. 3.31(b) and noting that Vj = —Vy, we write Tx. — &mVx — 8mbVx = 0. (3.84) “kK o e ac My “uv @® D Goes tI Ix Ix + + vy uO x @ &) © Figure 3.31 Calculation of the output impedance of a source follower.Sec. 3.3, Source Follower n It follows that eS ea (3.85) Interestingly, body effect decreases the output resistance of source followers. To understand why, suppose in Fig. 3.31(c), Vy decreases by AV so that the drain current increases. With no body effect, only the gate-source voltage of M; would increase by AV. With body effect, on the other hand, the threshold voltage of the device decreases as well. Thus, in (Ves —Vru)* the first term increases and the second decreases, resulting in a greater change in the drain current and hence a lower output impedance. The above phenomenon can also be studied with the aid of the small-signal model shown in Fig. 3.32(a). It is important to note that the magnitude of the current source gmpVbs is -—, 1" Y m1 ty 4 ie Ome Vy it © Figure 3.32 Source follower including body effect. linearly proportional to the voltage across it. Such behavior is that of a simple resistor equal to 1/&mb, yielding the small-signal model shown in Fig. 3.32(b). The equivalent resistor simply appears in parallel with the output, thereby lowering the overall output resistance. The reader can show that, without 1/gm4, the output resistance equals 1/g,, concluding that 3.86) (3.87) Modeling the effect of gy by a resistor—which is only valid for source followers—also helps explain the less-than-unity voltage gain implied by (3.80) for Rs = 00. As shown inChap.3 —Single-Stage Amplifiers Tm Figure 3.33 Representation of intrinsic source follower by a Thevenin equivalent, the Thevenin equivalent of Fig. 3.33, (3.88) eee Bn + 8nd (3.89) For completeness, we also study the source follower of Fig. 3.34(a) with finite channel- length modulation in M, and M2. From the equivalent circuit in Fig. 3.34(b), we have 1 —lroiWro2ll Re ———————— 3.90) T T = llroullroall Re + Bmb 8m @ ) Figure 3.34 (a) Source follower driving load resistance, (b) small-signal equivalent circuit,Seo. 3.3 Source Follower 73 Example 3.8 Calculate the voltage gain of the circuit shown in Fig. 3.35. Figure 3.35 Solution The impedance seen looking into the source of Mp is equal to [1/(gm2 + 8m2)]llro2. Thus, 1 Sepp reairo— hy = S02 Sain bts G91) ——— Iroatroill — + — 8in2 + Bmb2 Bmbi— &mi Source followers exhibit a high input impedance and a moderate output impedance, but at the cost of two drawbacks: nonlinearity and voltage headroom limitation. We consider these issues in detail ‘As mentioned in relation to Fig. 3.27(a), even if a source follower is biased by an ideal current source, its input-output characteristic displays some nonlinearity due to the nonlinear dependence of Vr upon the source potential. In submicron technologies, ro of the transistor also changes substantially with Vps, thus introducing additional variation in the small-signal gain of the circuit (Chapter 16). For this reason, typical source followers suffer from several percent of nonlinearity. The nonlinearity due to body effect can be eliminated if the bulk is tied to the source. This is usually possible only for PFETs because all NFETs share the same substrate. Fig. 3.36 shows a PMOS source follower employing two separate n-wells so as to eliminate the body effect of My. The lower mobility of PFETs, however, yields a higher output impedance in this case than that available in an NMOS counterpart. Source followers also shift the de level of the signal by Vgs, thereby consuming voltage headroom and limiting the voltage swings. To understand this point, consider the example illustrated in Fig. 3.37, a cascade of a common-source stage and a source follower. Without the source follower, the minimum allowable value of Vx would be equal to Vesi — Vr (for M, to remain in saturation). With the source follower, on the other hand, Vx must be greater than Vaso + (Voss — Vr3) 0 that Ms is saturated. For comparable overdrive voltages in ‘M, and Ms, this means the allowable swing at X is reduced by Vso, a substantial amount. Itis also instructive to compare the gain of source followers and common-source stages when the load impedance is relatively low. A practical example is the need to drive an external 50-@ termination in a high-frequency setup. As shown in Fig. 3.38(a), the load can4 Chap.3 Single-Stage Amplifiers @) Figure 3.37 Cascade of source fol- lower and CS stage. be driven by a source follower with an overall voltage gain of Vout Re eae EE Vin 8 * Re Wem ee On the other hand, as depicted in Fi . 3.38(b), the load can be included as part of acommon- Yoo Yoo Vino at A Ve ¥, out ‘out Vine My hen - (b) (a) Figure 3.38 (a) Source follower and (b) CS stage driving a load resistance.Sec. 3.3 Source Follower 8 source stage, providing a gain of Vout Vin les —gm Ri. 6.93) The key difference between these two topologies is the achievable voltage gain for a given bias current. For example, if 1/gm1 ~ Rx, then the source follower exhibits a gain of at most 0.5 whereas the common-source stage provides a gain close to unity. Thus, source followers are not necessarily efficient drivers, The drawbacks of source followers, namely, nonlinearity due to body effect, voltage headroom consumption due to level shift, and poor driving capability, limit the use of this topology. Perhaps the most common application of source followers is in performing voltage level shift, Example 3.9 (a) In the circuit of Fig. 3.39(a), calculate the voltage gain if C; acts as an ac short at the frequency of interest. What is the maximum de level of the input signal for which My remains saturated? @ ©) Figure 3.39 (b) To.accommodate an inputde level close to Vpp. the circuit is modified as shown in Fig. 3.39(b). ‘What relationship among the gate-source voltages of Mj-M3 guarantees that M; is saturated? Solution (@) The gain is given by Av = —8milroillro2ii(l/gm2))- (3.94) Since Vour = Vop—|Vesal, the maximum allowable de level of Vin is equal to Vpp—|Vesal-+ Vr ii. (©) If Vin = Vop, then Vx = Vop — Vgs3. For Mj to be saturated, Vpp — Voss — Vrin < Vop ~ |Vas2\ and hence Vgs3 + Vrii > |Ves2! CE76 Chap.3 — Single-Stage Amplifiers As explained in Chapter 7, source followers also introduce substantial noise. For this reason, the circuit of Fig. 3.39(b) is ill-suited to low-noise applications. 3.4 Common-Gate Stage Incommon-source amplifiers and source followers, the input signal is applied to the gate of a MOSFET. Itis also possible to apply the signal to the source terminal. Shown in Fig, 3.40(a), a common-gate (CG) stage senses the input at the source and produces the output at the drain, The gate is connected to a de voltage to establish proper operating conditions. Note that the bias current of Mj flows through the input signal source. Alternatively, as depicted in Fig. 3.40(b), Mj can be biased by a constant current source, with the signal capacitively coupled to the circuit, vA Yoo CJ Rr Rp D Vout Vout V, i h-M% 7 Vi L , . mS in ; (a) {b) Figure 3.40 (a) Common-gate stage with direct coupling at input, (b) CG stage with capacitive coupling at input. ‘We first study the large-signal behavior of the circuit in Fig. 3.40(a). For simplicity, let us assume that Vj, decreases from a large positive value. For Vin > Vs — Vr, Mj is off and Vour = Vop. For lower values of Vin, we can write 1 Ww I = 5HnCox (Vo ~ Vin — Von) G95) if M, is in saturation. As Vi, decreases, so does Voy:, eventually driving Mj into the triode region if Lic Ww 2 Vow ~ 3H4nCox-¢-(Vo — Vin ~ Vr) Ro = Vo ~ Ven 3.96) ‘The input-output characteristic is shown in Fig. 3.41. If M; is saturated, we can express the output voltage as 1 Ww Vou = Vow ~ 5HnCox7-(Vs — Vin ~ Vr) Ros (3.97)Seo. 3.4 Common-Gate Stage 7 Vo-Vinv,, Figure 3.41 Common-gate input- = output characteristic. obtaining a small-signal gain of BVour Ww OVrn Bi a Ma Cor eV — Vn Vr (—1 — 6.98) Since OVrx/9Vin = 9VrH/3Vs— =n, we have Vout Ww Wn inCox 7 Ro(Vo — Vin — Vr Xl +0) (3.99) = &m(l+n)Ro. (3.100) Note that the gain is positive. Interestingly, body effect increases the equivalent transcon- ductance of the stage, The input impedance of the circuit is also important. We note that, for 4 = 0, the impedance seen at the source of M, in Fig. 3.40(a) is the same as that at the source of M, in Fig. 3.31, namely, 1/(gm + 8mb) = 1/L8m(1 + n)]. Thus, the body effect decreases the input impedance of the common-gate stage. The relatively low input impedance of the common-gate stage proves useful in some applications. Example 3.10 In Fig. 3.42, transistor M, senses AV and delivers a proportional current to a 50-2 transmission line. ‘The other end of the line is terminated by a 50-S resistor in Fig. 3.42(a) and a common-gate stage in Fig. 3.42(b). Assume A = y = 0. (@) Calculate Vour/ Vin at low frequencies for both arrangements. (b) What condition is necessary to minimize wave reflection at node X? Solution (a) For small signals applied to the gate of Mj, the drain current experiences a change equal to mi 4Vx. This current is drawn from Rp in Fig. 3.42(a) and Mp in Fig. 3.42(b), producing an output voltage swing equal to ~gm1 AVx Rp. Thus, Ay = —gmRp for both cases. (b) To minimize reflection at node X, the resistance seen at the source of Mz must equal 50 and the reactance must be small. Thus, 1/(@m + &mb) = 50 @, which can be ensured by proper sizing and biasing of Mz. To minimize the capacitances of the transistor, itis desirable to use a small device biased at a large current, (Recall that gm = »/24nCox(W/L)Ip.) In addition to higher power dissipation, this remedy also requires a large Ves for Mg.78 Chap.3 — Single-Stage Amplifiers oom 1 aa ob Tio ou co @ Figure 3.42 ‘The key point in this example is that, while the overall voltage gain in both arrangements equals —gmiRp, the yalue of Rp in Fig. 3.42(b) can be much greater than 50 @ without introducing reflections at point X. Thus, the common-gate circuit can provide a much higher voltage gain than that in Fig. 3.42(a). Now let us study the common-gate topology in a more general case, taking into ac- count both the output impedance of the transistor and the impedance of the signal source. Depicted in Fig. 3.43(a), the circuit can be analyzed with the aid of its equivalent shown (b) Figure 3.43 (a) CG stage with finite output resistance, (b) small-signal equivalent circuit. in Fig. 3.43(b). Noting that the current flowing through Rs is equal to —Vou/Rp. We have: Vout Vi- 3 Rs + Vin 1 Rp 's + Vi 101)Sec.3.4 — Common-Gate Stage 79 Moreover, since the current through ro is equal to —Vou./ Rp — 8m Vi ~ BmoVi, We can Write —Vour Vout ro ( = 8mVi — envi) - Rs + Vin = Vout (3.102) Rp Ro Upon substitution for V; from (3.102), (3.101) reduces to Vous Rs — (Bm + 8m) { Vou Z— ~ Vin ) | — ro [=f ~ e+ 600 (tar - vi) It follows that Rs Rp + Vin = Vous (3.103) Vout (Gm + Boro +1 Vin To + (m+ Bnb\roRs + Rs + Ro Ro. (3.104) Note the similarity between (3.104) and (3.71). The gain of the common-gate stage is slightly higher due to body effect. Example 3.11 Calculate the voltage gain of the circuit shown in Fig. 3.44(a) if A # O and y #0. Yop Yoo Rp Ro Vout Vout Yb, Ym, R, eq My wy Vine 2c) ©) "© Figure 3.44 Solution We first find the Thevenin equivalent of My. As shown in Fig. 3.44(b), M) operates as a source follower and the equivalent Thevenin voltage is given by rou Vineg = 3.105) ro | Smb1 SmtChap.3 —_Single-Stage Amplifiers and the equivalent Thevenin resistance is 1 1 Req =ro1 bua, (3.106) Boi | mt Redrawing the circuit as in Fig. 3.44(c), we use (3.104) to write ve (Gna + 1 "OU gt Zi n+ 8miaroa + Fb aon in i ror + (1 + (Ga + nta¥ro2] (roi]——]—] + Ro roif—— + — &mb1 || Smt Bmb1 Bm? The input and output impedances of the common-gate topology are also of interest. To obtain the impedance seen at the source (Fig. 3.45(a)], we use the equivalent circuit in Yoo Rp My Yb, ¥r0 tin, (a) ) Figure 3.45 (a) Input resistance of a CG stage, (b) small-signal equivalent circuit. Fig. 3.45(b). Since V; = —Vy and the current through ro is equal to Ix + 8mVi + &mbVi = 1x ~ (Gm + 8m) Vx, We can add up the voltages across ro and Rp as Rolx +rollx — (8m + &mb)Vx] = Vx. (3.108) Thus, Vx Ro tro ceeaaee eeecuemaas eames (3.109) Tx 1+ (8m + &mb)ro f » Ro 1 we _ (3.110) (8m + Bmb\O Bm + Bmbs if @m+8mo)ro > 1. This result reveals that the drain impedance is divided by (gm-+8mb)ro when seen at the source. This is particularly important in short-channel devices because of their low intrinsic gain. Two special cases of (3.109) are worth studying. First, supposeSeo. 3.4 Common-Gate Stage 81 Rp = 0. Then, ¥ Ads a B.D Tx V+ (8m + 8mo)ro eee 112) 1 Ft 8m + 8imb ro which is simply the impedance seen at the source of a source follower, a predictable result because if Rp = 0, the circuit configuration is the same as in Fig. 3.31(a). Second, let us replace Rp with an ideal current source. Equation (3.110) predicts that the input impedance approaches infinity. While somewhat surprising, this result can be explained with the aid of Fig. 3.46. Since the total current through the transistor is fixed and equal to /;, a change in the source potential cannot change the device current, and hence 1x = 0. In other words, the input impedance of a common-gate stage is relatively low only if the load impedance connected to the drain is small. Yoo 4 My wk =o Ix %O - Figure 3.46 Input resistance of a CG stage with ideal current source load. Example 3.12 Calculate the voltage gain of a common-gate stage with a current-source load [Fig. 3.47(a)]. Solution Letting Rp approach infinity in (3.104), we have Av = (Gm + Smb)ro +1. 3.113) Interestingly, the gain does not depend on Rs. From our foregoing discussion, we recognize that if Rp ~ 00, so does the impedance seen at the source of Mj, and the small-signal voltage at node X becomes equal to Vin. We can therefore simplify the circuit as shown in Fig. 3.47(b), readily arriving at 3.113) In order to calculate the output impedance of the common-gate stage, we use the circuit82 Chap. 3 Single-Stage Amplifiers Yoo on Vout My Vout | to x Yin (a) ) Figure 3.47 in Fig. 3.48. We note that the result is similar to that in Fig. 3.22 and hence Rour = {1 + (8m + Bmb)rolRs + rolllRo- G.114) Figure 3.48 Calculation of output re- sistance of a CG stage. Example 3.13 As seen in Example 3.10 the input signal of a common-gate stage may be a current rather than voltage. Shown in Fig, 3.49 is such an arrangement, Calculate Vour/Jin and the output impedance of the circuit if the input current source exhibits an output impedance equal to Rp. Solution To find Vout / Tin, we replace Jin and Rp with a Thevenin equivalent and use (3.104) to write Vout _ (an + Boro +1 Tin 10+ Gm + Bb FORE + Rp + Rp RoRp. 3.115)Sec.3.5 Cascode Stage 83 Yoo Fo Vout Me ‘in Ap = = Figure 3.49 ‘The output impedance is simply equal to Rout = {1 + (gm + gmp)rolRe + rolllRp. 116) 3.5 Cascode Stage As mentioned in Example 3.10 the input signal of a common-gate stage may be a current. We also know that a transistor in a common-source arrangement converts a voltage signal to a current signal. The cascade of a CS stage and a CG stage is called a “cascode” topology, providing many useful properties. Fig. 3.50 shows the basic configuration: M; generates a small-signal drain current proportional to V;, and M2 simply routes the current to Rp. Figure 3.50 Cascode stage. We call M; the input device and Mz the cascode device. Note that in this example, M, and Mp carry equal currents. As we describe the attributes of the circuit in this section, many advantages of the cascode topology over a simple common-source stage become evident. First, let us study the bias conditions of the cascode, For Mj to operate in saturation, Vx > Vin — Vein. If M; and M; are both in saturation, then Vx is determined primarily by The term cascode is believed to be the acronym for “cascaded triodes,” possibly invented in vacuum tube days.Chap.3 — Single-Stage Amplifiers Vp: Vx = Vb — Vaso. Thus, Vs — Vos2 = Vin — Vreri and hence Vp > Vin + Ves2 — Vr (Fig. 3.51). For Mz to be saturated, Vow > Vi — Vru2, thatis, Vouk > Vin — Vr + Vos2 — Figure 3.51 Allowable voltages in cascode stage. Vrun if Vp is chosen to place My at the edge of saturation. Consequently, the minimum output level for which both transistors operate in saturation is equal to the overdrive voltage of M, plus that of Mp. In other words, addition of Mz to the circuit reduces the output voltage swing by at least the overdrive voltage of Mz. We also say Mz is “stacked” on top of M.. We now analyze the large-signal behavior of the cascode stage shown in Fig. 3.50 as Vin goes from zero to Vpp. For Vin < Vrai, Mi and Mp are off, Vow = Vop, and Vx © Vs — Vena (if subthreshold conduction is neglected) (Fig. 3.52). As Vin exceeds Veni, My begins to draw current, and Voye drops. Since Ip increases, Vas2 must increase Figure 3.52 Input-output characteris- tic of a cascode stage. Vani Vin as well, causing Vx to fall. As Viz assumes sufficiently large values, two effects occur: (1) Vx drops below Vig by Vrii, forcing M; into the triode region; (2) Vow drops below Vp by Vru2, driving Mz into the triode region, Depending on the device dimensions and the values of Rp and V;, one effect may occur before the other. For example, if Vj is relatively Jow, M, may enter the triode region first. Note that if Mz goes into deep triode region, Vx and Vou become nearly equal. Let us now consider the small-signal characteristics of a cascode stage, assuming both transistors operate in saturation. If . = 0, the voltage gain is equal to that of a common- source stage because the drain current produced by the input device must flow through the cascode device. Illustrated in the equivalent circuit of Fig. 3.53, this result is independent of the transconductance and body effect of M2.Sec.3.5 Cascode Stage 85 SmiV1 Vout Figure 3.53 Small-signal equivalent circuit of cascode stage. Example 3.14 Calculate the voltage gain of the circuit shown in Fig. 3.54 if A = 0. Figure 3.54 Solution ‘The small-signal drain current of My, gmi Vins is divided between Rp and the impedance seen looking into the source of Mz, 1/(em2 + mba). Thus, the current flowing through Mz is (m2 + &mb2)Re Tp2 = 8m Vin (3.117) ST ema + &nba) RP The voltage gain is therefore given by mil Gm2 + &mba)RPRi Ay = —8niGna + SmbRPRD | @.118) T+ (m2 + Bmba) RP An important property of the cascode structure is its high output impedance. As illustrated in Fig. 3.55, for calculation of Ryu, the circuit can be viewed as a common-source stage with a degeneration resistor equal to ro). Thus, from (3.60), Rout = 1+ (8m2 + 8mb2)roalro1 + roa. 119)Chap.3 —Single-Stage Amplifiers Figure 3.55 Calculation of output re- sistance of cascode stage. Ye2e EM Yore M Vino My, Figure 3.56 Triple cascode. Assuming gmro > 1, we have Rou * (m2 + &mb2)Fo2ro1- That is, Mz boosts the output impedance of M, by a factor of (m2 + 8mb2)Fo2. As shown in Fig. 3.56, cascoding can be extended to three or more stacked devices to achieve a higher output impedance, but the required additional voltage headroom makes such configurations less attractive. For example, the minimum output voltage of a triple cascode is equal to the sum of three overdrive voltages. To appreciate the usefulness of a high output impedance, recall from the lemma in Section. 3.2.3 that the voltage gain can be written as Gr, Rous. Since Gm is typically determined by the transconductance of a transistor, e.g., M; in Fig. 3.50, and hence bears trade-offs with the bias current and device capacitances, itis desirable to increase the voltage gain by maximizing Roy. Shown in Fig. 3.57 is an example. If both M, and Mz operate in saturation, Yoo h Vout Yom, Vinee My Figure 3.57 Cascode stage with current-source load. then Gm ® Bmi and Rou © (m2 + Smb2)ro2ro1, Yielding Ay = (m2 + 8md2)FO28miTo1-Sec.3.8 Cascode Stage 87 Thus, the maximum voltage gain is roughly equal to the square of the intrinsic gain of the transistors. Example 3.15 Calculate the exact voltage gain of the circuit shown in Fig. 3.57. Solution ‘The actual Gm of the stage is slightly less than gt because a fraction of the small-signal current Produced by Mj is shunted to ground by ro1. As depicted in Fig. 3.58: Yoo hh Vout Ma Wek. roe Tot = Imi For Vin ©) Figure 3.58 Tout = 8m Vin rol 3.120) ror + ——}r, O1F gma + Boa f°? It follows thatthe overall transconductance is equal to Gq = —SmitotronGina + énba)+ 1 enn To1ro2(8m2 + 8mb2) +701 + ror and hence the voltage gain is given by \Av| = Gm Rout (3.122) = Smirosll@m2 + &mb2)¥02 + 11 @.123) If we had assumed Gm © gm, then |Ay| * 8mi{Ll + (m2 + 8mé2)ro2Iro1 + ro2)- Another approach to calculating the voltage gain is toreplace Vin and M; by a Thevenin equivalent, reducing the circuit to a common-gate stage. Ilustrated in Fig. 3.58(b), this method in conjunction with (3.104) gives the same result as (3.123).Chap.3 Single-Stage Amplifiers to 'p Ip Yor vy Ww Vin Ww ince in ae Vine # @ © © Figure 3.59 Increasing output impedance by increasing the device length or cascoding. It is also interesting to compare the increase in gain due to cascoding with that due to increasing the length of the input transistor for a given bias current (Fig. 3.59). Suppose, for example, that the length of the input transistor of a CS stage is quadrupled while the width remains constant. Then, since Ip = (1/2)ttnCox(W/L)(Vas — Vriz)*, the overdrive voltage is doubled, and the transistor consumes the same amount of voltage headroom as does a cascode stage. That is, the circuits of Figs. 3.59(b) and (c) impose equal voltage swing constraints. Now consider the output impedance achieved in each case. Since (3.124) and 4 x 1/L, quadrupling L only doubles the value of gmro while cascoding results in an output impedance of roughly (gm7o)?. Note that the transconductance of My in Fig. 3.59(b) is half that in Fig. 3.59(c), leading to higher noise (Chapter 7).. A cascode structure need not operate as an amplifier. Another popular application of this topology is in building constant current sources. The high output impedance yields a current source closer to the ideal, but at the cost of voltage headroom. For example, current source J} in Fig. 3.57 can be implemented with a PMOS cascode (Fig. 3.60), exhibiting an impedance equal to [1 + (gms + 8nss)"o3]ros + ro3- If the gate bias voltages are chosen Cascode Current Source Vg Figure 3.60 NMOS cascode ampli- ¥ fier with PMOS cascode load.Sec. 3.5, Cascode Stage 89 properly, the maximum output swing is equal to Vpp — (Vest — Vr) ~ (Vasa — Vera) — \Ves3 — Vru3l — |Vasa — Vrual- We calculate the voltage gain with the aid of the lemma illustrated in Fig. 3.25. Writing Gm © Bmi and Rour = (1 + (8m2 + Bmb2\ro2]ro1 + roa}IM{Ll + (Bm3 + Smbs)roslros + ros), (3.125) we have |Ay| © 81 Row. For typical values, we approximate the voltage gain as {Aol © Smil(gm2ro2ro1)II(8m3ro3ro4)]- 3.126) Shielding Property Recall from Fig. 3.23 that the high output impedance arises from the fact that if the output node voltage is changed by AV, the resulting change at the source of the cascode device is much less. In a sense, the cascode transistor “shields” the input device from voltage variations at the output. The shielding property of cascodes proves useful in many circuits. Example 3.16 Two identical NMOS transistors are used as constant current sources in a system [Fig. 3.61(a)]. However, due to internal circuitry of the system, Vy is higher than Vy by AV. Figure 3.61 (@) Calculate the resulting difference between Ip; and Ip2 if A #0. (b) Add cascode devices to My and Mz and repeat part (2). Solution (@) We have 1 w x Toi ~ Hon = 5HnCox (Vb — Vr)*QVpsi ~ 4V 052) 3.127) 1 w = GeaCox 7 (M6 ~ Vr PQAV). (3.128)Chap.3 — Single-Stage Amplifiers (b) As shown in Fig. 3.61(b), cascoding reduces the effect of Vx and Vy upon /p1 and Ip2, respectively. As depicted in Fig, 3.23 and implied by Eq. (3.63), a difference AV between Vx and Vy translates to a difference AVpg between P and Q equal to rot Oe eee (3.129) Po = AV TE Gena ¥ amoadroalroi + Fos am AV ——_-—__.. (3.130) (m3 + 8mb3)rO3 Thus, Low aay It — In2 = 5 UnCox (Vb ~ Vr —————. 3.131 DE ta ginox 7 Uo VOW) enon In other words, cascoding reduces the mismatch between Ip1 and Ip2 by (m3 + &mb3)P03 The shielding property of cascodes diminishes if the cascode device enters the triode region. To understand why, let us consider the circuit in Fig. 3.62, assuming Vx decreases from a large positive value. As Vx falls below Vi2—Vri2, Mz requires a greater gate-source Figure 3.62 Output swing of cascode stage. overdrive so as to sustain the current drawn by M;. We can write 1 Ww Tor = 5 HnCox (Z) [2(Vb2 = Vp — Vrn2)(Vx — Ve)— (Vx — Vey}, (3.132) 2 concluding that as Vx decteases, Vp also drops so that [p2 remains constant. In other words, variation of Vx is less attenuated as it appears at P. If Vx falls sufficiently, Vp goes below Vin — Vrizi, driving M; into the triode region. 3.5.1 Folded Cascode The idea behind the cascode structure is to convert the input voltage to a current and apply the result to a common-gate stage. However, the input device and the cascode device need not be of the same type. For example, as depicted in Fig. 3.63(a), a PMOS-NMOS combination performs the same function. In order to bias M; and Mz, a current source must be added as in Fig. 3.63(b). The small-signal operation is as follows. If Viq becomes more positive, |Jp1| decreases, forcing pz to increase and hence Vou: to drop. The voltage gain and output impedance of the circuit can be obtained as calculated for the NMOS-NMOSSec.3.5 Cascode Stage 91 Yoo Yop Rp Fo Vin Yor Vn 2 Vout = HM 9m Vin we i; @ ® Figure 3.63 (a) Simple folded cascode, (b) folded cascode with proper biasing, (c) folded cascode with NMOS input. cascode of Fig. 3.50. Shown in Fig. 3.63(c) is an NMOS-PMOS cascode. The advantages and disadvantages of these types will be explained later. The structures of Figs. 3.63(b) and (c) are called “folded cascode” stages because the small-signal current is “folded” up [in Fig. 3.63(b)] or down {in Fig. 3.63(c)]. Note that the total bias current in this case must be higher than that in Fig. 3.50 to achieve comparable performance. Itis instructive to examine the large-signal behavior of a folded-cascode stage. Suppose in Fig. 3.63(b), Vin decreases from Vpp to zero. For Vin > Vp — |Vritl Mi is off and Mz carries all of 1? yielding Voy = Vop — 11 Rp. For Vin < Von —|Vruil, Mj turns on in saturation, giving 7 Ww Toa = hh S1epCon (@) (Wp ~ Vin = WVran)?. 6.133) : As Vin drops, Ip2 decreases further, falling to zero if Ip, = I. For this to occur: : Ww FHeCos (¥) (op ~ Via ~ IVrail? = h 6.134) ; Thus, Vint = Voo —lWrml- (3.135) HpCox(W/L); If Vin falls below this level, Zp, tends to be greater than /; and Mf; enters the triode region so as to allow Ip; = 1). The result is plotted in Fig. 3.64. ‘What happens to Vx in the above test? As Ip2 drops, Vx rises, reaching Vs ~ Vriz for |. As My enters the triode region, Vx approaches Vpp. In = If 1 is excessively large, Mz may enter deep triode region, possibly driving /; into the triode region as well.92 Chap.3 Single-Stage Amplifiers Vir Yoo-|rHi] Vin Vint Yoo~|Vru] Vin Figure 3.64 Large-signal characteristics of folded cascode. Example 3.17 Calculate the output impedance of the folded cascode shown in Fig. 3.65 where Ms operates as a current source. oa Rout Vino at, { M2alH Mp Yea lf Ms, = Figure 3.65 Solution Using (3.60), we have Rout = (1 + (m2 + 8mb2)ro2Kroi llro3) + ro2- G.136) ‘Thus, the circuit exhibits an output impedance lower than that of a nonfolded cascode. In order to achieve a high voltage gain, the load of a folded cascode can be implemented as a cascode itself (Fig. 3.66). This structure is studied more extensively in Chapter 9. Throughout this chapter, we have attempted to increase the output resistance of voltage amplifiers so as to obtain a high gain. This may seem to make the speed of the circuit quite susceptible to the load capacitance. However, as explained in Chapter 8, a high output impedance per se does not pose a serious issue if the amplifier is placed in a proper feedback oop. 3.6 Choice of Device Models In this chapter, we have developed various expressions for the properties of single-stage amplifiers. For example, the voltage gain of a degenerated common-source stage can be as simple as — Rp/(Rs + 8m!) or as complex as Eq. (3.71). How does one choose a sufficiently accurate device model or expression?Problems: 93 jure 3.66 Folded cascode with cas- code load, ‘The proper choice is not always straightforward and it is a skill gained by practice, ex- perience, and intuition. However, some general principles in choosing the model for each transistor can be followed. First, break the circuit down into a number of familiar topolo- gies. Next, concentrate on each subcircuit and use the simplest transistor model (a single voltage-dependent current source for FETs operating in saturation) for all transistors. If the drain of a device is connected to a high impedance (e.g., the drain of another), then add To to its model. At this point, the basic properties of most circuits can be determined by inspection. In a second, more accurate iteration, the body effect of devices whose source or bulk is not at ac ground can be included as well. For bias calculations, it is usually adequate to neglect channel-length modulation and body effect in the first pass. These effects do introduce some error but they can be included in the next iteration step—after the basic properties are understood. Tn today’s analog design, simulation of circuits is essential because the behavior of short- channel MOSFETs cannot be predicted accurately by hand calculations. Nonetheless, if the designer avoids a simple and intuitive analysis of the circuit and hence skips the task of gaining insight, then he/she cannot interpret the simulation results intelligently. For this reason, we say, “Don't let the computer think for you.” Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 and assume Vop = 3 V where necessary, All device dimensions are effective values and in microns, 3.1. For the circuit of Fig. 3.9, calculate the small-signal voltage gain if (W/L), = 50/0.5, (W/L)2 = 10/0.5, and Ip, = Ip2 = 0.5 mA. What is the gain if Mz is implemented as a diode-connected PMOS device (Fig. 3.12)? 32, In the circuit of Fig. 3.14, assume (W/L), = 50/0.5,(W/L)2 = $0/2, and Ip: = Ip2 = 0.5 mA when both devices are in saturation, Recall that A 1/L. (a) Calculate the small-signal voltage gain. (b) Calculate the maximum output voltage swing while both devices are saturated.33. 34, 35. 3.6. 37. 38. 39. 3.10. 341. 3.12, 3.3. 3.14. 3.15. 3.16. Chap.3 Single-Stage Amplifiers In the circuit of Fig. 3.3(a), assume (W/L), = 50/0.5, Rp = 2k, and 2 (a) What is the small-signal gain if Mj is in saturation and [p = | mA? (b) What input voltage places My at the edge of the triode region? What is the small-signal gain under this condition? (© What input voltage drives M; into the triode region by 50 mV? What is the small-signal gain under this condition? Suppose the common-source stage of Fig. 3.3(a) is to provide an output swing from 1 V to 2.5 V. Assume (W/L)i = 50/0.5, Rp = 2k, and d = 0. (@) Calculate the input voltages that yield Vour = 1 V and Vour = 2.5 V. (b) Calculate the drain current and the transconductance of Mj for both cases. (©) How much does the small-signal gain, gm Rp, Vary as the output goes from 1 V to 2.5 V? (Variation of small-signal gain can be viewed as nonlinearity.) Calculate the intrinsic gain of an NMOS device and a PMOS device operating in saturation with W/L = 50/0.5 and |Zp| = 0.5 mA. Repeat these calculations if W/L = 100/1 Plot the intrinsic gain of a satuated device versus the gate-source voltage if (a) the drain current is constant, (b) W and L are constant, Plot the intrinsic gain of a saturated device versus W/L if (a) the gate-source voltage is constant, (b) the drain current is constant, AnNMOS transistor with W/L = 50/0.5 is biased with Vq = +1.2 V and Vs = 0. The drain voltage is varied from 0 to 3 V. (a) Assuming the bulk voltage is zero, plot the intrinsic gain versus Vis. (b) Repeat part (a) for a bulk voltage of —1 V. For an NMOS device operating in saturation, plot gm, ro, and gmr'o as the bulk voltage goes from 0 to —co while other terminal voltages remain constant. Consider the circuit of Fig. 3.9 with (W/L); = 50/0.5 and (W/L)z = 10/0.5. Assume A=y=0. (a) At what input voltage is My at the edge of the triode region? What is the small-signal gain under this condition? (b) What input voltage drives My into the triode region by 50 mV? What is the small-signal gain under this condition? Repeat Problem 3.10 if body effect is not neglected. In the circuit of Fig. 3.13, (W/L) = 20/0.5, 1 = 1 mA, and Js = 0.75 mA. Assuming A =0, calculate (W/L)z such that M; is at the edge of the triode region. What is the small- signal voltage gain under this condition? Plot the small-signal gain of the circuit shown in Fig. 3.13 as J goes from 0 to 0.75/. Assume ‘My is always saturated and neglect channel-length modulation and body effect. The circuit of Fig. 3.14 is designed to provide an output voltage swing of 2.2 V with a bias current of 1 mA and a small-signal voltage gain of 100. Calculate the dimensions of My and Ma. Sketch Vour versus Vin for the circuits of Fig. 3.67 as Vin varies from 0 to Vip. Identify important transition points. Sketch Vous versus Vin for the circuits of Fig. 3.68 as Vin varies from 0 to Vpp. Identify important transition points,Problems Yoo Yoo Yop Fo Rp FF Ap My Vout Vout Vout Vine M. Ye Re Vin FA 1 Vi As @ © © Yoo Yoo Ro Vin’ My Yor my Be i Vout out Rs As @ © Figure 3.67 Yoo Yoo Yoo Rp Vino] Ro . Vout Me Vout Vine, Yeh m, Figure 3.6896 Chap. 3 Single-Stage Amplifiers 3.17. Sketch Vous versus Vin for the circuits of Fig. 3.69 as Vin varies from 0 to Vpp. Identify important transition points. Yop Yoo Voor My Vine, Vout Vag Yo te e Yee Vine My @ to) Yoo Yop Vine Ms Vino My Vou sy, Yor me on AB Me Vout Vie, Voom, © @ Figure 3.69 3.18, Sketch /y versus Vx for the circuits of Fig. 3.70 as Vx varies from 0 to Vip. Identify important transition points, Yoo Yoo Ry M2 no Yor E mu, Ra Ix 1 Ix v, Yi Rs= OM™— @ ) © Figure 3.70 3.19, Sketch fy versus Vx for the circuits of Fig. 3.71 as Vx varies from 0 to Vpp. Identify important transition points, 3.20. Assuming all MOSFETs are in saturation, calculate the small-signal voltage gain of each circuit in Fig. 3.72 (4 £0, y =0)Problems Figure 3.71 Yop Yop Yoo a, FR * me vo Vin Ma out Vo R, Kev, ees Vin My Vins + (a) (b) () Yoo Yoo rk, mM, Vout Vout Fo Vino a, Vine my Figure 3.72Chap. 3 Single-Stage Amplifiers 3.21, Assuming all MOSFETs are in saturation, calculate the small-signal voltage gain of each circuit in Fig. 3.73 (2 #0, y = 0). Yoo Yop Yoo Yop M37 IF Y3 Le | Vere Ms M2 "| Yb2 Vout Vout Vout Vine M2 Vine M2 Vine Me Vout y My alE Yer dE, 4m, Voze fe My in 1 L @ ) © @ Yop Yoo Yoo Yor ma Mg, Msg, Ms Vout Vine M2 Vore Me Virb wm thoy, Vout Vout ‘out Vox My, Vine, Vine, Vine, ih © © ro) ) Figure 3.73 3.22. Sketch Vx and Vy as a function of time for each circuit in Fig. 3.74, The initial voltage across C1 is equal to Vp. M; — Voth, Yoo"ee, x Yoel @ Figure 3.74 3.23. In the cascode stage of Fig. 3.50, assume (W/L): = 50/0.5, (W/L)s = 10/0.5, Ip. = Ip2 = 0.5 mA, and Rp = 1k2. (a) Choose Vp such that Mf is 50 mV away from the triode region. (b) Calculate the small-signal voltage gain. (©) Using the value of Vj found in part (a), calculate the maximum output voltage swing. Which device enters the triode region first aS Voy: falls? (@) Calculate the swing at node X for the maximum output swing obtained above.Problems 3.24, 3.25, 3.26. 3.27. 3.28. 3.29, Consider the circuit of Fig. 3.16 with (W/L); = 50/0.5, Rp = 2k, and Rs = 2002. (a) Calculate the small-signal voltage gain if Ip = 0.5 mA. (b) Assuming 4 = y = 0, calculate the input voltage that places Mj at the edge of the triode region, What is the gain under this condition? Suppose the circuit of Fig. 3.15 is designed for a voltage gain of 5. If (W/L), = 20/0.5, Ip. = 0.5 mA, and V, = OV. (@) Calculate the aspect ratio of Ms, (b) What input level places Mj at the edge of the triode region. What is the small-signal gain under this condition? (©) What input level places Mz at the edge of the saturation region? What is the small-signal gain under this condition? Sketch the small-signal voltage gain of the circuit shown in Fig. 3.15 as Vp varies from 0 to Vp. Consider two cases: (a) M; enters the triode region before My is saturated; (b) My enters the triode region after M2 is saturated. A source follower can operate as a level shifter. Suppose the circuit of Fig. 3.30(b) is designed to shift the voltage level by 1 V, ie., Vin — Vout = 1 V. (a) Calculate the dimensions of My and Mp if Ip and A= y =0. (b) Repeat part (a) if y = 0.45 V~! and Vi which Mz remains saturated? [oz = 0.5 mA, Ves2 — Vas = 0.5 V, 2.5 V. What is the minimum input voltage for ‘Sketch the small-signal gain, Vous/ Vin, of the cascode stage shown in Fig. 3.50 as Vp goes from 0 to Vpp. Assume A = y = 0. The cascode of Fig. 3.60 is designed to provide an output swing of 1.9 V with a bias current of 0.5 mA. If y =O and (W/L)\-4 = W/L, calculate Vp), Vs2, and W/L. What is the voltage gain if L = 0.5 um?Chapter 4 Differential Amplifiers ‘The differential amplifier is among the most important circuit inventions, dating back to the vacuum tube era. Offering many useful properties, differential operation has become the dominant choice in today’s high-performance analog and mixed-signal circuits. This chapter deals with the analysis and design of CMOS differential amplifiers. Follow- ing a review of single-ended and differential operation, we describe the basic differential pair, and analyze both the large-signal and the small-signal behavior. Next, we introduce the concept of common-mode rejection and formulate it for differential amplifiers. We then study differential pairs with diode-connected and current-source loads as well as differential cascode stages. Finally, we describe the Gibert cell. 4.1 Single-Ended and Differential Operation 100 A single-ended signal is defined as one that is measured with respect to a fixed potential, usually the ground, A differential signal is defined as one that is measured between two nodes that have equal and opposite signal excursions around a fixed potential. In the strict sense, the two nodes must also exhibit equal impedances to that potential. Fig. 4.1 illustrates the two types of signals conceptually. The “center” potential in differential signaling is called the “common-mode” (CM) level. “! @) ) Figure 4.1 (a) Single-ended and (b) differential signals.Sec.4.1 Single-Ended and Differential Operation 101 An important advantage of differential operation over single-ended signaling is higher immunity to “environmental” noise. Consider the example depicted in Fig. 4.2, where two adjacent lines in a circuit carry a small, sensitive signal and a large clock waveform. Due to capacitive coupling between the lines, transitions on line L2 corrupt the signal on line L;. Now suppose, as shown in Fig. 4.2(b), the sensitive signal is distributed as two equal and opposite phases. If the clock line is placed midway between the two, the transitions disturb the differential phases by equal amounts, leaving the difference intact. Since the common- mode level of the two phases is disturbed but the differential output is not corrupted, we say this arrangement “rejects” common-mode noise. cK Clock Line Signal Line )-to-Line Capacitance () Figure 4.2 (a) Corruption of a signal due to coupling, (b) reduction of coupling by differential operation, Another example of common-mode rejection occurs with noisy supply voltages. In Fig. 4.3(a), if Vop varies by AV, then Voy changes by approximately the same amount, i.e., the output is quite susceptible to noise on Vpp. Now consider the circuit in Fig, 4.3(b), Here, if the circuit is symmetric, noise on Vpp affects Vx and Vy but not Vy — Vv = Vous. ‘Thus, the circuit of Fig. 4.3(b) is much more robust to supply noise.102 Chap. 4 Differential Amplifiers @ b) Figure 4.3 Effect of supply noise on (a) a single-ended circuit, (b) a differential circuit. Thus far, we have seen the importance of employing differential paths for sensitive signals. It is also beneficial to employ differential distribution for noisy lines. For example, suppose the clock signal of Fig. 4.2 is distributed in differential form on two lines (Fig. 4.4). Then, with perfect symmetry, the components coupled from CK and CK to the signal line cancel each other. Figure 4.4 Reduction of coupled noise by differential operation. Another useful property of differential signaling is the increase in maximum achievable voltage swings. In the circuit of Fig. 4.3, for example, the maximum output swing at X or ¥ is equal 0 Vpn — (Ves — Vr), whereas for Vx — Vy, the peak-to-peak swing is equal to 2[Vop ~— (Ves — Vra)l. Other advantages of differential circuits over single-ended counterparts include simpler biasing and higher linearity (Chapter 13). While it may seem that differential circuits occupy twice as much area as single-ended alternatives, in practice this is a minor drawback. Also, the suppression of nonideal effects by differential operation often results in a smaller area than that of a brute-force single-ended design. Furthermore, the numerous advantages of differential operation by far outweigh the possible increase in the area.Sec. 4.2 Basic Differential Pair 103 4.2 Basic Differential Pair How do we amplify a differential signal? As suggested by the observations in the previous section, we may incorporate two identical single-ended signal paths to process the two phases (Fig. 4.5(a)]. Such a circuit indeed offers some of the advantages of differential (b) Figure 4.5 (a) Simple differential circuit, (b) illustration of sensi- tivity to the input common-mode level, signaling: high rejection of supply noise, higher output swings, etc. But what happens if Vint and Vino experience a large common-mode disturbance or simply do not have a well- defined common-mode dc level? As the input CM level, Vin,car, changes, so do the bias currents of M; and Mz, thus varying both the transconductance of the devices and the output CM level. The variation of the transconductance in turn leads to a change in the small-signal gain while the departure of the output CM level from its ideal value lowers the maximum allowable output swings. For example, as shown in Fig. 4.5(b), if the input CM level is excessively low, the minimum values of Vini and Vjq2 may in fact turn off My and M3, leading to severe clipping at the output. Thus, it is important that the bias currents of the devices have minimal dependence on the input CM level. A simple modification can resolve the above issue. Shown in Fig. 4.6, the “differential pair”! employs a current source Iss to make Ip + Ip2 independent of Vin,car. Thus, if Vint = Vina, the bias current of each transistor equals /ss/2 and the output common-mode "Also called a source-coupled pair or (in the British literature) a long-tailed pair.Chap. 4 Differential Amplifiers Figure 4.6 Basic differential pair. level is Vop — Rolss/2. It is instructive to study the large-signal behavior of the circuit for both differential and common-mode input variations. 4.2.1 Qualitative Analysis Let us assume that in Fig. 4.6, Vin ~ Vinz varies from —oo to +00. If Vin is much more negative than Vin2, My is off, Mz is on, and [p2 = Iss. Thus, Vwi = Voo and Vour2 = Von — Rolss. AS Viny is brought closer to Viq2, My gradually turns on, drawing a fraction of Iss from Rp; and hence lowering Voy. Since Ip + Ip2 = Iss, the drain current of Mz decreases and Vou:2 rises. As shown in Fig. 4.7(a), for Vini = Vina, we have Vout! = Vour2 = Von — RpIss/2. As Vin becomes more positive than Vin2, Mj, carries a greater current than does Mz and Voy drops below Voy;2. For sufficiently large Vini — Vina. My “hogs” all of Iss, turning M2 off, As aresult, Vout = Vop — Ross and Vourr = Vov- Fig. 4.7 also plots Vou — Vour2 Versus Vin — Vin2- Voutr—Voutz +Rolsg Yoo - Fo Iss Vina Vina. Vout2 - Ap Yin Vina a @ ) Figure 4.7 input-output characteristics of a differential pair. ‘The foregoing analysis reveals two important attributes of the differential pair. First, the maximum and minimum levels at the output are well-defined (Vpp and Vpp ~ Rolss. respectively) and independent of the input CM level. Second, the small-signal gain (the slope of Vout — Vow2 Versus Vin — Vin) is maximum for Vi) = Vina, gradu- ally falling to zero as |Vini — Vina| increases. In other words, the circuit becomes more nonlinear as the input voltage swing increases. For Vin1 = Vinz, we say the circuit is in equilibrium.Sec. 4.2 tov Ie Basic Differential Pair 105 Now let us consider the common-mode behavior of the circuit. As mentioned earlier, the role of the tail current source is to suppress the effect of input CM level variations on the operation of M, and Mz and the output level. Does this mean that Vi,,cy can assume arbitrarily low or high values? To answer this question, we set Vin1 = Ving = Vin.cat and vary Vinca from 0 to Vpp. Fig. 4.8(a) shows the circuit with /ss implemented by an NFET. Note that the symmetry of the pair requires that Vou = Vou2- Ve '39 {ssp SJ 2° - - ~ tH ~ Vincm am Yincw ia) Minow © Figure 4.8 (a) Differential pair sensing an input common-mode change, (b) equivalent circuit if Mz operates in deep ‘wiode region, (c) common-mode input-output characteristics, What happens if Vin.cy = 0? Since the gate potential of M; and M is not more positive than their source potential, both devices are off, yielding Ip = 0. This indicates that Ms is in deep triode region because Vj is high enough to create an inversion layer in the transistor. With Ip) = Ip2 = 0, the circuit is incapable of signal amplification, and Vourt = Vourr = Voo- Now suppose Vin, car becomes more positive. Modeling M; by a resistor as in Fig. 4.8(b), we note that M, and Mz turn on if Vin,ca > Vr. Beyond this point, Zp, and Ip. continue to increase and Vp also rises [Fig. 4.8(c)]. In a sense, Mj and Mz constitute a source follower, forcing Vp to track Vin.cy. For a sufficiently high Vi,,cy, the drain-source voltage of Ms exceeds Vass — Vrs, allowing the device to operate in saturation. The total current through M; and M; then remains constant. We conclude that for proper operation, Vin,cat > Vest + (Vass — Vru3). ‘What happens if Vin,cu rises further? Since Viyr1 and Vour2 are relatively constant, we expect that M; and Mz enter the triode region if Vin,cay > Vout + Vr = Voo—Rolss/2+ Vru. This sets an upper limit on the input CM level. In summary, the allowable value of106 Chap. 4 Differential Amplifiers Vin.ca is bounded as follows: Vasi + (Voss ~ Vrs) < Vine < min [von = RoE + Ven Vo] 4.) Example 4.1 Sketch the small-signal differential gain of a differential pair as a function of the input CM level. Solution ‘As shown in Fig. 4.9, the gain begins to increase as Vin,car exceeds Vri7. After the tail current source Avi Vow Ve Vin.om Figure 4.9 enters saturation (Vjp,cm = Vj), the gain remains relatively constant, Finally, if Vin,cwy is so high that the input transistors enter the triode region (Vin,car = V2). the gain begins to fall. With our understanding of differential and common-mode behavior of the differential pair, we can now answer another important question: How large can the output voltage swings of a differential pair be? As illustrated in Fig. 4.10, for My and Mp to be saturated, each output can go as high as Vpp but as low as approximately Vinca — Vru. In other Yop Ro Ro Vino Aa ead © {ss Figure 4.10 Maximumallowable out- = put swings in a differential pair. words, the higher the input CM level, the smaller the allowable output swings. For this reason, it is desirable to choose a relatively low Vi,,ca, but the preceding stage may not provide such a level easily. ‘An interesting trade-off exists in the circuit of Fig. 4.10 between the maximum value of Vin,ca and the differential gain. Similar to a simple common-source stage (Chapter 3),Sec. 4.2 Basic Differential Pair 107 the gain of a differential pair is a function of the de drop across the load resistors. Thus, if Rolss/2 is large, Vin.cu must remain close to ground potential. 4.2.2 Quantitative Analysis ‘We now quantify the behavior of a MOS differential pair as a function of the input differential voltage. We begin with large-signal analysis to arrive at an expression for the plots shown in Fig. 4.7. Figure 4.11 Differential pair. For the differential pair in Fig. 4.11, wehave Vout = Vop— RosIp1 and Von = Vop — Ro2lpr, i Ro2Ip2 — Roilp1 = Ro(Ip2 — Ip1) if Roy = Ror = Ro. Thus, we simply calculate Zp, and Jpz in terms of Vin and Vinz, assuming the circuit is symmetric, My and Mz are saturated, and A = 0. Since the voltage at node P is equal to Vint ~ Vesi and Ving — Ves2, Vins — Vina = Vos — Vaso. (4.2) For a square-law device, we have: ID. z= !p os — Vea) = Oy (43) phe ears and, therefore, Th Ves P+ Ven. (4.4) It follows from (4.2) and (4.4) that Vint Vina = [iO | _2to as) HnCox MaCor 41s108 Chap. 4 Differential Amplifiers Our objective is to calculate the differential output current, Zp) ~ Ip2. Squaring the two sides of (4.5) and recognizing that Ip1 + Ip2 = Iss, we obtain 2 (Vint = Vin2)” = Fp Iss — 2VToiTpa). 4.6) HnCox—— L ‘That is, 1 w a gHnCoxF-(WVint — Vina)? — Iss = —2V/TpiTon. an ‘Squaring the two sides again and noting that 411 Jp2 = (Ip: + Ip2)* — (Ip — Im)? = 13s — Up1 — Ip2)?, we arrive at 1 w\ Ww (pi ~ InP = a (mca) (Vint — Vin2)* + IsstnCox (Vint —Vin2y. (4.8) Thus, 1 Ww 41; For ~ box = 5H nCox7-(WVint ~ Vino) | 5 = Vint = Vin2®. 49) Hn Cox As expected, Ip: ~ Ipz is an odd function of Vin — Vin2, falling to zero for Vint = Vin2. AS !Vini ~ Vinal increases from zero, |p — Ipe| also increases because the factor preceding the square root rises more rapidly than the argument in the square root drops,” Before examining (4.9) further, itis instructive to calculate the slope of the characteristic, Le., the equivalent G», of M and Mp. Denoting Ip; ~ Ip2 and Viny — Ving by Ap and AVin, respectively, the reader can show that 4Iss —2av2 dAlp 1 eae eee oe 5 hnCox ; (4.10) BV, 2" OT Iss nya MaCoxW/L : For AVin = 0, Gm = V/HnCox(W/L)Iss. Moreover, since Vout ~ Vou = RpAI = RoGmAVin, we can write the small-signal differential voltage gain of the circuit in the equilibrium condition as [WwW Vdvl = unCox TF IssRo- 4.11) 21t is interesting to note that, even though Zp and p2 are even functions oftheir respective gate-source voltages, Zp1 ~ Ina is an odd function of Vins ~ Vina- This effect is studied in Chapter 13,Sec.4.2 Basic Differential Pair 109 Equation (4.10) also suggests that G,, falls to zero for AVin = V3Is3/inCox W/L). As we will see below, this value of AV, plays an important role in the operation of the circuit, Let us now examine Eq. (4.9) more closely. It appears that the argument in the square root drops to zero for AVin = J4Tss/iinCox W/L), implying that Ap crosses zero at ‘two different values of A V;q. This was not predicted in our qualitative analysis in Fig. 4.7. This conclusion, however, is incorrect. To understand why, recall that (4.9) was derived with the assumption that both M; and Mz are on. In reality, as AVj, exceeds a limit, one transistor carries the entire Jss, turning off the other.’ Denoting this value by A Vint, we have Ip; Iss and AViny = Vosi — Vr because M2 is nearly off. It follows that 21; AVin = | (4.12) Core UnCox L For AVin > AVini, Mz is off and (4.9) does not hold. As mentioned above, Gy, falls to zero for AVin = AVint. Figure 4.12 plots the behavior, ~AVinn +AVint AVin —AVint + Vint AVin (@) (b) Figure 4.12 Variation of drain currents and overall transconductance of a differen- tial pair versus input voltage. Example 4.2 Plot the input-output characteristic of a differential pair as the device width and the tail current vary. Solution Consider the characteristic shown in Fig. 4.13(a). As W/L increases, A Vjn1 decreases, narrowing the input range across which both devices are on (Fig. 4.13(b)]. As Iss increases, both the input range and the output current swing increase (Fig. 4.13(c)]. Intuitively, we expect the circuit to become more linear as Iss increases or W/L decreases. LL The value of AVin, given by (4.12) in essence represents the maximum differential input that the circuit can “handle.” It is possible to relate AVjq1 to the overdrive voltage 3 We neglect subthreshold conduction here.110 Chap. 4 Differential Amplifiers Figure 4.13 of M, and Mz in equilibrium. For a zero differential input, Ip, = Ip. = Iss/2, and hence I; (Ves —Vrua 2 HnCox Thus, the equilibrium overdrive is equal to A Vini/x/2. The point is that increasing A V;qi to make the circuit more linear inevitably increases the overdrive voltage of M; and M. For a given Iss, this is accomplished only by reducing W/L and hence the transconductance of the transistors. ‘We now study the small-signal behavior of differential pairs. As depicted in Fig, 4.14, we apply small signals Vini and Vig2 and assume M; and M; are saturated. What is the dif- ferential voltage gain, Vou:/(Vini — Vin)? Recall from Eq. (4.11) that this quantity equals in CorlssW/LRp. Since in the vicinity of equilibrium, each transistor carries approxi- mately [ss/2, this expression reduces to g» Rp, where gm denotes the transconductance of ‘My and Mp, To arrive at the same result by small-signal analysis, we employ two different methods, each providing insight into the circuit's operation. We assume Rp} = Rp2 = Rp.Sec.4.2 Basic Differential Pair 11 Figure 4.14 Differential pair with ‘small-signal inputs. Figure 4.15 (a) Differential pair sensing one input signal, (b) circuit of (a) viewed as a CS stage degenerated by Mp, (c) equivalent circuit of (b) Method | The circuit of Fig. 4.14 is driven by two independent signals, Thus, the output can be computed by superposition. Let us set Vin2 to zero and find the effect of Vin1 at X and ¥ (Fig. 4.15(a)]. To obtain Vy, we note that M, forms a common-source stage with a degeneration resistance equal to the impedance seen looking into the source of Mz [Fig. 4.15(b)]. Neglecting channel-length112 Chap. 4 Differential Amplifiers Yop Roa’ Y Vourz Ry Mg, IK “Cy : b) Figure 4.16 Replacing Mj by a Thevenin equivalent. modulation and body effect, we have Rs = 1/m (Fig. 4.15(c)] and Vx —Ro +=. (4.14) Va yD a 8m 8m2 To calculate Vy, we note that My drives M; as a source follower and replace Vin and M; by a Thevenin equivalent (Fig. 4.16): the Thevenin voltage Vr = Vini and the resistance Rr = 1/8m1. Here, Mz operates as a common-gate stage, exhibiting a gain equal to vs R 7 2 (4.15) im TT Bn It follows from (4.14) and (4.15) that the overall voltage gain for Vin1 is (Vx — Vy )Ipve to vint (4.16) which, for gmt = &m2 = &m Feduces to (Vx — Vy)IDue to Vint = —8mRdVini- 4.17) By virtue of symmetry, the effect of Vin2 at X and Y is identical to that of Vin except for a change in the polarities: (Vx ~ Vy)Ipue to vine = 8m Rp Vin2- (4.18) Adding the two sides of (4.17) and (4.18) to perform superposition, we have (Vx = Wy )tor ERs (4.19) Vel pee CaySeo.4.2 Basic Differential Pair 113 ‘Comparison of (4.17), (4.18), and (4.19) indicates that the magnitude of the differential gain is equal to gm Rp regardless of how the inputs are applied: in Figs. 4.15 and 4.16, the input is applied to only one side whereas in Fig. 4.14 the input is the difference between two sources. It is also important to recognize that if the output is single-ended, ic., it is sensed between X or ¥ and ground, the gain is halved. Example 4.3 Inthe circuit of Fig. 4.17, Mz is twice as wide as My. Calculate the small-signal gain if the bias values of Vint and Vin2 are equal. Figure 4.17 Solution Ifthe gates of My and Mp are at the same de potential, then Vgs1 = Vos2 and Ip2 = 21p1 = 2Iss/3. Thus, m1 = V2HnCox(W/LISS73 and &m2 = V2inCox2W/L)21s5/3 = 28mi- Following the same procedure as above, the reader can show that 2k, aol 2 (4.20) + Smit 28m 4 = z8miRo- (4.21) Note that, for a given Iss, this value is lower than the gain of a symmetric differential pair (with 2W/L for each device) (Eq. (4.19)] because gm is smaller. How does the gain of a differential pair compare with that of a common-source stage? For a given toral bias current, the value of gq in (4.19) is 1//2 times that of a single transistor biased at /ss with the same dimensions. Thus, the total gain is proportionally less. Equivalently, for given device dimensions and load impedance, a differential pair achieves the same gain as a CS stage at the cost of twice the bias current. Method IIIf a fully-symmetric differential pair senses differential inputs (i.e., the two inputs change by equal and opposite amounts from the equilibrium condition), then the concept of “half circuit” can be applied. We first prove a lemma14 Chap. 4 Differential Amplifiers Lemma. Consider the symmetric circuit shown in Fig. 4.18(a), where D and D2 represent ©) © Figure 4.18 Illustration of why node P is a virtual ground, any three-terminal active device. Suppose Vin changes from Vo to Vo + AVj, and Vin2 from Vo to Vo — AVin (Fig. 4.18(b)]. Then, if the circuit remains linear, Vp does not change. Assume 4, Proof. Let us assume that V, and V2 have an equilibrium value of V, and change by AV; and AV», respectively [Fig. 4.18(c)]. The output currents therefore change by gy AV; and BmAV2. Since I) + fy = Ir, we have Bn AVi + &mAV2 = 0, ie., AV; = —AV>. We also know Vini — Vi = Vin2— V2, and hence Vo + AVin—(Va-+ AVi) = Vo—AVin—(Va+AV2). Consequently, 2AVi, = AV, — AV, = 2AVj. In other words, if Vini and Vina change by +AVj, and —A Vi, respectively, then V; and V2 change by the same values, ie., adifferential change in the inputs is simply “absorbed” by V; and Vp. In fact, since Vp = Vini — Vi, and since V; exhibits the same change as Vin, Vp does not change. a The proof of the foregoing lemma can also be invoked from symmetry. As long as the operation remains linear so that the difference between the bias currents of D; and D> is negligible, the circuit is symmetric. Thus, Vp cannot “favor” the change at one input and “ignore” the other. From yet another point of view, the effect of D; and D, at node P can be represented by Thevenin equivalents (Fig. 4.19). If Vri and Vr2 change by equal and opposite amounts and Rr} and R72 are equal, then Vp remains constant. We emphasize that this is valid if the changes are small such that we can assume Rr; = Rro.* The above lemma greatly simplifies the small-signal analysis of differential amplifiers. ‘As shown in Fig. 4.20, since Vp experiences no change, node P can be considered “ac ground” and the circuit can be decomposed into two separate halves, hence the term “half-circuit concept” [1]. We can write Vx /Vini = —&mRp and Vy/(—Vint) = —8mRps where V;,,; and —Vj,1 denote the voltage change on each side. Thus, (Vy — Vy)/(2Vini) = ~8mRp. ‘it is also possible to derive an expression for the large-signal behavior of Vp and prove that for small Vint ~ Vina, Vp remains constant. We defer this calculation to Chapter 14Sec.4.2 Basic Differential Pair 115 Figure 4.19 Replacing each half of a differential pair by a Thevenin equivalent. Yoo For Apa’ Vouti°—$ XY $0 Voura My Me . 5 Vey dt & % ) Figure 4.20 Application of the half-circuit concept. Example 4.4 Calculate the differential gain of the circuit of Fig. 4.20(a) if 4 # 0. Solution Applying the half-circuit concept as illustrated in Fig. 4.21, we have Vx/Vint = —8m(Rpliro1) and Vy /(—Vinit) = ~8m(Roliro2), thus arriving at (Vx — Vy)/(2Vin1) = —&m(Rollro), where ro =ro1 = ro2. Note that Method I would require lengthy calculations here. Figure 4.21 The half-circuit concept provides a powerful technique for analyzing symmetric differ- ential pairs with fully differential inputs. But what happens if the two inputs are not fully116 Chap.4 Differential Amplifiers My M, + + Yer “OVina = les = @ My M2 + Iss +, © @ Figure 4.22 Conversion of arbitrary inputs to differential and common-mode components. differential [Fig. 4.22(a)]? As depicted in Figs. 4.22(b) and (c), the two inputs Vini and Vin can be viewed as = Vina | Vint + Vina 5 > (4.22) Vin jn ‘in ty fag te (4.23) Since the second term is common to both inputs, we obtain the equivalent circuit in Fig. 4.22(d), recognizing that the circuit senses a combination of a differential input and a common-mode variation. Therefore, as illustrated in Fig, 4.23, the effect of each type of input can be computed by superposition, with the half-circuit concept applied to the differential-mode operation, Example 4.5 ——————__—____ In the circuit of Fig. 4.20(a), calculate Vx and Vy if Vins # —Vin2 and 4 #0.Sec. 4.2 Basic Differential Pair 117 My M2 + +4. Vina= Vint 2 a Iss 7D? @) © Figure 4.23 Superposition for differential and common-mode signals. Solution For differential-mode operation, we have from Fig, 4.24(a) Vins = Vi Vx = -8m(Ro iro.) (4.24) Vina — Vin Vy = ~8n(Roliro2)— (4.25) That is, Vx ~ Vy = —@m(Ro iro Vint ~ Vin2)s (4.26) which is to be expected. Figure 4.24 For common-mode operation, the circuit reduces to that in Fig. 4.24(b). How much do Vy and Vy change as Vin,car changes? If the circuit is fully symmetric and /ss an ideal current source, the118 Chap.4 Differential Amplifiers current drawn by M; and M3 from Rp1 and Rp? is exactly equal to /ss/2 and independent of Vin,cw. ‘Thus, Vx and Vy experience no change as Vin,cay Varies, Interestingly, the circuit simply amplifies the difference between Vin and Vin2 while eliminating the effect of Vin,ca. 4.3 Common-Mode Response An important attribute of differential amplifiers is their ability to suppress the effect of ‘common-mode perturbations. Example 4.5 portrays an idealized case of common-mode response. In reality, neither is the circuit fully symmetric nor does the current source exhibit an infinite output impedance. As a result, a fraction of the input CM variation appears at the output, We first assume the circuit is symmetric but the current source has a finite output impedance, Rss (Fig. 4.25(a)]. As Vin,cw changes, so does Vp, thereby increasing the drain currents of Mj and M; and lowering both Vx and Vy. Owing to symmetry, Vy re- mains equal to Vy and, as depicted in Fig. 4.25(b), the two nodes can be shorted together. Since M, and Mp are now “in parallel,” ie., they share all of their respective terminals, the Vout Vin.cm ofS at, + My Ass © Figure 4.25 (a) Differential pair sensing CM input, (b) simplified version of (a), (c) equivalent circuit of (b).0.4.3 Common-Mode Response 119 circuit can be reduced to that in Fig. 4.25(c). Note that the compound device, M; + M2, has twice the width and the bias current of each of M; and M; and, therefore, twice their transconductance. The CM gain of the circuit is thus equal to Vout Avcu = 7 (427) “cM ae Rp/2 ~~ T/Q8m) + Rss” where g,, denotes the transconductance of each of M; and Mz and 4 = y =0. ‘What is the significance of this calculation? In a symmetric circuit, input CM variations disturb the bias points, altering the small-signal gain and possibly limiting the output voltage swings. This can be illustrated by an example. (4.28) Example 4.6 The circuit of Fig. 4.26 uses a resistor rather than a current source to define a tail current of 1 mA. Figure 4.26 Assume (W/L)},2 = 25/0.5, UnCox = 50 BAIV?, Vr = 0.6% (@) What is the required input CM for which Rss sustains 0.5 V? (b) Calculate Rp for a differential gain of 5. (©) What happens at the output if the input CM level is 50 mV higher than the value calculated in (a)? Solution (@) Since Ip1 = In2 = 0, and Vp = 3 V. .5 mA, we have 2h Vos = Vase = |p + Vrw (429) UaCox =12BV. (4.30) ‘Thus, Vinca = Ves +.0.5 V= 1.73 V. Note that Rss = 500 Q. (b) The transconductance of each device is gm = V2ZinCox(W/L)Ini = 1/(632 2), requiring Rp = 3.16 k& for a gain of 5. Note that the output bias level is equal to Vo — Ip1 Rp = 1.42 V. Since Vin,cw = 1.73 V and Vriz = 0.6 V, the transistors are 290 mV away from the triode region.120 Chap. 4 Differential Amplifiers (©) If Vin,cw increases by 50 mV, the equivalent circuit of Fig. 4.25(c) suggests that Vy and Vy drop by Rp/2 AV x. = AVincw = (4.31) ae OM Rss + 1/em) “ = 50 mV x 1,94 (4.32) = 96.8 mV. (4.33), Now, Mi and M2 are only 143 mV away from the triode region because the input CM level has increased by $0 mV and the output CM level has decreased by 96.8 mV. VL The foregoing discussion indicates that the finite output impedance of the tail current source results in some common-mode gain in a symmetric differential pair. Nonetheless, this is usually a minor concern. More troublesome is the variation of the differential output as a result of a change in Vip,cq, an effect that occurs because in reality the circuit is not fully symmetric, i.e., the two sides suffer from slight mismatches during manufacturing. For example, in Fig. 4.25(a), Rp may not be exactly equal to Rp2. We now study the effect of input common-mode variation if the circuit is asymmetric and the tail current source suffers from a finite output impedance. Suppose, as shown in Fig. 4.27, Roi = Rp and Rp2 = Rp + ARp, where ARp denotes a small mismatch and Figure 4.27 Common-mode response in the presence of resistor mismatch. the circuit is otherwise symmetric. What happens to Vx and Vy as Vip.ca increases? Since M, and My are identical, Ip, and Ip2 increase by [2m /(I + 28m Rss)]AVin,cu, but Vy. and Vy change by different amounts: 8m AVx = —AVin.cm ——"—_R, (4.34) x MT 2g Ros? (4.34) AVy = ~AVin.cu 2 >— (Ro + ARp). (4.35) 1+ 2gmRss Thus, acommon-mode change at the input introduces a differential component at the output. We say the circuit exhibits common-mode to differential conversion. This is a critical problem because if the input of a differential pair includes both a differential signal andSec. 4.3, Common-Mode Response 121 common-mode noise, the circuit corrupts the amplified differential signal by the input CM change. The effect is illustrated in Fig. 4.28. Figure 4.29. CM response with finite tail capacitance, In summary, the common-mode response of differential pairs depends on the output impedance of the tail current source and asymmetries in the circuit, manifesting itself through two effects: variation of the output CM level (in the absence of mismatches) and conversion of input common-mode variations to differential components at the output. In analog circuits, the latter effect is much more severe than the former. For this reason, the common-mode response should usually be studied with mismatches taken into account. How significant is common-mode to differential conversion? We make two observations. First, as the frequency of the CM disturbance increases, the total capacitance shunting the tail current source introduces larger tail current variations. Thus, even if the output resistance of the current source is high, common-mode to differential conversion becomes significant at high frequencies. Shown in Fig. 4,29, this capacitance arises from the parasitics of the current source itself as well as the source-bulk junctions of M; and Mz. Second, the asymmetry in the circuit stems from both the load resistors and the input transistors, the latter contributing a typically much greater mismatch. Let us now study the asymmetry resulting from mismatches between Mj and Mz in Fig. 4.30(a). Owing to dimension and threshold voltage mismatches, the two transistors122 Chap.4 Differential Amplifiers @ ©) Figure 4.30 (a) Differential pair sensing CM input, (b) equivalent circuit of (a). carry slightly different currents and exhibit unequal transconductances. To calculate the gain from Vin,cu to X and Y, we use the equivalent circuit in Fig, 4.30(b), writing Ip: = Smi(Vincm — Vp) and In2 = 8m2(Vincm — Vp). That is, (8mi + 8m2)(Vinom — Ve)Rss = Vp, (4.36) and (Smi + 8m2)Rss oe 437 Gt + Bna)R55+ 1 CM eS) We now obtain the output voltages as Vx. ‘Bmi(Vin,om — Ve)Ro (4.38) =8mt = Te Ro vin 4.39) (ma + Bna)Rss- 17M 439) and Vy = —8m2(Vin.cm — Ve)Ro (4.40) a RoVincm- (4.41) ~ Gm + &m2)Rs5 +1 ‘The differential component at the output is therefore given by Bm ~ 8m2 Vy — Vy = ———8™\— 8m? avs cy. (4.42) Gent + Gna) Rog-F PEM In other words, the circuit converts input CM variations to a differential error by a factorSec. 4.3 Common-Mode Response : 123 equal to AgmRo Acu-pau = ————"—> __, up (Bmi + 8m2)Rss +1 (4.43) where Acy—pu denotes common-mode to differential-mode conversion and Ag, = 8m — Bm2- Example 4.7 ‘Two differential pairs are cascaded as shown in Fig. 4.31. Transistors M3 and Mg suffer from a gm Figure 4.31 mismatch of Agm, the total parasitic capacitance at node P is represented by Cp, and the circuit is, otherwise symmetric. What fraction of the supply noise appears as a differential component at the output? Assume A = y = 0. Solution Neglecting the capacitance at nodes A and B, we note that the supply noise appears at these nodes with no attenuation, Substituting 1/(Cps) for Rss in (4.43) and taking the magnitude, we have Asm AcM-pa| = ——— oP (4.44) 1 1+ (gma + &ma)?| —— [tem ner] ‘The key point is that the effect becomes more noticeable as the supply noise frequency, «increases. —— For meaningful comparison of differential circuits, the undesirable differential com- ponent produced by CM variations must be normalized to the wanted differential output resulting from amplification, We define the “common-mode rejection ratio” (CMRR) as. Apu CMRR =|?" _ Acu-pM : (4.45)124 Chap.4 Differential Amplifiers If only gm mismatch is considered, the reader can show from the analysis of Fig. 4.15 that Rod Bmi + 8m2 + 48mi8m2Rss Aoul = (4.46) Mow = TE mi + BnadRss where it is assumed Vinj = —Vin2, and hence Simi + 8m2 + 48mi8maRss CMRR = S217 Bn F*Bm mass 447 2m (4.47) 8m w SP (14 2enRss)y 4.48 Bam’ + 28mRss), (4.48) where gm denotes the mean value, i.€., gm = (8m + &m2)/2. In practice, all mismatches must be taken into account. 4.4 Differential Pair with MOS Loads ‘The load of a differential pair need not be implemented by linear resistors. As with the common-source stages studied in Chapter 3, differential pairs can employ diode-connected or current-source loads (Fig. 4.32). The small-signal differential gain can be derived using Yoo @ o Figure 4.32 Differential pair with (a) diode-connected and (b) current- source loads. the half-circuit concept. For Fig. 4.32(a), Ay = ~8nn (Spe lrow ror) (4.49) = —SnN (4.50) np where subscripts N and P denote NMOS and PMOS, respectively. Expressing gun and 8np in terms of device dimensions, we have 451)Sec. 4.4 Differential Pair with MOS Loads 125 For Fig. 4.32(b), we have Av = —8nn(ronllrop). (4.52) In the circuit of Fig. 4.32(a), the diode-connected loads consume voltage headroom, thus creating a trade-off between the output voltage swings, the voltage gain, and the input CM range. Recall from Eq. (3.35) that, for given bias current and input device dimensions, the circuit's gain and the PMOS overdrive voltage scale together. To achieve a higher gain, (W/L)p must decrease, thereby increasing |Vcsp — Vrip| and lowering the CM level at nodes X and Y. In order to alleviate the above difficulty, part of the bias currents of the input transistors can be provided by PMOS current sources, Illustrated in Fig. 4.33, the idea is to lower the &m of the load devices by reducing their current rather than their aspect ratio. For example, Figure 4.33 Addition of current sources to increase the voltage gain. if Ms and Mg carry 80% of the drain current of M; and Mz, the current through M3 and My is reduced by a factor of five. For a given |Vesp — Vrizp|. this translates to a factor of five reduction in the transconductance of Ms and Mz because the aspect ratio of the devices can be lowered by the same factor. Thus, the differential gain is now approximately five times that of the case with no PMOS current sources. ‘The small-signal gain of the differential pair with current-source loads is relatively low— in the range of 10 to 20 in submicron technologies. How do we increase the voltage gain? Borrowing ideas from the amplifiers in Chapter 3, we increase the output impedance of both PMOS and NMOS devices by cascoding, in essence creating a differential version of the cascode stage introduced in Chapter 3. The result is depicted in Fig. 4.34(a). To calculate the gain, we construct the half circuit of Fig. 4.34(b), which is similar to the cascode stage of Fig. 3.60. Thus, [Av] © 8mil(8msro3?01)Il(Gms"osto7)): (4.53) Cascoding therefore increases the differential gain substantially but at the cost of consuming more voltage headroom. As a final note, we should mention that high-gain fully differential amplifiers require a means of defining the output common-mode level. For example, in Fig. 4.32(b), the output126 Chap.4 Differential Amplifiers Yoo Yea Mz Yoo Ms Vout Vir My Vino me, o) Figure 4.34 (a) Cascode differential pair, (b) half circuit of (a). ‘common-mode level is not well-defined whereas in Fig. 4.32(a), diode-connected transistors define the output CM level as Vpp — Vosp. We return to this issue in Chapter 9. 4.5 Gilbert Cell Our study of differential pairs reveals two important aspects of their operation: (1) the small-signal gain of the circuit is a function of the tail current and (2) the two transistors ina differential pair provide a simple means of steering the tail current to one of two destinations. By combining these two properties, we can develop a versatile building block. ‘Suppose we wish to construct a differential pair whose gain is varied by a control voltage. This can be accomplished as depicted in Fig. 4.35(a), where the control voltage defines the Yoo Yoo Yoo Rp. Ro Ro Fo . fe Ro Vout Voute (b) Figure 4.35 (a) Simple VGA, (b) two stages providing variable gain.Sec.4.5 Gilbert Cell 127 tail current and hence the gain. In this topology, Ay = Vous/ Vin Varies from zero (if Ins = 0) to a maximum value given by voltage headroom limitations and device dimensions. This circuit is a simple example of a “variable-gain amplifier” (VGA), VGAs find application in systems where the signal amplitude may experience large variations and hence requires inverse changes in the gain, Now suppose we seek an amplifier whose gain can be continuously varied from anegative value to a positive value, Consider two differential pairs that amplify the input by opposite gains [Fig. 4.35(b)]. We now have Vouri/Vin = ~&mRp and Vou2/ Vin = +8m Rp, where &m denotes the transconductance of each transistor in equilibrium. If f; and J vary in opposite directions, so do |Vouri/Vin| and |Voua/ Vinl- But how should Voy11 and Voyr2 be combined into a single output? As illustrated in Fig. 4.36(a), the two voltages can be summed, producing Vou: = Vout -+ Vour2 = A1Vin-+ A2Vin, Veontt © @ Figure 4.36 (a) Summation of the output voltages of two amplifiers, (b) summation in the current domain, (c) use of Ms-Ms to control the gain, (d) Gilbert cell128 Chap.4 Differential Amplifiers where A; and A2 are controlled by Veonr1 and Veonr2, Tespectively. The actual implementation is in fact quite simple: since Vou = RoJp1 — Rolv2 and Vowr2 = Rola — Rolps, We have Vourt + Vour2 = Ro(Ip1 + !p4)— Rop2 + Ips). Thus, rather than add Vouri and Vour2, we simply short the corresponding drain terminals to sum the currents and subsequently generate the output voltage (Fig. 4.36(b)]. Note that if; = 0, then Vou = +8mRpVin and if Fy = 0, then Vou = —8mRp Vin. For I) = 1, the gain drops to zero. In the circuit of Fig. 4.36(b), Veont1 and Veonr2 must vary J, and /2 in opposite directions such that the gain of the amplifier changes monotonically. What circuit can vary two currents in opposite directions? A differential pair provides such a characteristic, leading to the topology of Fig. 4.36(c). Note that for a large |Veonr1 — Veonr2|, all of the tail current is steered to one of the top differential pairs and the gain from V;, to Voy: is atits most positive or most negative value. For Veonti = Veont2, the gain is zero. For simplicity, we redraw the circuit as shown in Fig, 4.36(d). Called the “Gilbert cell” [2], this circuit is widely used in ‘many analog and communication systems. In a typical design, M,-Mg are identical and so are Ms and Mg. Example 4.8 Explain why the Gilbert cell can operate as an analog voltage multiplier. Solution Since the gain of the circuit is a function of Veonr = Veonri — Veonr2s We have Vout = Vin + fVcont) Expanding f(Veont) in a Taylor series and retaining only the first-order term, crVeonr, We have Vout = Vin Veont. Thus, the circuit can multiply voltages. This property accompanies any voltage-controlled variable-gain amplifier. As with a cascode structure, the Gilbert cell consumes a greater voltage headroom than asimple differential pair does. This is because the two differential pairs M,-Mz and M3-Mz are “stacked” on top of the control differential pair. To understand this point, suppose the differential input, V;q, in Fig. 4.36(d) has a common-mode level Vow, in- Then, Va = Vp = Vew.in—Vsi, where Mi-Mz are assumed identical. For Ms and Mg to operate in saturation, the CM level of Veonrs Veatconts Must be such that Vew.con < Vemsin — Vosi + Vriss- Since Vos — Vrs. is roughly equal to one overdrive voltage, we conclude that the control CM level must be lower than the input CM level by at least this value. In arriving at the Gilbert cell topology, we opted to vary the gain of each differential pair through its tail current, thereby applying the control voltage to the bottom pair and the input signal to the top pairs. Interestingly, the order can be exchanged while still obtaining a VGA. Illustrated in Fig. 4.37(a), the idea is to convert the input voltage to current by means of Ms and Mg and route the current through M,-Ms to the output nodes. If, as shown in Fig. 4.37(b), Veon: is very positive, then only My and Mz are on and Vou = 8ms,6RpVin. Similarly, if Veon: is very negative (Fig, 4.37(c)], then only Ms and M, are on and Vous = —8ns,6RpVin- If the differential control voltage is zero, then Voy; = 0. The input differential pair may incorporate degeneration to provide a linear voltage-to-current conversion.Problems (b) © Figure 4.37 (a) Gilbert cell sensing the input voltage by the bottom differential pair, (b) signal path for very positive Veonr, (C) signal path for very negative Veont. Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 and assume Vo 4. 43, 44. 45. 4.6. 47. 48. 3. V where necessary. All device dimensions are effective values and in microns Suppose the total capacitance between adjacent lines in Fig. 4.2 is 10 fF and the capacitance from the drains of My and Mp to ground is 100 fF. (a) What is the amplitude of the glitches in the analog output in Fig. 4.2(a) for a clock swing of 3 V? (b) Ifin Fig. 4.2(b), the capacitance between L1 and Lz is 10% less than that between L1 and Ls, what is the amplitude of the glitches in the differential analog output for a clock swing of 3V? ‘Sketch the small-signal differential voltage gain of the circuit shown in Fig. 4.8(a) if Vp varies from 0 to 3 V. Assume (W/L)1-s = 50/0.5, Vinca = 1.3 V, and Vp = 1 V. Construct the plots of Fig. 4,8(c) for a differential pair using PMOS transistors. In the circuit of Fig. 4.10, (W/L), = 50/0.5 and Iss = 0.5 mA. (a) What is the maximum allowable output voltage swing if Vin,ca = 1.2 V2 (b) What is the voltage gain under this condition? A differential pair uses input NMOS devices with W/L = $0/0.5 and a tail current of | mA. (a) What is the equilibrium overdrive voltage of each transistor? (b) How is the tail current shared between the two sides iff Vint ~ Ving = 50 mA? (©) What is the equivalent G», under this condition? (@) For what value of Vini — Vina does the Gy drop by 10%? By 90%? Repeat Problem 4.5 with W/L = 25/0.5 and compare the results. Repeat Problem 4.5 with a tail current of 2 mA and compare the results. Sketch Zp: and [pz in Fig, 4.17 versus Vin1 — Vin2- For what value of Vin — Ving are the two ‘currents equal?130 49. 4.10. 4.1. 4.12. 4.13. 414, 4.15. 4.16. 4.17, 4.18. 4.19. 4.20, 4.21, Chap.4 Differential Amplifiers Consider the circuit of Fig. 4.28, assuming (W/L)1,2 = 50/0.5 and Rp = 2 kX. Suppose Rss represents the output impedance of an NMOS current source with (W/L)ss = 50/05 and a drain current of 1 mA. The input signal consists of Vin,oo = 10 mV pp and Vin, = 1.5 V +Vp(t), where V,(t) denotes noise with a peak-to-peak amplitude of 100 mV. Assume AR/R = 0.5%. (a) Calculate the output differential signal-to-noise ratio, defined as the signal amplitude di- vided by the noise amplitude. (b) Calculate the CMRR. Repeat Problem 4.9 if AR = 0 but My and Mz suffer from a threshold voltage mismatch of 1 mV, Suppose the differential pair of Fig. 4.32(a) is designed with (W/L)1,2 = 50/0.5, (W/L)s,. 10/0.5,and Iss = 0.5 mA. Also, Iss is implemented with an NMOS device having (W/L)ss = 30/0. (a) What are the minimum and maximum allowable input CM levels ifthe differential swings at the input and output are small? (b) For Vin,cur = 1.2 V, sketch the small-signal differential voltage gain as Vpp goes from 0 t03V. In Problem 4.11, suppose My and Mz have a threshold voltage mismatch of 1 mV. What is the CMRR? In Problem 4.11, suppose Ws = 10 zm but Ws = 11 wm. Calculate the CMRR. For the differential pairs of Fig. 4.32(a) and (b), calculate the differential voltage gain if Iss = 1 mA, (W/L)1.2 = 50/0.5, and (W/L)3,4 = 50/1. What is the minimum allowable input CM level if Zs requires at least 0.4 V across it? Using this value for Vin,car, calculate the maximum output voltage swing in each case. In the circuit of Fig. 4.33, assume Iss = 1 mA and W/L = 50/0.5 for all of the transistors. (a) Determine the voltage gain. (b) Calculate Vp such that Ips = Ing = 0.8(Iss/2). (© If Jss requires a minimum voltage of 0.4 V, what is the maximum differential output swing? Assuming all ofthe circuits shown in Fig. 4.38 are symmetric, sketch Vous a8 (a) Vin and Vina vary differentially from zero to Vpp, and (b) Vint and Vin2 are equal and they vary from zero 0 Vpp. Assuming all of the circuits shown in Fig, 4.39 are symmetric, sketch Vour aS (a) Vint and Vina vary differentially from zero to Vp, and (b) Vini and Vig are equal and they vary from zero to Vop. Assuming all of the transistors in the circuits of Figs. 4.38 and 4,39 are saturated and 2 # 0, calculate the small-signal differential voltage gain of each circuit. Consider the circuit shown in Fig. 4.40. (a) Sketch Vous a8 Vini and Vino Vary differentially from zero to Vp. (b) If 4 = 0, obtain an expression for the voltage gain. What is the voltage gain if W3,4 = 0.8Ws.6? For the circuit shown in Fig. 4.41, (a) Sketch Vour, Vx, and Vy as Vin and Vin2 vary differentially from zero to Vp. (b) Calculate the small-signal differential voltage gain Assuming no symmetry in the circuit of Fig. 4.42 and using no equivalent circuits, calculate the small-signal voltage gain (Vous)/(Vint — Vina) if A = Oand y # 0.130 49. 4.10. 4.1. 4.12. 4.13. 414, 4.15. 4.16. 4.17, 4.18. 4.19. 4.20, 4.21, Chap.4 Differential Amplifiers Consider the circuit of Fig. 4.28, assuming (W/L)1,2 = 50/0.5 and Rp = 2 kX. Suppose Rss represents the output impedance of an NMOS current source with (W/L)ss = 50/05 and a drain current of 1 mA. The input signal consists of Vin,oo = 10 mV pp and Vin, = 1.5 V +Vp(t), where V,(t) denotes noise with a peak-to-peak amplitude of 100 mV. Assume AR/R = 0.5%. (a) Calculate the output differential signal-to-noise ratio, defined as the signal amplitude di- vided by the noise amplitude. (b) Calculate the CMRR. Repeat Problem 4.9 if AR = 0 but My and Mz suffer from a threshold voltage mismatch of 1 mV, Suppose the differential pair of Fig. 4.32(a) is designed with (W/L)1,2 = 50/0.5, (W/L)s,. 10/0.5,and Iss = 0.5 mA. Also, Iss is implemented with an NMOS device having (W/L)ss = 30/0. (a) What are the minimum and maximum allowable input CM levels ifthe differential swings at the input and output are small? (b) For Vin,cur = 1.2 V, sketch the small-signal differential voltage gain as Vpp goes from 0 t03V. In Problem 4.11, suppose My and Mz have a threshold voltage mismatch of 1 mV. What is the CMRR? In Problem 4.11, suppose Ws = 10 zm but Ws = 11 wm. Calculate the CMRR. For the differential pairs of Fig. 4.32(a) and (b), calculate the differential voltage gain if Iss = 1 mA, (W/L)1.2 = 50/0.5, and (W/L)3,4 = 50/1. What is the minimum allowable input CM level if Zs requires at least 0.4 V across it? Using this value for Vin,car, calculate the maximum output voltage swing in each case. In the circuit of Fig. 4.33, assume Iss = 1 mA and W/L = 50/0.5 for all of the transistors. (a) Determine the voltage gain. (b) Calculate Vp such that Ips = Ing = 0.8(Iss/2). (© If Jss requires a minimum voltage of 0.4 V, what is the maximum differential output swing? Assuming all ofthe circuits shown in Fig. 4.38 are symmetric, sketch Vous a8 (a) Vin and Vina vary differentially from zero to Vpp, and (b) Vint and Vin2 are equal and they vary from zero 0 Vpp. Assuming all of the circuits shown in Fig, 4.39 are symmetric, sketch Vour aS (a) Vint and Vina vary differentially from zero to Vp, and (b) Vini and Vig are equal and they vary from zero to Vop. Assuming all of the transistors in the circuits of Figs. 4.38 and 4,39 are saturated and 2 # 0, calculate the small-signal differential voltage gain of each circuit. Consider the circuit shown in Fig. 4.40. (a) Sketch Vous a8 Vini and Vino Vary differentially from zero to Vp. (b) If 4 = 0, obtain an expression for the voltage gain. What is the voltage gain if W3,4 = 0.8Ws.6? For the circuit shown in Fig. 4.41, (a) Sketch Vour, Vx, and Vy as Vin and Vin2 vary differentially from zero to Vp. (b) Calculate the small-signal differential voltage gain Assuming no symmetry in the circuit of Fig. 4.42 and using no equivalent circuits, calculate the small-signal voltage gain (Vous)/(Vint — Vina) if A = Oand y # 0.4.22. 4.23, 4.24, 4.28, 4.26. Ry Ry Vino [t-° Vina Yosh Ms © Figure 4.38 Due to a manufacturing defect, a large parasitic resistance has appeared between the drain and source terminals of Mj in Fig. 4.43. Assuming 4 = y = 0, calculate the small-signal gain, common-mode gain, and CMRR. Due to a manufacturing defect, a large parasitic resistance has appeared between the drains of ‘My and Mg in the circuit of Fig. 4.44. Assuming 4 = y = 0, calculate the small-signal gain, ‘common-mode gain, and CMRR. In the circuit of Fig. 4.45, all of the transistors have a W/L of $0/0.5 and M3 and Mg are to operate in deep triode region with an on-resistance of 2k. Assuming Ips = 20 wA and 4= y = 0, calculate the input common-mode level that yields such resistance. Sketch Voyri and Vour2 a8 Vini and Vinz vary differentially from 0 to Vpp. In the circuit of Fig. 4.32(b), (W/L)1—4 = 50/0.5 and Iss = 1 mA. (a) What is the small-signal differential gain? () For Vin,cur = 1.5 V, what is the maximum allowable output voltage swing? In the circuit of Fig, 4.33, assume Ms and Mg have a small threshold voltage mismatch of AV and Iss has an output impedance Rss. Calculate the CMRR. 131132 Figure 4.40 (b)Figure 4.41 Yoo For Foz Vino 2 Vina Ret Asp © Iss = Figure 4.42 Figure 4.43 133134 Chap. 4 Yoo Fo Ro Ms Yor Ma | b-* Mina Vee Ms = Figure 4.44 Figure 4.45 References Differential Amplifiers 1. P.R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., New Yor Wiley, 1993. 2. B. Gilbert, “A Precise Four-Quadrant Multiplier with Subnanosecond Response,” IEEE J. Solid- State Circuits, vol. SC-3, pp. 365-373, Dec. 1968.Chapter 5 Passive and Active Current Mirrors Our study of single-stage and differential amplifiers in Chapters 3 and 4 points to the wide usage of current sources. In these circuits current sources act as a large resistor without consuming excessive voltage headroom. We also noted that MOS devices operating in saturation can act as a current source. Current sources find other applications in analog design as well. For example, some digital-to-analog (D/A) converters employ an array of current sources to produce an analog output proportional to the digital input. Also, current sources, in conjunction with “current mirrors,” can perform useful functions on analog signals. This chapter deals with the design of current mizrors as both bias elements and signal Processing components. Following a review of basic current mirrors, we study cascode mirror operation. Next, we analyze active current mirrors and describe the properties of differential pairs using such circuits as loads. 5.1 Basic Current Mirrors Fig. 5.1 illustrates two examples where a current source proves useful, From our study in Chapter 2, recall that the output resistance and capacitance and the voltage headroom of a current source trade with the magnitude of the output current. In addition to these issu: several other aspects of current sources are important: supply, process, and temperature dependence, output noise current, and matching with other current sources. We postpone noise and matching considerations to Chapters 7 and 13, respectively. How should a MOSFET be biased so as to operate as a stable current source? To gain a better view of the issues, let us consider the simple resistive biasing shown in Fig. 5.2. Assuming M, is in saturation, we can write ln bye, © (2 fou SH Con (ee Vop — vr) : GD) This expression reveals various dependencies of J,4; upon the supply, process, and tem- perature. The overdrive voltage is a function of Vpp and Vrj; the threshold voltage may 135136 Chap.5 Passive and Active Current Mirrors Yoo Yoo che" care" 4 fF 4 It Vout 7 Vout ma Viney Vine, Iss > Yor - @ (b) Figure 5.1. Applications of current sources. Yoo = Figure 5.2 Definition of current by re- sistive divider. vary by 100 mV from wafer to wafer. Furthermore, both ix and Vry exhibit temperature dependence. Thus, [ous is poorly defined. The issue becomes more severe as the device is biased with a smaller overdrive voltage, e.g., to consume less headroom. With a nominal overdrive of, say, 200 mY, a 50-mV error in Vr results in a 44% error in the output current. It is important to note that the above process and temperature dependencies exist even if the gate voltage is not a function of the supply voltage. In other words, if the gate-source voltage of a MOSFET is precisely defined, then its drain current is not! For this reason, we ‘must seek other methods of biasing MOS current sources. The design of current sources in analog circuits is based on “copying” currents from a reference, with the assumption that one precisely-defined current source is already available. While this method may appear to entail an endless cycle, it is carried out as illustrated in Fig. 5.3. A relatively complex circuit—sometimes requiring external adjustments—is used Figure 5.3 Use of a reference to gen- erate various currents.Sec.5.1 Basic Current Mirrors 137 to generate a stable reference current, [gg r, which is then copied to many current sources in the system. We study the copying operation here and the reference generator circuit in Chapter 11. How do we generate copies of a reference current? For example, in Fig. 5.4, how do we guarantee [oy = Irer? For a MOSFET, if Ip = f(Vos), where f(-) denotes the vy ® tree Tout Figure 5.4 Conceptual means of copying currents. functionality of /p versus Vgs, then Vos = f~'(Ip). That is, if a transistor is biased at Irer, then it produces Ves = f—'(Iper) (Fig. 5.5(a)]. Thus, if this voltage is applied to the gate and source terminals of a second MOSFET, the resulting current is Igy = Ff~'Urer) = Inee (Fig. 5.5(b)]. From another point of view, two identical MOS devices that have equal gate-source voltages and operate in saturation carry equal currents (if . = 0). Yop Yoo t ‘rer ner J fo a i | w M. Mile (pee) toy, OF ot = (a) (b) Figure 5.5 (2) Diode-connected device providing inverse function, (b) basic current mirror. The structure consisting of M; and M; in Fig. 5.5(b) is called a “current mirror.” In the general case, the devices need not be identical. Neglecting channel-length modulation, we can write 1 w Ter = =MnCox | — os — Vr 5.2) REF = 5h (F), ves THY (3.2) 1 Ww lou = 5HnCoe (2), (Wes —Vew, 63)138 Chap.5 Passive and Active Current Mirrors obtaining (W/L)o = Wp (54) The key property of this topology is that it allows precise copying of the current with no dependence on process and temperature. The ratio of J4y: and Jge-r is given by the ratio of device dimensions, a quantity that can be controlled with reasonable accuracy. Example 5.1 In Fig. 5.6, find the drain current of Mg if all of the transistors are in saturation. igure5.6 Solution We have [p2 = Irer((W/L)2/(W/L)]. Also, |Ip3| = \Ip2| and Ipg = Ipa{(W/L)4/(W/L)s], Thus, |Zps| = aBIaer, where « = (W/L)2/(W/L); and B = (W/L)4/(W/L)s. Proper choice of « and 6 can establish large or small ratios between Ip, and [xz r. Forexample,a = 6 = Syieldsamag- nification factor of 25. Similarly, a = B = 0.2.can be utilized to generate a small, well-defined current. Current mirrors find wide application in analog circuits, Fig. 5.7 illustrates a typical case, where a differential pair is biased by means of an NMOS mirror for the tail current source and a PMOS mirror for the load current sources. The device dimensions shown establish a Yoo: ae 7 Figure 5.7 Current mirrors used to bias a differential amplifier.Sec.5.2 Cascode Current Mirrors 139 drain current of 0.4/y in Ms and Mg, reducing the drain current of Mg and Mz and hence increasing the gain, Current mirrors usually employ the same length for all of the transistors so as to minimize errors due to the side-diffusion of the source and drain areas (Lp). For example, in Fig. 5.7, the NMOS current sources must have the same channel length as Mo. This is because if, Lérawn's, say, doubled, then Leys = Lrawn—2Lp isnot. Furthermore, the threshold voltage of short-channel devices exhibits some dependence on the channel length (Chapter 16). Thus, current ratioing is achieved by only scaling the width of transistors. We should also mention that current mirrors can process signals as well. In Fig. 5.5(b), for example, if Iger increases by AT, then Ioy; increases by AI(W/L)2/(W/L). That is, the circuit amplifies the small-signal current if (W/L)s/(W/L), > 1 (but at the cost of proportional multiplication of the bias current). Example 5.2, pe Calculate the small-signal voltage gain of the circuit shown in Fig. 5.8. Figure 5.8 Solution ‘The small-signal drain current of My is equal to gm Vin. Since Ip2 = Ipy and Ip3 = Ip2(W/L)s/ (W/L)a, the small-signal drain current of Ms is equal to m1 Vin(W/L)3/(W/L)2, yielding a voltage gain of gm1RL(W/L)s/(W/L)2. ey 5.2 Cascode Current Mirrors In our discussion of current mirrors thus far, we have neglected channel length modulation. In practice, this effect results in significant error in copying currents, especially if minimum- length transistors are used so as to minimize the width and hence the output capacitance of the current source. For the simple mirror of Fig. 5.5(b), we can write Ini L w Cox (3) (Ves — Vr) +2Vps1) (3.5) 1 As explained in Chapter 18, the widths are actually scaled by placing multiple unit transistors in parallel rather than making a device wider.140 Chap.5 Passive and Active Current Mirrors 1 Ww 2 ; Ip = 5HnCox (>) (Vas — Vruy'(1 + 4¥ps2), (5.6) 2 L), and hence ton _ (W/Ln 1+ Vos2 Ip. (W/L), 1+AVpsi" (5.7) While Vosi = Vest = Vesa» Vos2 may not equal Ves2 because of the circuitry fed by Mp. For example, in Fig. 5.7, the potential at node P is determined by the input common-mode level and the gate-source voltage of My and Mp, and it may not equal Vx. In order to suppress the effect of channel-length modulation, a cascode current source ‘can be used. As shown in Fig. 5.9(a), if Vp is chosen such that Vy = Vx, then Inu; closely tracks [gzp. This is because, as described in conjunction with Fig. 3.61, the cascode device “shields” the bottom transistor from variations in Vp. With the aid of Fig. 3.23, the reader can prove that AVy * AVp/[(gma + 8ms3)Fo3]- Thus, we say that Vy remains close to Vy and hence Ip2 © Ip; with high accuracy. Such accuracy is obtained at the cost of the voltage headroom consumed by M3. Note that, while L; must be equal to Z2, the length of ‘Ms need not be equal to Ly and L2. Yoo Yoo a P rer InergP ‘DD Fout Tout N Iner@) Yooh Ms My de, Molt hs x Y x Vesot Vx x Y My mM, wade a, JHE, @ ) © Figure5.9 (a)Cascode current source, (b) modification of mirror circuit to generate the cascode bias voltage, (c) cascode current mirror. How do we generate V; in Fig. 5.9(a)? Since the objective is to ensure Vy = Vx, we must guarantee Vp — Voss = Vx or V; = Vass + Vx. This result suggests that if a gate-source voltage is added to Vx, the required value of V; can be obtained. Depicted in Fig. 5.9(b), the idea is to place another diode-connected device, Mo, in series with My, thereby generating a voltage Vy = Voso + Vx. Proper choice of the dimensions of Mo with respect to those of M3 yields Voso = Voss. Connecting node NV to the gate of My as shown in Fig. 5.9(c), we have Voso + Vx = Voss + Vy. Thus, if (W/L)3/(W/L)o = (W/L)2/(W/L)1, then Voss = Veso and Vy = Vy. Note that this result holds even if Mo and M; suffer from body effect.Sec.5.2 Cascode Current Mirrors 141 Example 5.3 In Fig. 5.10, sketch Vx and Vy as a function of rer. If [ger requires 0.5 V to operate as a current source, what is its maximum value? po JRE VyoVy, Fout Molt Ms x Y Vey ™,dKH—E mu, t i ner @ © Figure 5.10 Solution Since Mz and M3 are properly ratioed with respect to My and Mo, we have Vy = Vx © ViREF inCox(W7E)1] + Vr. The behavior is plotted in Fig. 5.10(b). To find the maximum value of Ire-r, we note that Vw = Vaso + Vesi 6.8) 2; L L ENO @ ]emenn 0 21; L L Yop - (ime [ (%), o (%), | —Vrno— Vrii =0.5V. 6.10) HnCox (Vop — 0.5 V = Vrno ~ Veni)? 2 (VLIW )o + VIEW)? Thus, and hence TREFmax = (1D While operating as a current source with high output impedance and accurate value, the topology of Fig. 5.9(c) nonetheless consumes substantial voltage headroom. For simplicity, let us neglect the body effect and assume all of the transistors are identical. Then, the142 Chap.5 Passive and Active Current Mirrors minimum allowable voltage at node P is equal to Vy ~ Vr = Vaso + Vest — Vr .12) = (Ves0 — Vru) + (Ves — Vr) + Vru, 6.13) i.e., two overdrive voltages plus one threshold voltage, How does this value compare with that in Fig. 5.9(a) if Vs could be chosen more arbitrarily? As shown in Fig. 3.51, V, could be so low that the minimum allowable voltage at P is merely two overdrive voltages. Thus, the cascode mirror of Fig. 5.9(c) “wastes” one threshold voltage in the headroom. This is because Vps2 = Vos2, whereas Vps2 could be as low as Ves: — Vr while maintaining ‘Mp in saturation. Fig. 5.11 summarizes our discussion. In Fig. 5.11(a), Vs is chosen to allow the lowest possible value of Vp but the output current does not accurately track [ger because M; and ‘Mp sustain unequal drain-source voltages. In Fig. 5.11(b), higher accuracy is achieved but the minimum level at P is higher by one threshold voltage. P Yoo ,¥ lout lner + Tree Vp AE Ves-Vrn x ma|Y | My + Ves- Yiu Ves - @ Figure 6.11 (a) Cascode current source with minimum headroom voltage, (b) head- room consumed by a cascode mirror. Before resolving this issue, it is instructive to examine the large-signal behavior of a cascode current source. Example 5.4 ——————__ In Fig. 5.12(a), assuming all of the transistors are identical, sketch Fy and Vg as Vx drops from a large positive value. Solution For Vx > Vy ~ Vr, both Mz and My are in saturation, Iy = Irer and Vp = Va. As Vx drops, which transistor enters the triode region frst, Ms or Mz? Suppose Mz enters the triode region before ‘M3 does. For this to occur, Vps2 must drop and, since Vso is constant, so must [p2. This means Voss increases while [p3 decreases, which is not possible if Ms is still in saturation. Thus, M; enters the triode region first. As Vx falls below Vy — Vriz, Ms enters the triode region, requiring a greater gate-source overdrive to carry the same current, Thus, as shown in Fig. 5.12(b), Vs begins to drop, causing [p2 and henceSec. 5.2 Cascode Current Mirrors 143 Yoo JRE Mo A My Y-Viis Vy Oo) Figure 5.12 1x to decrease slightly. As Vx and Vg decrease further, eventually we have Vp < V4 —Vry,and Mz centers the triode region. At this point, p2 begins to drop sharply. For Vx = 0, Ix = 0, and Mp and ‘Ms operate in deep triode region. Note that as Vx drops below Viv ~ Vy, the output impedance of the cascode falls rapidly because gm3 degrades in the triode region. _ In order to eliminate the accuracy-headroom trade-off described above, we first study the modification depicted in Fig. 5.13(a). Note that this circuit is in fact a cascode topology with its output shorted to its input. How can we choose V; so that both Mj and M2 are in saturation? We must have V5 — Vri2 < Vx(= Vsi) for Mz to be saturated and Vest — Vrii < Va(= Vo — Vos2) for M; to be saturated. Thus, Vasa + (Vosi — Veit) = Vo $ Ves + Vina. (5.14) A solution exists if Ves2 + (Vast ~ Vent) $ Vest + rua, ies if Ves ~ Vena < Vr. ‘We must therefore size M such that its overdrive voltage remains less than one threshold voltage. Now consider the circuit shown in Fig. 5.13(b), where all of the transistors are in saturation and proper ratioing ensures that Ves, = Voss. If Vo = Vosr + (Vest ~ Vr) = Vasa + (Vass — Vri3), then the cascode current source M3-M, consumes min- imum headroom (the overdrive of M3 plus that of Ms) while M; and M3 sustain equal144 Chap.5 Passive and Active Current Mirrors TRer @ o) Figure 5.13 Modification of cascode mirror for low-voltage operation. drain-source voltages, allowing accurate copying of rer. We call this a “low-voltage cascode.” ‘We must still generate Vj. For minimal voltage headroom consumption, Va = Vosi ~ Vrui and hence V must be equal to (or slightly greater than) Vosx + (Vasi — Vrin)- Fig. 5.14(a) depicts an example, where Ms generates Voss * Vosq and Mg together with Ry produces Voss = Voss — Roly © Vesi — Vr. Some inaccuracy nevertheless arises because Ms does not suffer from body effect whereas Mz does. Also, the magnitude of Ry is not well-controlled. Yoo ty My x yee im, Yb ie Mg (O) Figure 5.14 Generation of gate voltage Vp for cascode mirrors. ‘An alternative circuit is shown in Fig. 5.14(b), where the diode-connected transistor My has a large W/L so that Vos1 © Vru7. That is, Voss © Voss — Vrar7 and hence Vs = Vass + Vase — Vru7. While requiring no resistors, this circuit nonetheless suffers from similar errors due to body effect. Some margin is therefore necessary to ensure My and My remain in saturation,Seo. 5.3 Active Current Mirrors 145 Figure 5.15 Low-voltage cascode us- ing a source follower level shifter. We should mention that low-voltage cascodes can also be biased using source followers. Shown in Fig. 5.15, the idea is to shift the gate voltage of M3 down with respect to Vy by interposing a source follower. If Ms is biased at a very low current density, Ip /(W/L), then its gate-source voltage is approximately equal to Vr, i.e., Viv © Vy — Vrws, and Va = Vosi + Veso ~ Vrs — Voss (5.15) Vest — Vrs. 6.16) implying that My is at the edge of the triode region. In this topology, however, Vps2 # Vost» introducing substantial mismatch. Also, if the body effect is considered for Mo, Ms, and Ms, itis difficult to guarantee that Mz operates in saturation. We should mention that, in addition to reducing the systematic mismatch due to channel-length modulation, the cascode structure also provides a high output impedance. 5.3 Active Current Mirrors As mentioned earlier and exemplified by the circuit of Fig. 5.8, current mirrors can also process signals, i.e., operate as “active” elements, Particularly useful is a type of mirror topology used in conjunction with differential pairs. In this section, we study this circuit and its properties. First, let us examine the circuit shown in Fig. 5.16, where M; and M, are identical. Neglecting channel-length modulation, we have [oy = Tig, ie., with the direction shown for Jin and 441, the circuit performs no inversion. From the small-signal point of view, if Tin increases by AT, 50 does Lous. ‘Now consider the differential amplifier of Fig. 5.17(a), where a current source ina mirror arrangement serves as the load and the output is single-ended. What is the small-signal gain, Ay = Vou/ Viny of this circuit? We calculate Ay using two different approaches,’ assuming y =O for simplicity. Note that, owing to the lack of symmetry, the half-circuit concept cannot be applied here.146 Chap.5 Passive and Active Current Mirrors Figure 5.16 Current mirror process- ing a signal @ Yoo Toa a Rout roe py, M2 at Smt (b) © Figure 5.17 (a) Differential pair with current-source load, (b) circuit for cal- culation of Gm, (c) circuit for calculation of Rous. Writing |Ay| = GmRou and recognizing from Fig. 5.17(b) that Gm = lout/Vin = (8m1Vin/2)/ Vin = 8mi/2, We simply need to compute Rous. As illustrated in Fig. 5.17(c), for this calculation, Mp is degenerated by the source output impedance, 1/gm1, of Mi, thereby exhibiting an output impedance equal to (1 + gm27o2)(1/8mi.2) + 702 = 2roz + 1/Bmi ©Sec. 5.3 Active Current Mirrors 147 2ro2. Thus, Row * (2ro2)||roa, and lAel © 4 (2roa)iirosl 6.17) Interestingly, if ros + 00, then Ay > gmiro2. This can be explained by the second approach. Figure 6.18 Circuit for calculation of Ve/Vin- In our second approach, we calculate Vp/Viq and Vour/Vp and multiply the results to obtain Vou:/Vin- With the aid of Fig. 5.18, Vp Reg Ve . _ Bm (5.18) where R,, denotes the resistance seen looking into the source of Mz. Since the drain of M; is terminated by a relatively large resistance, ro4, the value of Req must be obtained from Eq. 3.110): a 6.19) Bm2ro2 La eS) . (5.20) 702 It follows that ros 142 Vee rou mgt 6.21) Ton Note that if ros > 0, Vp/Vin > 1/2 and if rox > 00, then Vp/Vin > 1 We now calculate Vaus/Vp while taking ro into account. From Fig. 5.19, Vout _ 1+ 8m: Vou _ 1+ &na¥o2 Dy Vp 142 4148 Chap.5 Passive and Active Current Mirrors a Figure 5.19 Circuit for calculation of Vous / VP. x Bnaton ~ 5.23) Toa From (5.21) and (5.23), we have 1 ro4 Ve ron, 8maror a ee (5.24) Vin 74 108 1 4 Foe Toz To4 _ BmForros = 5.25) 2ro2 + roa oa = 2 1@roniiros- 5.26) In the circuit of Fig. 5.17, the small-signal drain current of M; is “wasted.” As concep- tually shown in Fig, 5.20(a), it is desirable to utilize this current with proper polarity at the output. This can be accomplished as depicted in Fig. 5.20(b), where M3 and M, are idemtical. To see how M3 enhances the gain, suppose the gate voltage of M, increases by a small amount, increasing Ip by AJ and decreasing Ip) by AJ. Since |{p3| and hence Ips| also increase by AJ, we observe that the output voltage tends to increase through two mechanisms: the drain current of M, drops and the drain current of Mg rises.> In contrast to the circuit of Fig. 5.17, here Mg assists Mz with the voltage change at the output. This configuration is called a differential pair with active current mirror. An important property of this circuit is that it converts a differential input to a single-ended output. She reader may wonder how this is possible if KCL requires that Ip 3.2 clarifies this issue. ‘Its also called a differential pair with active load. Ipa|. The explanation in ExampleSec. 5.3 Active Current Mirrors 149 Figure 5.20 (a) Concept of combining the drain currents of My and Mp, (b) realization of (a). 5.3.1 Large-Signal Analysis Let us study the large-signal behavior of the circuit. To this end, we replace the ideal tail current source by a MOSFET as shown in Fig. 5.21(a). If Viq1 is much more negative than Vinz, IM) is off and so are Mg and Mg. Since no current can flow from Vpp, both Mp and Ms operate in deep triode region, carrying zero current. Thus, Vour = 0.5 As Vini approaches Vinz, M; turns on, drawing part of Ips from Ms and turning Ms on. The output voltage then depends on the difference between Ips and Ipz. For a small difference between Viqi and Vina, both Mz and M, are saturated, providing a high gain [Fig. 5.21(b)]. As Vini becomes more positive than Vina, Zot, |Zps|,and |ps| increase and J;p2 decreases, eventually driving Ms into the triode region. If Vin1 ~ Vin2 is sufficiently large, Mz tums off, Mg operates in deep triode region with zero current, and Vey, = Vpp. Note that if Vinr > Vr + Vrn, then My enters the triode region. The choice of the input common-mode voltage of the circuit is also important, For M3 to be saturated, the output voltage cannot be less than Vj,,ca# ~ Vr. Thus, to allow maximum. output swings, the input CM level must be as low as possible, with the minimum given by Vasi.2+ Voss,min. The direct relationship between the input CM level and the output swing in this circuit is a critical drawback. What is the output voltage of the circuit when Vins = Vino? With perfect symmetry, Vou = Ve = Von — Vesa]. This can be proved by contradiction as well. Suppose, for example, that Voy < Ve. Then, due to channel-length modulation, My must carry a greater current than Mp (and M, a greater current than Ms). In other words, the total current through 4M, is greater than half of Iss. But this means that the total current through M; also exceeds Jss/2, Violating the assumption that M, carries more current than M3. In reality, however, asymmetries in the circuit may result in a large deviation in Vout, possibly driving Mz or ‘Mg into the triode region. For example, if the threshold voltage of Mz is slightly smaller SIE Vin is greater than one threshold voltage with respect o ground, Ms may draw a small current from Mi, raising Vou slightly150 Chap.5 Passive and Active Current Mirrors Yoo Ms M4 F 2 Vout 5 High Gain Yin 2 Vine Region Yortams Vini-Vine @ ) Figure 5.21 (a) Differential pair with active current mirror and realistic current source, (b) large-signal input-output characteristic. than that of Mj, the former carries a greater current than the latter even with Vint = Vina» causing Voy: to drop significantly. For this reason, the circuit is rarely used in an open-loop configuration to amplify small signals, Example 5.5. ee Assuming perfect symmetry, sketch the output voltage of the circuit in Fig. 5.22(a) as Vpp varies from 3 V to zero. Assume that for Vp = 3 V all of the devices are saturated. Yoo My My F Vout +15 Vo] he 1.5 Yes @ CO) Figure 5.22 Solution For Vpp = 3 V, symmetry requires that Vou = Ve. As Vpp drops, so do Vp and Vour with a slope close to unity [Fig. 5.22(b)}. As Ve and Voy fall below +1.5 V —Vryn, My and Mp enter the triode region, but their drain currents are constant if Ms is saturated. Further decrease in Vpp and hence Vp and Vous causes Vos1 and Ves2 to increase, eventually driving Ms into the triode region.Sec.5.3 Active Current Mirrors 151 ‘Thereafter, the bias current of all of the transistors drops, lowering the rate at which Vow decreases. For Vo < {Vrip|, we have Vous = 0. 5.3.2 Small-Signal Analysis ‘We now analyze the small-signal properties of the circuit shown in Fig. 5.21(a), assuming Y = Ofor simplicity. Can we apply the half-circuit concept to calculate the differential gain here? As illustrated in Fig. 5.23, with small differential inputs, the voltage swings at nodes Yoo Ms Ma uv Vk pov" N ® Iss Figure 5.23 Asymmetric swings in a differential pair with active current * mirror. X and ¥ are vastly different. This is because the diode-connected device Ms yields a much lower voltage gain from the input to node X than that from the input to node ¥. As a result, the effects of Vy and Vy at node P (through ro; and ro, respectively) do not cancel each other and this node cannot necessarily be considered a virtual ground. We compute the gain using two different approaches. In the first approach, we write |Ay| = GyRour and obtain Gm and Rou separately. For the calculation of G,,, consider Fig. 5.24(a). The circuit is not quite symmetric but tb) Figure 5.24 (a) Circuit for calculation of Gy, (b) circuit of (a) with node P grounded,152 Chap.5 Passive and Active Current Mirrors because the impedance seen at node X is relatively low and the swing at this node small, the current returning from X to P through ro: is negligible and node P can be viewed as a virtual ground (Fig. 5.24(b)]. Thus, Zoi = |Zosl = (pal = $m1,2Vin/2 and To2 = —8m1,2Vin/2, yielding Lye = ~8mi,2Vin and hence |Gm| = mi,2. Note that, by virtue of active current mirror operation, this value is twice the transconductance of the circuit of Fig. 5.17(b). Calculation of Roy: is less straightforward. We may surmise that the output resistance of this circuit is equal to that of the circuit in Fig. 5.17(c), namely, (2r92)||704. In reality, how- ever, the active mirror operation yields a different value because when a voltage is applied to the outputto measure Ry, the gate voltage of M, does not remain constant. Rather than draw the entire equivalent circuit, we observe that, for small signals, Iss is open [Fig. 5.25(a)], any current flowing into M, must flow out of Mz, and the role of the two transistors can be @ & Figure 5.25 (a) Circuit for calculating Rous, (b) substitution of M; and M2 by a resistor. represented by a resistor Ryy = 2ro1,2 [Fig. 5.25(b)]. Asa consequence, the current drawn from Vy by Rxy is mirrored by Ms into M, with unity gain. We can therefore write: (5.27) where the factor 2 accounts for current copying action of M3 and Ms. For 2ro1,2 > (1/ms)|lro3, We have Rou * roallros. (5.28) ‘The overall voltage gain is thus equal to |Ay| = GmRow = 8mi,2(roallros), somewhat higher than that of the circuit in Fig. 5.17(a). ‘The second approach to calculating the voltage gain of the circuits illustrated in Fig. 5.26, providing more insight into the operation. We substitute the input source and My and Mz by a Thevenin equivalent. As illustrated in Fig. 5.27(a), for the Thevenin voltage calcula- tion, node P is a virtual ground because of symmetry, and a half-circuit equivalent yields Veq = 8mi.2701.2Vin- Moreover, the output resistance is Reg = 2ro,2. From Fig. 5.27(b),Seo.5.3 Active Current Mirrors 153 (@) (b) Figure 5.27 (a) Calculation of the Thevenin equivalent voltage, (b) simplified circuit ‘we note that the current through Reg is mn Vin In = i 7 ee (5.29) roi + Ir o12 + Fo |r The fraction of this current that flows through 1/gq3 is mirrored into My with unity gain, Thatis, Vout = 8mi. paar . te Vous (530) 2ro2+—liros 78 18m3 Tos 8n3 Assuming 2ro1,2 >> (1/gms,a)llro3.4s we obtain Vout _ 8mi Vou _ 8mi.2F 03.80 01.2 531) Vin roi +1034 = 8m1.2(Fo1.2/|"03.4)- (5.32)154 Chap.5 Passive and Active Current Mirrors Example 5.6 Calculate the small-signal voltage gain of the circuit shown in Fig. 5.28. How does the performance of this circuit compare with that of a differential pair with active mirror? Yoo Yew, Vout Vine my = Figure 5.28 Solution We have Ay = gmi(roillro2), similar to the value derived above. For given device dimensions, this circuit requires half of the bias current to achieve the same gain as a differential pair. However, advantages of differential operation often outweigh the power penalty. The above calculations of the gain have assumed an ideal tail current source, In re- ality, the output impedance of this source affects the gain, but the error with respect to 8mi,2("o1.2||"03,4) is relatively small. 5.3.3 Common-Mode Properties Let us now study the common-mode properties of the differential pair with active current mirror. We assume y = 0 for simplicity and leave a more general analysis including body effect for the reader. Our objective is to predict the consequences of a finite output impedance in the tail current source. As depicted in Fig. 5.29, a change in the input CM level leads to Figure 5.29 Differential pair with ac- tive current mirror sensing a common- mode change. a change in the bias current of all of the transistors. How do we define the common-mode gain here? Recall from Chapter 4 that the CM gain represents the corruption of the outputSec. 5.3 Active Current Mirrors 155 signal of interest due to variations of the input CM level. In the circuits of Chapter 3, the output signal was sensed differentially and hence the CM gain was defined in terms of the output differential component generated by the input CM change. In the circuit of Fig. 5.29, on the other hand, the output signal of interest is sensed with respect to ground. Thus, we define the CM gain in terms of the single-ended output component produced by the input CM change: AVout AVincot Acu = (5.33) To determine Aci, we observe that if the circuit is symmetric, Vou = Vr for any input CM level. For example, as Vin,cy increases, Vr drops and so does Vous. In other words, nodes F and X can be shorted [Fig. 5.30(a)], resulting in the equivalent circuit shown Yoo joa 29msall 2 Ve fout fora 2 @) (b) Figure 5.30 (a) Simplified circuit of Fig. 5.29, (b) equivalent circuit of (a). in Fig. 5.30(b). Here, M, and M2 appear in parallel and so do M3 and Ms. It follows that _ 1 Jrosa 2 Acm © (5.34) R: Pama * Rss Sh = Sant (5.35) + 2gm12Rss Bm3.4"156 Chap.5 Passive and Active Current Mirrors where we have assumed 1/(2gm3.4) ro3,4 and neglected the effect of r93,2/2. The CMRR is then given by (5.36) (5.37) = (1+ 28m1.2Rss)8m3,4(7o1,21I"03,4)- (5.38) Equation (5.35) indicates that, even with perfect symmetry, the output signal is corrupted by input CM variations, a drawback that does not exist in the fully differential circuits of Chapter 3. High-frequency common-mode noise therefore degrades the performance considerably as the capacitance shunting the tail current source exhibits a lower impedance. Example 5.7 ‘The CM gain of the circuit of Fig. 5.29 can be shown to be zero by a (flawed) argument. As shown in Fig. 5.31(a), if Vin,cw introduces a change of AJ in the drain current of each input transistor, then AVin,cm° ) Figure 5.31 Ip3 also experiences the same change and so does Ips. Thus, Ma seemingly provides the additional current required by Mp, and the output voltage need not change, i.c., Acar = 0. Explain the flaw in this proof. Solution The assumption that A pg completely cancels the effect of Ap? is incorrect. Consider the equivalent circuit shown in Fig. 5.31(b). Since AVr = Ah (z m3 >) 2 (5.39)Sec. 5.3 Active Current Mirrors 157 we have [A lpal = eneAVe 6.40) = sus 641) This current and Als (= Al = A) give a net voltage change equal to AVour = (AN 8ns: ee ~ Ahyros (5.42) in37O8 —t ros, 5.43) Bmaros + 170% Co which is equal to the voltage change at node F. Itis also instructive to calculate the common-mode gain in the presence of mismatches. As an example, we consider the case where the input transistors exhibit slightly different transconductances [Fig. 5.32(a)]. How does Vou depend on Vinca’? Since the change at ) Figure 6.32 Differential pair with gq mismatch. nodes F and X is relatively small, we can compute the change in [p, and Ip2 whileneglecting the effect of ro, and roz. As shown in Fig. 5.32(b), the voltage change at P can be obtained by considering M; and M2 as a single transistor (in a source follower configuration) with a transconductance equal t0 gmt + Bnav iit, R AV = AVin.ct Rss + T . (5.44) Smt + &m2158 Chap.5 Passive and Active Current Mirrors | where body effect is neglected. The changes in the drain currents of M; and M; are therefore given by Alpi = 8mi(AVincw — AVe) (5.45) ___AVincm Smt (546 =e ae - eaeeae Bmi + 8m2 Se Bn + Bm Alp2 = 8m2(AVin.cm — AVp) (5.47) AVincm ___&m2 ‘ (5.48) Rss + ~ Bini + Bm2 Bmi + &m2 The change Ap, multiplied by (1/gn3)\'03 Yields |A pl = &nal(1/gms)llro3]Ap1. The difference between this current and A /p) flows through the output impedance of the circuit, which is equal to ro4 because we have neglected the effect of ro; and ro2: Bmi A Vino Tos 8m2AVin,oot AVous = | —2™ eM _ eee chee 1+ (Bm + &m2)Rss 1+ (8mi + 8m2)Rss ro ros (5.49) 3 + — — AVinemt (8m1 = 8m2)F03 ~ &m2/ Bm’ 1+ (mi + 8m2)Rss ‘04+ (5.50) ros+ Bm3 If ros > 1/Bmay we have AVour_, (Bm1 — Sm2)FO3 ~ 8m2/Bm3 (5.51) AVincwt 1+ (mi + &m2)Rss Compared to Eq. (5.35), this result contains the additional term (gm — 8n2)"o3 in the numerator, revealing the effect of transconductance mismatch on the common-mode gain. Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 and assume Vp = 3 V where necessary. All device dimensions are effective values and in microns, S.A In Fig. 5.2, assume (W/L); = 50/0.5, 4 = 0, Lou = 0.5 mA, and My is saturated. (a) Determine Ro/Ri (b) Calculate the sensitivity of Zour to Vp, defined as lou /8V pp and normalized t0 Toys. (e) How much does Jour change if Vr changes by 50 mV? (d) If the temperature dependence of jy is expressed as jy, T~*/? but Viv is independent of temperature, how much does Jou vary if T changes from 300°K to 370°K?Problems 5.2, 53. 54. 55. 5.6. 57. 5.8. 59. 5.10, 5.1. 5.12. 5.13, 5.14, 5.5, 5.16. 159 (©) Whatis the worst-case change in Jour if Vop changes by 10%, Vr by 50 mV, and T from 300°K to 370°K? Consider the circuit of Fig. 5.6. Assuming Ire r is ideal, sketch Lous versus Vp 88 Vpp varies from 0 t0 3 V. In the circuit of Fig. 5.7, (W/L) = 10/0.5,(W/L)p = 10/0.5, and Iner = 100 wA. The input CM level applied to the gates of M; and M; is equal to 1.3 V. (a) Assuming A = 0, calculate Vp and the drain voltage of the PMOS diode-connected tran- sistors. (b) Now take channel-length modulation into account to determine /y and the drain current of the PMOS diode-connected transistors more accurately. Consider the circuit of Fig. 5.8; sketch Voys versus Vpp as Vpp varies from 0 t0 3 V. Consider the circuit of Fig. 5.9(a), assuming (W/L),-3 = 40/0.5, Irer = 0.3mA, andy = 0. (@) Determine Vp such that Vx = Vr. (b) If Vs deviates from the value calculated in part (a) by 100 mV, what is the mismatch between Lou; and Ieer? (©) If the circuit fed by the cascode current source changes Vp by 1 V, how much does Vy change? The circuit of Fig. 5.13 is designed with (W/L)i,2 = 20/0.5, (W/L)s, 100 a. (a) Determine Vx and the acceptable range of Vp. (b) Estimate the deviation of Zour from 300 A if the drain voltage of Mg is higher than Vx by lV. ‘The circuit of Fig. 5.17(a) is designed with (W/L)i-¢ = 50/0.5 and Iss = 2h (a) Calculate the small-signal voltage gain, (b) Determine the maximum output voltage swing if the input CM level is 1.3 V. Consider the circuit of Fig. 5.22(a) with (W/L)1-5 = 50/0.5 and Ips = 0.5 mA. (a) Calculate the deviation of Vous from Ve if |r a3] is 1 mV less than |Vr zal. (b) Determine the CMRR of the amplifier. Sketch Vy and Vy asa function of Vip for each circuit in Fig. 5.33, Assume the transistors in each circuit are identical. = 60/0.5, and Ire = 0.5 ma. Sketch Vx and Vy as a function of Vip for each circuit in Fig. 5.34. Assume the transistors in each circuit are identical. For each circuit in Fig. 5.35, sketch Vy and Vy asa function of Vj for0 < Vi < Vpp. Assume the transistors in each circuit are identical For each circuit in Fig. 5.36, sketch Vy and Vy as a function of Vj for0 < Vi < Vpp. Assume the transistors in each circuit are identical, For each circuit in Fig. 5.37, sketch Vx and Vy as a function of Irer- For the circuit of Fig. 5.38, sketch Jqur, Vx, Va, and Vg as a function of (a) Ire, (b) Vo. In the circuit shown in Fig. 5.39, a source follower using a wide transistor and a smalll bias current is inserted in series with the gate of Ms so as to bias Mz at the edge of saturation. Assuming Mo-Ms are identical and 2 # 0, estimate the mismatch between Joy and [per if (@)y =0,(b)y 40. ‘Sketch Vx and Vy as a function of time for each circuit in Fig. 5.40, Assume the transistors i each circuit are identical.160 Chap.5 Passive and Active Current Mirrors x y x y My My Ma My @ ©) Yoo Ry Ry Ry Ay x y x y My My My My Ry . = Ry @ © Figure 5.33 @ (b) © Figure 5.35Problems Yoo ie > m4 m x 7 M2 My @ 161 yy Ter x M2 © Figure 5.36 Vpn Yop Sree Ry Jer Ms x = x Y Me My M2 My ® © Figure 5.37 Figure 5.38 Figure 5.39162 Chap.5 Passive and Active Current Mirrors Yop Yoo Yoo Jer Ry Tree Ry x y x Y M2, My M2 My 0 1 t oO ae . 7 ae Cc; ¢, a) ® ‘ © ~ Vop Ry Yo, R, = Ry x G JY x y My Ms Malthe, = = Mo, | = 1 c @ ©) Figure 5.40 5.17, Sketch Vx and Vy as a function of time for each circuit in Fig. 5.41. Assume the transistors in each circuit are identical Yoo Yoo Ry Ry Y - Sper Yous |rer Vem, rer! x v, Yoo, Ma, My x M. cy = Te My, My &) (a) © Figure 5.41 5.18, Sketch Vy and Vy as a function of time for each circuit in Fig. 5.42. Assume the transistors in each circuit are identical. 5.19, The circuit shown in Fig. 5.43 exhibits a negative input capacitance. Calculate the input impedance of the circuit and identify the capacitive component.Problems 163 Yoo + Y orc, MS © Figure 5.43 5.20. Due to a manufacturing defect, a large parasitic resistance, Rj, has appeared in the circuits of Fig. 5.44. Calculate the gain of each circuit. Figure 5.44 5.21, In digital circuits such as memories, a differential pair with active current mirror is used to convert small differential signal to a large single-ended swing (Fig. 5.45). In such applications, s desirable that the output levels be as close to the supply rails as possible. Assuming moderate differential input swings (¢.g., AV = 0.1 V) around a common-mode level Vin,car and a high gain in the citcuit, explain why Viain depends on Vin,cm164 Chap.5 Passive and Active Current Mirrors Venax Vinin Figure 5.45 5.22. Sketch Vx and Vy for each circuit in Fig. 5.46 as a function of time. The initial voltage across C1 is shown, Yoo M3 Ma x Y +15V P Oss © Yoo Ms Ma x Y © Figure 5.46 5.23. If in Fig. 5.47, AV is small enough that all of the transistors remain in saturation, determine the time constant and the initial and final values of Vousoblems 7 Figure 5.47Chapter 6 Frequency Response of Amplifiers Our analysis of simple amplifiers has thus far focussed on low-frequency characteristics, neglecting the effect of device and load capacitances. In most analog circuits, however, the speed trades with many other parameters such as gain, power dissipation, and noise. It is therefore necessary to understand the frequency response limitations of each circuit, In this chapter, we study the response of single-stage and differential amplifiers in the frequency domain. Following a review of basic concepts, we analyze the high-frequency behavior of common-source and common-gate stages and source followers. Next, we deal with cascode and differential amplifiers. Finally, we consider the effect of active current mirrors on the frequency response of differential pairs. 6.1 General Considerations 6.1.1 Miller Effect An important phenomenon that occurs in many analog (and digital) circuits is related to “Miller Effect,” as described by Miller in a theorem. Miller’s Theorem. If the circuit of Fig. 6.1(a) can be converted to that of Fig. 6.1(b), then Z, = Z/(1 — Ay) and Z, = Z/(1 — A,!), where Ay = Vy/Vx. 2; Z, @ © Figure 6.1 Application of Miller effect to a floating impedance. 166$Sec.6.1 General Considerations 167 Proof. The current flowing through Z from X to ¥ is equal to (Vy — Vy)/Z. For the two circuits to be equivalent, the same current must flow through Z,. Thus, Vx — Vy “= (6.1) thatis, 62) Similarly, (63) a Example 6.1 sider the circuit shown in Fig. 6.2(a), where the voltage amplifier has a negative gain equal to —A otherwise ideal. Calculate the input capacitance of the circuit. Ce vi 2, 22 @) (b) © Figure 6.2 Solution Using Miller's theorem to convert the circuit to that shown in Fig. 6.2(b), we have Z = 1/(Crs) and Zi =[1/(Crs)]/(l + A). That is, the input capacitance is equal to Cr(1 + A). Why is Cy multiplied by 1 + A? Suppose, as depicted in Fig. 6.2(c), we measure the input capacitance by applying a voltage step at the input and calculating the charge supplied by the voltage source. A step equal to AV at X resultsin achange of —AAV at, yielding atotal change of (1-+A)AV in the voltage across Cz. Thus, the charge drawn by Cr from Vig is equal to (1+ A)CrAV and the equivalent input capacitance equal to (I + A)Cr- a168 Chap.6 Frequency Response of Amplifiers tis important to understand that (6.2) and (6.3) hold if we know a priori that the circuit of Fig. 6.1(a) can be converted to that of Fig, 6.1(b). That is, Miller’s theorem does not stipulate the conditions under which this conversion is valid. If the impedance Z forms the only signal path between X and ¥, then the conversion is often invalid. Illustrated in Fig. 63 for a simple resistive divider, the theorem gives a correct input impedance but an incorrect Ry x Y x Y Ra Ry+Ry 4 “Re @ ) Figure 6.3 Improper application of Miller's theorem. gain, Nevertheless, Miller's theorem proves useful in cases where the impedance Z appears in parallel with the main signal (Fig. 6.4). Figure 6.4 Typical case for valid ap- plication of Miller’s theorem. Main Signal Path Example 6.2 Calculate the input resistance of the circuit shown in Fig. 6.5(a). Yop Yop dy Ny to Y 1-1/Av My My Yeh =r Yes Figure 6.5Sec.6,1 General Considerations 169 Solution ‘The reader can prove that the voltage gain from X to ¥ is equal to 1 + (gm + gmb)ro. As shown in Fig. 6.5(b), the input resistance is given by the parallel combination of ro /(I ~ Ay) and 1/(gm-+ 8mb)- Since Ay is usually greater than unity, ro /(1 — Ay) is a negative resistance. We therefore have ro 1 Rin = —————__ (6.4) "= T+ Gn smovrol | Smt Bm eo =1 = i (65) &m + &mb | 8m + Bb oo. 66) This is the same result as obtain¢ Chapter 3 (Fig. 3.46) by direct calculation. We should also mention that, strictly speaking, the value of Ay = Vy/Vy in (6.2) and (6.3) must be calculated at the frequency of interest, complicating the algebra significantly. However, in many cases we use the low-frequency value of A, to gain insight into the behavior of the circuit, If applied to obtain the input-output transfer function, Miller's theorem cannot be used simultaneously to calculate the output impedance. To derive the transfer function, we apply a voltage source to the input of the circuit, obtaining a value for Vy / Vx in Fig. 6.1(a). On the other hand, to determine the output impedance, we apply a voltage source to the output of the circuit, obtaining a value for Vx / Vy that may not be equal to the inverse of the Vy / Vx measured in the first test. For example, the circuit of Fig. 6.5(b) may suggest that the output impedance is equal to ro Row as ) ro = 6.8) 1+ (8m + 8mo)rol? wo) Soa 69) Bm t+ &mb whereas the actual value is equal to ro (if X is grounded). Other subtleties of Miller's theorem are decribed in the appendix. 6.1.2 Association of Poles with Nodes Consider the simple cascade of amplifiers depicted in Fig. 6.6. Here, A, and Az are ideal voltage amplifiers, R; and Rz model the output resistance of each stage, Ci, and Cy repre- sent the input capacitance of each stage, and Cp denotes the load capacitance. The overall transfer function can be written as Vout ( At Az 1 7 +RiCys 1+R:Cps” =—) 6.1 Vin 1+ RsCins 6.10)170 Chap.6 Frequency Response of Ampities The circuit exhibits three poles, each of which is determined by the total capacitance seen from each node to ground multiplied by the total resistance seen at the node to ground, We can therefore associate each pole with one node of the circuit, i.e., ©; = ry!, where 7; is the product of the capacitance and resistance seen at node j to ground. From this perspective, we may say “each node in the circuit contributes one pole to the transfer function.” Figure 6.6 Cascade of amplifiers. The above statement is not valid in general. For example, in the circuit of Fig. 6.7, the location of the poles is difficult to calculate because Rs and Cs create interaction between Figure 6.7 Example of interaction be- tween nodes. X and Y. Nevertheless, in many circuits association of one pole with each node provides an intuitive approach to estimating the transfer function: we simply multiply the total equivalent capacitance by the total incremental resistance (both from the node of interest to ground), thus obtaining an equivalent time constant and hence a pole frequency. Example 6.3 In Fig. 6.8, calculate the pole associated with node X. ure 6.8Sec.6.1 General Considerations 71 Solution From Fig. 6.2(b), the total equivalent capacitance seen from X to ground equals (1 + A)Cp. Since this capacitance is driven by Rs, the pole frequency is equal to 1/[Rs(I + A)Cr] (in rad/s). We call this the “input pole.” Ne The above approach does suffer from some limitations. In particular, the simplification of the circuit through the use of Miller effect often discards the zeros of the transfer func- tion. However, the utility of the method becomes apparent in more complex topologies, as described in the following example. Example 6.4 Neglecting channel-length modulation, compute the transfer function of the common-gate stage shown in Fig. 6.9. Figure 6.9 Common-gate stage with parasitic capacitances. Solution In this circuit, the capacitances contributed by M; are connected from the input and output nodes to ground. At node X, Cs = Csi + Csa1, giving a pole frequency “1 1 Bm + Bt )| . a Similarly, at node ¥, Cp = Cog + Cop. yielding a pole frequency en = [ico +Cspi) (és @out = (Cog + Cpa)Rol"! (6.12) The overall transfer function is thus given by Vout 5) - Gm + 8m) RD 1 a __ 1, (6.13) Vin = TH (Bin + Bmb)RS (+2)0-4) a on out where the first fraction represents the low-frequency gain of the circuit. Note that if we do not neglect ror, the input and output nodes interact, making it difficult to calculate the poles, _172 Chap.6 Frequency Response of Ampitiers 6.2 Common-Source Stage The common-source topology exhibits a relatively high input impedance while providing voltage gain and requiring a minimal voltage headroom. As such, it finds wide application in analog circuits and its frequency response is of interest. ‘Shown in Fig. 6.10 is a common-source stage driven by a finite source resistance, Rs We identify all of the capacitances in the circuit, noting that Ces and Cpp are “grounded” capacitances while Cgp appears between the input and the output. Assuming that 4 = 0 and M, operates in saturation, let us first estimate the transfer function by associating one pole with each node. The total capacitance seen from X to ground is equal to Ces plus the Miller multiplication of Cg: Ces + (1 — Ay)Cop, where Ay = —8m Rp. The magnitude of the input pole is therefore given by On = (6.14) 1 RslCos + (1+ &mRv)Coo)" At the output node, the total capacitance seen to ground is equal to Cpg plus the Miller effect of Cen: Coz + (1 — A5")Cen © Con + Cop. Thus, (6.15) Ou = —————. * Ro(Coa + Coo) Another approximation of the output pole can be obtained if Rs is relatively large. Simplifying the circuit as shown in Fig. 6.11, where the effect of Rs is neglected, the reader can prove that 1 Con+Cos 1 ) Zy= 2S), 6.16) ances ( Cap 8m where Cey = CepCes/(Cep + Cos). Thus, the output pole is roughly equal to 1 our = : (6.17) Con+Ces 1 [0 (Settee +) (Coq + Coa) Cap Smt Figure6.10 High-frequency model of ‘a common-source stage.Sec.6.2 Common-Source Stage 173 Yoo R Can a My Zx ilies Toes = = Figure 6.11. Model for calculation of - output impedance. Cos Yx ImVx. [= Ay " abi Figure 6.12 Equivalent circuit of Fig. 6.10. We then surmise that the transfer function is Cae) Note that ro, and any load capacitance can easily be included here. The primary error in this estimation is that we have not considered the existence of zeros in the circuit. Another concern stems from approximating the gain of the amplifier by —gnRp whereas in reality the gain varies with frequency (for example, due to the capacitance at the output node). ‘We now obtain the exact transfer function, investigating the validity of the above ap- proach. Using the equivalent circuit depicted in Fig. 6.12, we can sum the currents at each node: Vout Vin = (6.18) Vin Rpt Vx Cass + (Vx — Vour)Cans s (6.19) 1 (Wout ~ Vx)Cans + 8mVx + Vour (je + Cons) =0. (6.20) D174 Chap.6 Frequency Response of Amplifiers From (6.20), Vx is obtained as 1 Vout (coos ae cesaeee Cons) Ro Vy == (621) * 8m — Cops which, upon substitution in (6.19), yields =! —1 _y,,[RE' + Cos + CondsIRp! + (Cop +E} _ yong = Yin, 6) ‘Bn — Cops Rs Thatis, Vout (6) — (Cops ~ &m)Ro Vin RsRpgs? + [Rs(1 + 8mRv)Cen + RsCoas + Ro(Cep + Coa)ls + 1" (6.23) where § = CosCop + CosCpa + CanCps. Note that the transfer function is of second order even though the circuit contains three capacitors. This is because the capacitors form “loop,” allowing only two independent initial conditions in the circuit and hence yielding a second-order differential equation for the time response. If manipulated judiciously, Eq. (6.23) reveals several interesting points about the circuit. While the denominator appears rather complicated, it can yield intuitive expressions for the two poles, «p) and wpa, if we assume |ap1| « |p| [1]. Writing the denominator as, o=(£+1)(S+)) (6.24) On On s 2 11 = +(—+—]st+1 (6.25) @p1p2 Mp1 pa we recognize that the coefficient of s is approximately equal to 1 /ap1 if wp is much farther from the origin. It follows from (6.23) that 1 pt = RATE RE RE En PL Rs + Bm Ro)Cap + RsCas + Ro(Cav + Coa) (6.26) How does this compare with the “input” pole given by (6.14)? The only difference results from the term Rp(Cep + Coa), which may be negligible in some cases. The key point here is that the intuitive approach of associating a pole with the input node provides a rough estimate with much less effort. We also note that the Miller multiplication of Cgp by the low-frequency gain of the amplifier is relatively accurate in this case. Example 6.5 For the circuit shown in Fig. 6.13, calculate the transfer function (with = 0) and explain why Miller effect vanishes'as C pg increases.Sec. 6.2 Common-Source Stage 175 Figure 6.13 Solution Using (6.23) and letting Rp approach infinity, we have Vout Coos ~ sn ee — (6.27) Vin © = RSE Tem RsCop + Cov > Cah bay Coos ~ 8m gers (6.28) ~ SIRs(CasCoo + CasCos + CapCoa)s + (gmRs + Cap + Cos) As expected, the circuit exhibits two poles—one at the origin because the dc gain is infinity. The ‘magnitude of the other pole is given by (1+ amRs)Cov + Cog & (6.29) * RsiCav€as + CasCos + CanCos) om) For large Cpa. this expression reduces to 1 i (6.30) © Rs(Cas + Cap)" indicating that Cgp experiences no Miller multiplication. This can be explained by noting that, for large Cra, the voltage gain from node X to the output begins to drop even at low frequencies. As a result, for frequencies close to [Rs(Cgs + Cap)}"!, the effective gain is quite small and Cap(1 — Av) * Cep. Such a case is an example where the application of Miller effect using low-frequency gain does not provide a reasonable estimate. a From (6.23), we can also estimate the second pole of the CS stage of Fig. 6.10. Since the coefficient of s? is equal to (wpi@p2)~', we have 1 = —————————————— r=: (6.31 @p1 RsRo(CasCop + CosCos + CanCpa) Y = Rs + 8m Ro)Cap + RsCos + Ro(Cap + Coa) (632) RsRp(CesCan + CasCpz + CapCps)176 Chap.6 Frequency Response’ of Ampiiers If Cos > (1 + &mRv)Con + Ro(Can + Cpos)/Rs, then RsCas on & —————PsCas_ ” * RsRp(CasCap + CosCos) (6.33) 1 Ro(Con + Coe)" ee the same as (6.15). Thus, the “output” pole approach is valid only if Cs dominates the ar The transfer function of (6.23) exhibits a zero given by «, = +m/Cep, an effect not predicted by the simple approach leading to (6.18). Located in the right half plane, the zero arises from direct coupling of the input to the output through Cop. As illustrated in Fig. 6.14, Con provides a feedforward path that conducts the input signal to the output at very high frequencies, resulting in a slope in the frequency response that is less negative than —40 dB/dec. As explained in Chapter 10, a zero in the right half plane introduces stability issues in feedback amplifiers. Feedforward Path ‘ed Figure 6.15 Calculation of the zeroin ACS stage. The zero, s., can also be computed by noting that the transfer function Veus(s)/ Vin(S) must drop to zero for s = s;. For a finite Vin, this means that Vou(s.) = 0 and hence the output can be shorted to ground at this (possibly complex) frequency with no current flowing through the short (Fig. 6.15). Therefore, the currents through Cgp and My are equalSoc. 6.2 thr T ote Coe Toss I + I ‘Common-Source Stage 17 and opposite: ViCaps: = &mVi- (6.35) That is, s; = +8m/Cov.! In high-speed applications, the input impedance of the common-source stage is also important. As a first-order approximation, we have from Fig. 6.16(a) 1 Zin = —— [Cos + (1 + &mRo)Conls (6.36) But at high frequencies, the effect of the output node must be taken into account. Ignoring Ces for the moment and using the circuit of Fig. 6.16(b), we write Rp Ix 1+RpCpss © Cops Cx ~ &m Vx): = Vx, (6.37) and hence Vx 1+ Ro(Can + Con)s =o Oor—ere——eoro 6.38 Tx Ceps(1 + 8mRp + RoCss) ey ‘The actual input impedance consists of the parallel combination of (6.38) and 1/(Cgss). (@) © Figure 6.16 Calculation of input impedance of a CS stage. At frequencies where |Rp(Cop + Cpa)s| K 1 and |RpCoas| K 1+ gmRp, (6.38) reduces to [(1 + gm Rp)Cops]! (as expected), indicating that the input impedance is pri- marily capacitive. At higher frequencies, however, (6.38) contains both real and imaginary parts. In fact, if Cgp is large, it provides a low-impedance path between the gate and drain of Mj, yielding the equivalent circuit of Fig. 6.16(c) and suggesting that 1/gm1 and Rp appear in parallel with the input. ‘This approach is similar to expressing the transfer function a8 Gy Zou, and finding the 2er0s of Gyy and Zu178 Chap.6 Frequency Response of Amplifiers 6.3 Source Followers Source followers are occasionally employed as level shifters or buffers, impacting the over all frequency response. Consider the circuit depicted in Fig. 6.17(a), where C, represents the total capacitance seen at the output node to ground, including Csg1. The strong inter- Yoo Rs Rs 2 (oo My Vin & eal mal Vy OD anv Vin Y' Vout = T oS a To ° @) ) Figure 6.17 (a) Source follower, (b) high-frequency equivalent circuit. action between nodes X and ¥ through Cos in Fig. 6.17(a) makes it difficult to associate a pole with each node in a source follower. Neglecting body effect for simplicity and us- ing the equivalent circuit shown in Fig. 6.17(b), we can sum the currents at the output node: ViCoss + &mVi = Vou Cis, (6.39) obtaining Cus Vi = Vow (6.40 1 gat Coss 7 Also, beginning from Vj,, we can add up all of the voltages: Vin = Rs[ViCa@ss + (Vi + Vour)Cops] + Vi + Vou (641) Substituting for V; from (6.40), we have Vout () = Bm + Coss : Vin Rs(CosCu + CosCan + CapC)s* + (8mRsCap + Cr + Cas)s + &m (6.42) Interestingly, the transfer function contains a zero in the left half plane. This is because the signal conducted by Cos at high frequencies adds with the same polarity to the signal produced by the intrinsic transistor.$ec.6.3 Source Followers 179 If the two poles of (6.42) are assumed far apart, then the more significant one has a magnitude of 8m ~~ —__$n_ 6.43} Ort am RsCap + Cx + Cas 2) 1 = or (6.44) Ci + Cos" RsCon + Also, if Rs =0, then @p1 = Bn/(Cr + Cos). Letus now calculate the input impedance of the circuit, noting that Cp simply shunts the input and can be ignored initially. From the equivalent shown in Fig. 6.18, the small-signal Yoo Ix My Vy y Ces: Lt Vout . 1 = Cy Sm fT T* Figure6.18 Calculation of source fol- FF lower input impedance. gate-source voltage of M; is equal to [x /(Cass), giving a source current of gn lx /(Coss). Starting from the input and adding the voltages, we have Ix &mIx ) a i fet L —|— (6.45) : cat ( + Coss) Name [Crs )” (645) that is, a 8m 1 In = (it —— 6.46) Cass Cass} 8mo + Cis : Atrelatively low frequencies, gm» 9> |Cis| and _ (4%)+s, (647) Cass Bmb) — &mb indicating that the equivalent input capacitance is equal to Cosmo/(8m + &ms). This result can also be obtained by Miller approximation, Since the low-frequency gain from the input tothe output equals fm/(gn + Smo) the effect of Ces at the input can be expressed as Cost ~&n/(@n+8nb)] = Cos8no(8m-+ Smo). In other words, the overall input capacitance is equal to Cop plus a fraction of Cos. Athigh frequencies, gas < [Crs] and Zn | Coss * Cis * CosCus? (6.48)180 Chap.6 Frequency Response of Amplifiers For a given s = jw, the input impedance consists of the series combination of capacitors Cos and C, and a negative resistance equal t0 ~&m/(CosCiw”). The negative resistance property can be utilized in oscillators [2]. Example 6.6 Calculate the transfer function of the circuit shown in Fig. 6.19(a). Yoo Rs x My + ) My, @ ) Figure 6.19 Solution Let us first identify all of the capacitances in the circuit. At node X, Cgp1 and Cpg2 are connected to ground and Cgsi and Cgp2 to ¥. At node ¥, Csi, Cos2, and Cy, are connected to ground, Similar to the source follower of Fig. 6.17(b), this circuit has three capacitances in a loop and hence a second- order transfer function. Using the equivalent circuit shown in Fig. 6.19(b), where Cx = Cop1+Cps2, Cxy = Cosi + Cap2, and Cy = Csa1 + Cos2 + Cr, we have ViCxys + &miVi = VourCys and hence Vi = VourCys/(Cxvs + 8m). Also, since V2 = Vout, the summation of currents at node X gives Vin = Vi = Vous (V1 + VourYOxS + 8m2 Vous + ViCxys = eet (6.49) ‘Substituting for V; and simplifying the result, we obtain Vout (5) = Bm + Cxrs Vin Rsks* + 1Cy + Bm RsCx + (1+ Bm2Rs)Cxvls + Bill + 8m2R5)" (6.50) where & = CxCy + CxCxy + CyCxy. As expected, (6.50) reduces to a form similar to (6.42) for m2 = 0. ‘The output impedance of source followers is also of interest. In Fig. 6.17(a), the body ef- fect and Cse simply yield an impedance in parallel with the output. Ignoring this impedance and neglecting Cep, we note from the equivalent circuit of Fig. 6.20(a) that ViCoss +Sec. 6.3 Source Followers 181 8nVi = —Ix. Also, ViCgssRs + Vi = —Vx. Dividing both sides of these equations gives Lou = (6.51) Ix = RsCoss +1 (6.52) 8m + Cass Itis instructive to examine the magnitude of this impedance as a function of frequency. At low frequencies, Zour * 1/8m, as expected, At very high frequencies, Zou * Rs (because Ces shorts the gate and the source). We therefore surmise that |Zou:| aries as shown in Figs. 6.20(b) ot (c). Which one of these variations is more realistic? Operating as buffers, source followers must lower the output impedance, i.¢., 1/gm < Rs. For this reason, the characteristic shown in Fig. 6.20(c) occurs more commonly than that in Fig. 6.20(b). The behavior illustrated in Fig. 6.20(c) reveals an important attribute of source followers. Since the output impedance increases with frequency, we postulate that it contains an inductive component. To confirm this guess, we represent Zou, by a first-order passive network, noting that Zou; equals 1/gm at @ = 0 and Rs at @ = oo. The network can therefore be assumed as shown in Fig, 6.21 because Z; equals Rp at o = 0 and Ry + Ro at @ = oo. In other words, Z) = Zou; if Ro = 1/8m, Ri = Rs — 1/gm, and L is chosen properly. To calculate L, we can simply obtain an expression for Z; in terms of the three com- ponents in Fig. 6.21 and equate the result to Zou; found above. Alternatively, since Ro is a series component of Z;, we can subtract its value from Z,,, thereby obtaining an expression (b) © Figure 6.20 Calculation of source follower output impedance182 Chap.6 Frequency Response of Amplifiers Figure 6.21 Equivalent output impe- dance of a source follower. for the parallel combination of Ry and L: : _ (&% - ) Zou — 2 = End 633) mu Bm Bn tCoss " Inverting the result to obtain the admittance of the parallel circuit, we have 1 1 1 to (654) Zua-L Rs a) 8m 8m 8m 8m ‘We can thus identify the first term on the right hand side as the inverse of R; and the second term as the inverse of an impedance equal to (Cos5/%m)(Rs — 1/m)se., an inductor with the value L S22 (re- 4). (6.55) 8m Bm The dependence of L upon Rs implies that if a source follower is driven by a large resistance, then it exhibits substantial inductive behavior. As depicted in Fig, 6.22, this effect manifests itself as “ringing” in the step response if the circuit drives a large load capacitance. Figure 6.22 Ringing in step response of a source follower with heavy capacitive load.Sec.6.4 Common-Gate Stage 183 6.4 Common-Gate Stage As explained in Example 6.4, in a common-gate stage the input and output nodes are “isolated” if channel-length modulation is neglected. For a common-gate stage such as that in Fig. 6.23, the calculation of Example 6.4 suggested a transfer function Figure 6.23 Common-gate stage at high frequencies. Vout (,) (8m + 8s) Ro 1 Vin 1+ @m + &mo)Rs ( Cs (6.56) 1+ —) (1+ RpCps) Sm + Bmb + RS! ‘An important property of this circuit is that it exhibits no Miller multiplication of capac- itances, potentially achieving a wide band. Note, however, that the low input impedance may load the preceding stage. Furthermore, since the voltage drop across Rp is typically maximized to obtain a reasonable gain, the dc level of the input signal must be quite low. If channel-length modulation is not negligible, the calculations become quite complex. Recall from Chapter 3 that the input impedance of a common-gate topology does depend on the drain load if 2 0. From Eq, (3.110), we can express the impedance seen looking into the source of M; in Fig. 6.23 as Z 1 5 _ + 6.57) (Bm + Bmb\rO Sm + Bmb 7 Zin where Z, = Rpll{1/(Cps)]. Since Zj, now depends on Z,, itis difficult to associate a pole with the input node. Example 6.7 For the common-gate stage shown in Fig. 6.24(a), calculate the transfer function and the input impedance, Zjn. Explain why Zi, becomes independent of Cy, as this capacitance increases. Solution Using the equivalent circuit shown in Fig. 6.24(b), we can write the current through Rg a8 —ViyeC1s-+ ViCins. Noting that the voltage across Rg plus Vj, must equal —V;, we have (-VourCs + ViCins)Rs + Vin = —Vi- (6.58)Chap.6 Frequency Response of Amplifiers Figure 6.24 that is, (6.59) We also observe that the voltage across ro minus V; equals Vout! ro(—VourCis = &mVi) — Vi = Vour- (6.60) Substituting for V; from (6.59), we obtain the transfer function: Vout 1+8mro Ser aoe gee es (6.61) Vin) roCLCin Rss? + [ro + CinRs + (1 + &mrovCLRsls + 1 Cy ‘The reader can prove that body effect can be included by simply replacing gm with gm + gmp. AS expected, the gain at very low frequencies is equal to 1 + Smo. For Zin, we can use (6.57) by replacing Z,, with 1/(C,.s), obtaining 1 1 1 Zin = ——— + — - Bm+ 8mb CLS (8m + 8mb\rO (6.62) We note that as Ci, or s increases, Zin approaches 1/(gm + 8b) and hence the input pole can be defined as 1 pin = 7] — (i c 1 m+ mb)” Why does Zin become independent of Cy at high frequencies? This is because Cy, lowers the voltage gain of the circuit, thereby suppressing the effect of the negative resistance introduced by Miller effect through ro (Fig. 6.5). In the limit, Cz, shorts the output node to ground, and ro affects the input impedance negligibly. (6.63)$ec.6.5 Cascode Stage 185 Ifa common-gate stage is driven by a relatively large source impedance, then the output impedance of the circuit drops at high frequencies. This effect is better described in the context of cascode circuits. 6.5 Cascode Stage As explained in Chapter 3, cascoding proves beneficial in increasing the voltage gain of amplifiers and the output impedance of current sources while providing shielding as well. The invention of the cascode (in the vacuum tube era), however, was motivated by the need for high-frequency amplifiers with relatively high input impedance. Viewed as a cas- cade of a common-source stage and a common-gate stage, a cascode circuit offers the speed of the latter—by suppressing the Miller effect—and the input impedance of the former. Let us consider the cascode shown in Fig. 6.25, first identifying all of the device ca- pacitances. At node A, Cosi is connected to ground and Ccpi to node X. At node X, Cosi, Csa2, and Cosp are tied to ground, and at node Y, Cpg2, Cepz, and Cy, are con- nected to ground. The Miller effect of Cp: is determined by the gain from A to X. As an approximation, we use the low-frequency value of this gain, which for low values of Rp (or negligible channel-length modulation) is equal to —gmi/(8n2 + &moa)- Thus, if My and M; have roughly equal dimensions, Cg is multiplied by approximately 2 rather than the large voltage gain in a simple common-source stage. We therefore say Miller effect is less significant in cascode amplifiers than in common-source stages. The pole associated with node A is estimated as Opa = — eS? or (6.64) Rs [eos + (: + ats) Coo1| m2 + 8mb2 Cosi + Cse2 Figure6.25 High-frequency model of cascode stage.186 Chap.6 Frequency Response of Amplifiers We can also attribute a pole to node X. The total capacitance at this node is roughly equal to 2Cepi + Cosi + Coz + Case, giving a pole 8&m2 + Bmb2 x =F (6.65) ?** 2Capi + Cosi + Csa2 + Cos2 Finally, the output node yields a third pole: L py = (6.66) Ro(Com2 + Ci + Cep2)" The relative magnitudes of the three poles in a cascode circuit depend on the actual design parameters, but «vp, x is typically chosen to be farther from the origin than the other two. As explained in Chapter 10, this choice plays an important role in the stability of op amps. But what if Rp in Fig. 6.25 is replaced by a current source so as to achieve a higher de gain? We know from Chapter 3 that the impedance seen at node X reaches high values if the load impedance at the drain of M is large. For example, Eq. (3.110) predicts that the pole at node X may be quite lower than (gm2 + 8mi2)/Cx if Rp itself is the output impedance of a PMOS cascode current source. Interestingly, however, the overall transfer function is negligibly affected by this phenomenon. This can be better seen by an example. Example 6.8 Consider the cascode stage shown in Fig. 6.26(a), where the load resistor is replaced by an ideal @ (b) Figure 6.26 Simplified model of a cascode stage. current source. Neglecting the capacitances associated with My, representing Vin and M, by a Norton equivalent as in Fig. 6.26(b), and assuming y = 0, compute the transfer function. Solution Since the current through Cy is equal to —Vour Cys ~ Tin, we have Vy = —(Vou Cvs + Tin)/(Cxs), and the small-signal drain current of M2 is —@m2(—VourCys — Hin)/(Cxs). The current through ro2Sec.6.6 Differential Pair 187 is then equal t0 —VouCy — 8ma(Vour C$ + lin)/(Cxs). Noting that Vx plus the voltage drop across ro2 is equal to Vour, we write ~ro2 | WouCrs + lin) $22 + VuCvs| — Vou Crs + lin} = Vou. (6.67) Cxs Cxs That is, ous __SaaFOn +1 fy 2 1+(1 + gmaro2dq- + Crroos Cx which, for gm2r02 > 1 and gm2ro2Cy /Cx » | (i.e, Cy > Cx), reduces to Vout mn ret we $n (669) i" XS gna + Cys Cx and hence Vou __Simi8m2__1 6m) Vin CyCxs 8m2/Cx +5 ‘The magnitude of the pole at node X is still given by gm2/Cyx. This is because at high frequencies (as we approach this pole) Cy shunts the output node, dropping the gain and suppressing the Miller effect of ro2. Ifacascode structure is used as a current source, then the variation of its output impedance with frequency is of interest. Neglecting Cgp1 and Cy in Fig. 6.26(a), we have Zour = (1 + Bmaro2)Zx +72, (71) where Zx = roi|(Cxs)~. Thus, Zou; contains a pole at (r91Cx)~? and falls at frequencies higher than this value. 6.6 Differential Pair The versatility of differential pairs and their extensive use in analog systems motivate us to characterize their frequency response for both differential and common-mode signals. Consider the simple differential pair shown in Fig. 6.27(a), with the differential half cir- cuit and the common-mode equivalent circuit depicted in Figs. 6.27(b) and (c), respectively. For differential signals, the response is identical to that of a common-source stage, exhibit- ing Miller multiplication of Cgp. Note that since + Vin2/2 and —Vin2/2 are multiplied by the same transfer function, the number of poles in Vour/Vin is equal to that of each path (rather than the sum of the number of the poles in the two paths). For common-mode signals, the total capacitance at node P in Fig. 6.27(c) determines the high-frequency gain. Arising from Cgp3, Coss, Csa1, and Csgp, this capacitance can be188 Chap.6 — Frequency Response of Amplifiers Yop Ro Ap Yao 2 Vina Yoo ms (a) Yoo Cop F 7 Vourt Vint My ie T= &) Figure 6.27 (a) Differential pair, (b) half-circuit equivalent, (c) equivalent circuit for common-mode inputs. quite substantial if M,-M; are wide transistors. For example, limited voltage headroom often necessitates that Ws be so large that M3 does not require a large drain-source voltage for operating in the saturation region. If only the mismatch between M, and Mo is considered, the high-frequency common-mode gain can be calculated with the aid of Eq. (4.43). We replace ro3 with rosli{1/(Cps)] and Rp by Roll{1/(Czs)], where Cy denotes the total capacitance seen at each output node. Thus, As R i ae [ 7 (a )I Avon =~ (8m + 8m2) [ros (&)I +1 (6.72) where other capacitances in the circuit are neglected.Sec.6.6 Differential Pair 189 This result suggests that, if the output pole is much farther from the origin than is the pole at node P, the common-mode rejection of the circuit degrades considerably at high frequencies. For example, as illustrated in Fig. 6.28, if the supply voltage contains high-frequency noise and the circuit exhibits mismatches, the resulting common-mode disturbance at node P leads to a differential noise component at the output. Tos T Cp Figure 6.28 Effect of high-frequency supply noise in differential pairs. We should emphasize that the circuit of Fig. 6.27(a) suffers from a trade-off between voltage headroom and CM RR. To minimize the headroom consumed by Ms, its width is maximized, introducing substantial capacitance at the sources of M, and M> and degrading the high-frequency CM RR. The issue becomes more serious at low supply voltages. ‘We now study the frequency response of differential pairs with high-impedance loads. Shown in Fig. 6.29(a) is a fully differential implementation. As with the topology of Fig. 6.27, this circuit can be analyzed for differential and common-mode signals sepa- rately. Note that here C,, includes the drain junction capacitance and the gate-drain overlap capacitance of each PMOS transistor as well. Also, as depicted in Fig. 6.29(b) for differen- tial output signals, C¢p3 and Cys conduct equal and opposite currents to node G, making this node an ac ground. (In practice, node G is nonetheless bypassed to ground by means of a capacitor.) The differential half circuit is depicted in Fig. 6.29(c), with the output resistance of My and Ms shown explicitly. This topology implies that Eq. (6.23) can be applied to this circuit if R,, is replaced by ro lIro3- In practice, the relatively high value of this resistance makes the output pole, given by {(ro1lIro3)Cz I~, the “dominant” pole. We return to this observation in Chapter 10. The common-mode behavior of the circuit is similar to that of Fig. 6.27(c). Let us now consider a differential pair with active current mirror (Fig. 6.30). How many poles does this circuit have? In contrast to the fully differential configuration of Fig. 6.29(a), this topology contains two signal paths with different transfer functions. The path consisting of M3 and My includes a pole at node E, approximately given by gma/C, where Cr denotes the total capacitance at E to ground. This capacitance arises from Cosa, Cass. Coa3, Costs and the Miller effect of Cgp1 and Copa. Even if only Cgs3 and Coss are considered, the severe trade-off between g,, and Ces of PMOS devices results in a pole that greatly impacts190 Chap.6 Frequency Response of Amplifiers Vv, Mi, oo Cops 1 Cont Vins Figure 6.29 (a) Differential pair with current-source loads, (b) effect of differential swings at node G, (c) half-circuit equivalent Yoo Ms Ms output E Pole Mirror 7 Van Pole * o Vin Figure 6.30 High-frequency behavior of differential pair with active current mirror. the performance of the circuit. The pole associated with node E is called a “mirror pole.” Note that, as with the circuit of Fig. 6.29(a), both signal paths shown in Fig. 6.30 contain a pole at the output node. In order to estimate the frequency response of the differential pair with active current mirror, we construct the simplified model depicted in Fig. 6.31(a), where all other capac- itances are neglected. Replacing Vin, Mi, and Mz by a Thevenin equivalent, we arrive at the circuit of Fig. 6.31(b), where, from the analysis of Fig. 5.26, Vy = gmronVin and Rx = 2ron. Here, the subscripts P and N refer to PMOS and NMOS devices, respectively,Sec.6.6 Differential Pair 191 ) Figure 6.31 (a) Simplified high-frequency model of differential pair with active current mirror, (©) circuit of (a) with a Thevenin equivalent. and we have assumed 1/2,» & rop. The small-signal voltage at E is equal to 1 Ve = Vou ~ Vx) CES * SP 673) — tr Ces+anp and the small-signal drain current of Mg is n4Ve. Noting that —@m4Ve — Ix = Vour(Cus + Top) We have Vous Vin _ Bmnton(28mp + Ces) 2ropronCeCs* + [row +rop)Ce + rop(l + 28mPronyCLIs + 28mP Fon + For) (6.74) Since the mirror pole is typically quite higher in magnitude than the output pole, we can utilize the results of Eq. (6.25) to write 28mp(ron trop) Dp (6.75) °1 Grow + Tor ICE + ror + 2enpron CL Neglecting the first term in the denominator and assuming 2gmprow >> 1, we have 1 Op © (6.76) (rowllrop)Cu"192 Chap.6 — Frequency Response of Ampiifiers an expected result. The second pole is then given by one B. (6.71) which is also expected. An interesting point revealed by Eq. (6.74) is a zero with a magnitude of 2gmp/Ce inthe left half plane. The appearance of such a zero can be understood by noting that the circuit, consists of a “slow path” (M,, Ms, and M,) in parallel with a “fast path” (Mj and M;). Representing the two by Ao/[(1 + 5/@pi)(1 + $/app)] and Ao/(1 + s/wp1), respectively, we have oe) (6.38) Vin 18/1 \1+s/op2 ___ Aol +8/0p2) co C¥ s/o) + 80,2) That is, the system exibits a zero at 252. The zero can also be obtained by the method of Fig. 6.15 (Problem 6.15). ‘Comparing the circuits of Figs. 6.29(a) and 6.30, we conclude that the former entails no mirror pole, another advantage of fully differential circuits over single-ended topologies. Example 6.9 Not al fully differential circuits are free from mirror poles. Fig. 6.32(a) illustrates an example, where ‘current mirrors M3-Ms and M,-Mg “fold” the signal current. Estimate the low-frequency gain and the transfer function of this circuit. Solution Neglecting channel-length modulation and using the differential half-circuit shown in Fig. 6.32(b), we observe that Ms multiplies the drain current of Ms by K, yielding an overall low-frequency voltage gain Ay = gmiK Rp. ‘To obtain the transfer function, we utilize the equivalent circuit depicted in Fig. 6.32(c), includinga source resistance Rs for completeness. To simplify calculations, we assume RpCz is relatively small so that the Miller multiplication of Cgps can be approximated as Cgps(+ &msRp). The circuit thus reduces to that in Fig. 6.32(d), where Cx © Coss + Coss + Coss + Caps(1 + 8msRp) + Cosi ‘The overall transfer function is then equal to Vx / Vin multiplied by Vous1/ Vx. The former is readily obtained from (6.23) by replacing Rp with 1/gm3 and Cpg with Cx, while the latter is Voutt 1 ths) = -gns Ro Wy = Ens ROT Res (6:80) Note that we have neglected the zero due to Ceps.Appendix A: Dual of Miller's Theorem 193 Figure 6,32 Appendix A: Dual of Miller’s Theorem In the Miller’s theorem (Fig. 6.1), we readily observe that Z; + Zp coincidence and it has interesting implications. Redrawing Fig. 6.1 as shown in Fig. 6.33(a), we surmise that since the point between Z; and Z2 can be grounded, then if we “walk” from X towards Y along the impedance Z, the local potential drops to zero at some intermediate point [Fig. 6.33(b)]. Indeed, for Vp = 0, we have Z. This is no Za Zat Zp (Vy ~ Vx) + Vx = 0, (6.81) and, since Z, + Zp (6.82) T= Vr/ Vx"194 Chap.6 Frequency Response of Ampitfers Figure 6.33 Illustration of Miller's theorem identifying a local zero potential along Z. Similarly, Zz Z=—- OS T= Vx/ Ve (6.83) In other words, Zi(= Ze) and Za(= Zp) are such decompositions of Z that provide an intermediate node having a zero potential. For example, since in the common-source stage of Fig. 6.10 Vy and Vy have opposite polarities, the potential falls to zero at some point “inside” Cop. The above observation explains the difficulty with the transformation depicted in Fig. 6.3. Drawing Fig, 6.33(b) for this case as in Fig. 6.34(a), we recognize that the circuit is Fy+R, -Ry Ay+R, -Rp x Y x Lf Pe Re @® © Figure 6.34 Resistive divider with decomposition of Ri. still valid before node P is grounded because the current through Ry + Re must equal that through — Rp. However, if, as shown in Fig. 6.34(b), node P is tied to ground, then the only current path between X and Y vanishes. The concept of a zero local potential along the floating impedance Z also allows us to develop the “dual” of Miller’s theorem, i.e., decomposition in terms of admittances and current ratios. Suppose two loops carrying currents /; and /2 share an admittance Y (Fig. 6.35(a)]. Then, if ¥ is properly decomposed into two parallel admittances ¥; and Y2, the current flowing between the two is zero [Fig. 6.35(b)] and the connection can be broken [Fig, 6.35(c)]. In Fig. 6.35(a), the voltage across ¥ is equal to (I) ~ /2)/¥ andin Fig. 6.35(c),Problems 195 120 = = = = hi fiy| 2 dm well] te 4 » | h = < (a) (b) (c) Figure 6.35 (a) Two loops sharing admittance Y, (b) decomposition of ¥ into ¥; and Y such that 1 = 0, (c) equivalent circuit, the voltage across ¥; is /1/¥1. For the two circuits to be equivalent, and (6.84) (6.85) (6.86) Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 and assume Vp = 3 V where necessary. Also, assume all transistors are in saturation. All device dimensions are effective values and in microns. 6.1. 6.2. 63. 6.4, 65. In the circuit of Fig. 6.2(c), suppose the amplifier has a finite output resistance Rous (a) Explain why the output jumps up by AV before it begins to go down. This indicates the existence of a zero in the transfer function, (b) Determine the transfer function and the step response without using Miller’s theorem, Repeat Problem 6.1 if the amplifier has an output resistance Rou and the circuit drives a load capacitance Cr. ‘The CS stage of Fig. 6.10 is designed with (W/L), = 50/0.5, Ry = 1k and Ry = 2kQ.1f Ipi = 1 mA, determine the poles and the zero of the circuit. Consider the CS stage of Fig. 6.13, where 1 is realized by a PMOS device operating in saturation. Assume (W/L): = 50/0.5, Ip: = 1 mA, and Rs = 1k. (@) Determine the aspect ratio of the PMOS transistor such that the maximum allowable output level is 2.6 V. What is the maximum peak-to-peak swing? (b) Determine the poles and the zero. A source follower employing an NFET with W/L = 50/0.5 and a bias current of 1 mA is driven by a source impedance of 10k. Calculate the equivalent inductance seen at the output.196 Chap.6 Frequency Response of Amplifiers 66. Neglecting other capacitances, calculate the input impedance of each circuit shown in Fig. 6.6. Yoo Yoo Yoo Nn rE K co Ca Ge aa ae coalteataall C Co re M, Mu —h : Hq Zin ' Zin ' To a=0 axo azo” fa) (b) © Figure 6.36 6.7. Estimate the poles of each circuit in Fig. 6.37. 68. Calculate the input impedance and the transfer function of each circuit in Fig. 6.38. 69. Calculate the gain of each circuit in Fig. 6.39 at very low and very high frequencies. Neglect ll other capacitances and assume A = 0 for circuits (a) and (b) and y = 0 for all of the circuits. 6.10, Calculate the gain of each circuit in Fig. 6.40 at very low and very high frequencies. Neglect all other capacitances and assume = y = 0. 6.11, Consider the cascode stage shown in Fig. 6.41. In our analysis of the frequency response of a cascode stage, we assumed that the gate-drain overlap capacitance of M, is multiplied by Bmi/(8m2 + 8mb2)- Recall from Chapter 3, however, that with a high resistance loading the drain of Mp, the resistance seen looking into the source of Mz,can be quite high, suggesting a much higher Miller multiplication factor for Cgp1. Explain why Cap1 is still multiplied by 1+ gmi/(m2 + 8mo2) if Cr is relatively large. 6.12. Neglecting other capacitances, calculate Zy in the circuits of Fig. 6.42, Sketch |Z,x| versus frequency. 6.13, ‘The common-gate stage of Fig. 6.23 is designed with (W/L), = 50/0.5,Ip1 = 1 mA, Rp = 2k, and Rs = 1k. Assuming 4 = 0, determine the poles and the low-frequency gain. How do these results compare with those obtained in Problem 6.9? 6.14. Suppose in the cascode stage of Fig. 6.25, a resistor Rg appears in series with the gate of Mz. Including only Cqs2, neglecting other capacitances, and assuming 4 = y = 0, determine the transfer function. 6.15. Apply the method of Fig. 6.15 to the circuit of Fig. 6.31(b) to determine the zero of the transfer function. 6.16, The circuit of Fig. 6.32(a) is designed with (W/L)1,2 = 50/0.5 and (W/L)3.4 = 10/05. If Iss = 100 wA, K = 2, Cy = 0, and Rp is implemented by an NFET having W/L = 0/0.5, estimate the poles and zeros of the circuit. Assume the amplifier is driven by an ideal voltage source.Problems 197 a#0 Figure 6.37 Figure 6.38198 Chap.6 Frequency Response of Amplifiers Yoo Veze[E Ms Figure 6.39 @ Figure 6.40Problems 199 Figure 6.41 Figure 6.42 Figure 6.43,200 Chap.6 Frequency Response of Ampitier 6.17. A differential pair driven by an ideal voltage source is required to have a total phase shift of 135° at the frequency where its gain drops to unity. (a) Explain why a topology in which the load is realized by diode-connected devices or cureat sources does not satisfy this condition. (b) Consider the circuit shown in Fig, 6.43. Neglecting other capacitances, determine the trans- fer function. Explain under what conditions the load exhibits an inductive behavior. Can this circuit provide a total phase shift of 135° at the frequency where its gain drops to unity! References 1. P.R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Thitd Ed., New ‘York: Wiley, 1993. 2. B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998,Chapter 7 Noise Noise limits the minimum signal level that a cireuit ean process with acceptable quality. ‘Today's analog designers constantly deal with the problem of noise because it trades. with power dissipation, speed, and linearity, Inthis chapter, we describe the phenomenon of noise and its effect on analog circuits, The objective is to provide sufficient understanding of the problem so that further developments of analog circuits in the following chapters take noise into account as readily as other circuit parameters such as gain, input and output impedance, etc, Seemingly a complex subject, noise is introduced at this early stage so as to accompany the reader for the remainder of the book and become more intuitive through various examples. Following a general description of noise characteristics in the frequency and time do- mains, we introduce thermal, shot, and flicker noise, Next, we consider methods of represent- ing noise in circuits. Finally, we deseribe the effect of noise in single-stage and differential amplifiers along with trade-offs with other performance parameters, Statistical Characteristics of Noise Noise is arandom process. For our purposes in this book, this statement means the value of noise cannot be predicted at any time even if the past values are known, Compare the output of a sinewave generator with that of a microphone picking up the sound of water flow in a river (Fig. 7.1). While the value of 17 (2) at ¢ = 11 can be predicted from the observed waveform, the value of x7(¢) at f = fp cannot. This is the principal difference between deterministic and random phenomena. If the instantaneous value of noise in the time damain cannot be predicted, how can we incorporate noise in circuit analysis? This is accomplished by observing the noise for a Jong time and using the measured results to construct a “statistical model” for the noise. ‘While the instantaneous amplitude of noise cannot be predicted. a statistical model provides knowledge about some other important properties of the noise that prove useful and adequate in circuit analysis. Which properties of noise can be predicted? In many cases, the average power of noise is predictable. For cxample, if a microphone picking up the sound of a river is brought 201202 Chap.7 Noise Signal Generator @ ) Figure 7.1 Output of a generator and the sound of a river. closer to the river, the resulting electrical signal displays, on the average, larger excursions and hence higher power (Fig. 7.2). The reader may wonder if a random process can be so random that even its average power is unpredictable. Such processes do exist, but we are fortunate that most sources of noise in circuits exhibit a constant average power. ‘The concept of average power proves essential in our analysis and must be defined carefully. Recall from basic circuit theory that the average power delivered by a periodic ye) Oh t a) Bie “iw. b) Figure 7.2 Illustration of the average power of a random signal‘Types of Noise 213 also varies to some extent with the drai y is still under active research. source voltage. The theoretical determination of Example 7.3 Find the maximum noise voltage that a single MOSFET can generate. Solution As shown in Fig. 7.18, the maximum output noise occurs if the transistor sees only its own output Figure7.18 impedance as the load, ie., if the extemal load is an ideal current source. The output noise voltage is then given by Wem V2 = Tr, 725) = 4kT (3) 3. (7.26) Equation (7.26) suggests that the noise current of a MOS transistor decreases if the transconduc- tance drops. For example, if the transistor operates as a constant current source, it is desirable to minimize its transconductance, Another important conclusion is that the noise measured at the output of the circuit does not depend on where the input terminal is because for output noise calculation, the input is set to zero.® For example, the circuit of Fig. 7.18 may be a common-source or a common-gate stage, exhibiting the same output noise. The ohmic sections of a MOSFET also contribute thermal noise. As conceptually illus- trated in the top view of Fig. 7.19(a), the gate, source, and drain materials exhibit finite resistivity, thereby introducing noise. For a relatively wide transistor, the source and drain resistance is typically negligible whereas the gate distributed resistance may become no- ticeable. In the noise model of Fig. 7.19(b), a lumped resistor Ry represents the distributed gate resistance. Viewing the overall transistor as the distributed structure shown in Fig. 7.19(c), Of course if the input voltage or current source has an output impedance that generates noise, this statement ‘must be interpreted carefully204 Chap.7 Noise of each type of noise. Also called the “power spectral density” (PSD), the spectrum shows how much power the signal carries at each frequency. More specifically, the PSD, S<(/). of a noise waveform x(t) is defined as the average power carried by x(¢) in a one-hertz bandwidth around f. That is, as illustrated in Fig. 7.4(a), we apply x(t) to a bandpass filter Band-Pass Filter x(t) Sitiiiiii , 4h (b) Figure 7.4 Calculation of noise spectrum, with center frequency f; and 1-Hz bandwidth, square the output, and calculate the average over a long time to obtain Sy( fi). Repeating the procedure with bandpass filters having different center frequencies, we arrive at the overall shape of Sx(f) [Fig. 7.4(b)]. Whilit is possible that the PSD of a random process is random itself, most of the noise sources of interest to us exhibit a predictable spectrum. As with the definition of P,, in (7.3), itis customary to eliminate Ry, from Sx(f). Thus, since each value on the plot in Fig. 7.4(b) is measured for a 1-Hz bandwidth, Sx(f) is expressed in V°/Hz rather than W/H2z. It is also common to take the square root of Sy(/), expressing the result in V//Hz. For example, we say the input noise voltage of an amplifier at 100 MHz is equal to 3 nV/VHz, simply to mean that the average power in a 1-Hz bandwidth at 100 MHz is equal to (3 x 10-)? V2. An example of a common type of noise PSD is the “white spectrum,” also called white noise. Shown in Fig. 7.5, such a PSD displays the same value at all frequencies (similar “tn signal processing theory, the PSD is defined as the Fourier transform of the autocorrelation function of be noise. The two definitions are equivalent in most cases of interest to usStatistical Characteristics of Noise 205 s,(f) Figure 7.5 White spectrum. to white light). Strictly speaking, we note that white noise does not exist because the total area under the power spectral density, ie., the total power carried by the noise, is infinite. In practice, however, any noise spectrum that is flat in the band of interest is usually called white. The PSD is a powerful tool in analyzing the effect of noise in circuits, especially in conjunction with the following theorem. Theorem Ifasignal with spectrum Sy (fis applied to a linear time-invariant system with transfer function H(s), then the output spectrum is given by Sy) = Sx PIHCAP, (7.4) H(s = 2njf). The proof can be found in textbooks on signal processing or communications, e.g., [1]. This theorem agrees with our intuition that the spectrum of the signal should be “shaped” by the transfer function of the system (Fig. 7.6). For example, as illustrated in Fig. 7.7, S,(f) | byes eee Figure 7.6 Noise shaping by a transfer function xin (t) Telephone Xout(t) | {Dt | Suin(f) : Srout(f) | La 4kHz f 20kHz f 4kHz f Figure 7.7 Spectral shaping by telephone bandwidth.Statistical Characteristics of Noise 207 the amplitude, indicating how often each value occurs. Also called the “probability density function” (PDF), the distribution of x(t) is defined as px(x)dx = probability of x < X vay 1 Vout Figure 7.13 Noise generated in a low-pass filter. Solution ‘Modeling the noise of R by a series voltage source Vg, we compute the transfer function from Vp to Vout? Vout _ ay From the theorem in Section 6.1.1, we have Vout |" Soul f) = Se) uo) ay) z = kT RO aus) Sn? R2C2 f+ 1 Thus, the white noise spectrum of the resistor is shaped by a low-pass characteristic (Fig. 7.14). 70 calculate the total noise power at the output, we write ane, ORCL df. 7.16) Prout which, since an‘Types of Noise 2 Sin(f) R Sout (f) 4kTR| “nrR T C Vnout ft t ‘igure 7.14 Noise spectrum shaping by a low-pass filter. reduces to (7.18) Prout = (7.19) Note that the unit ofk7/C is V?. We may alsoconsider /€T/C as the total rms noise voltage measured at the output. For example, with a 1-pF capacitor, the total noise voltage is equal to 64.3 Vins. Equation (7.19) implies that the total noise at the output of the circuit shown in Fig. 7.13 is independent of the value of R. Intuitively, this is because for larger values of R, the associated noise per unit bandwidth increases while the overall bandwidth of the circuit decreases. The fact that kT/C noise can be decreased by only increasing C (if T is fixed) introduces many difficulties in the design of analog circuits (Chapter 12). The thermal noise of a resistor can be represented by a parallel current source as well (Fig. 7.15). For the representations of Figs. 7.12 and 7.15 to be equivalent, we have Vz/R? = T3, that is, 1? = 4kT/R. Note that 7? is expressed in A2/Hz. Depending on the circuit topology, one model may lead to simpler calculations than the other. Noiseless 2, @)2 Resistor Figure 7.15 Representation of resis- tor thermal noise by a current source. Example 7.2 Calculate the equivalent noise voltage of two parallel resistors Ry and Ro (Fig. 7.16(@)]. + 2 Bees pe SR, Vin SR, Yin2 Vert =A, = (@) (b) Figure 7.16212 Chap.7 — Noise Sol As shown in Fig. 7.16(b), each resistor exhibits an equivalent noise current with the spectral density 4KT/R. Since the two noise sources are uncorrelated, we add the powers: Tisor = Tn + Mh 7.20) = 4kT ( 72) Thus, the equivalent noise voltage is given by Vineot = Tar Ri Ra) a2) = ART(RiIIR2), 723) as intuitively expected. Note that our notation assumes a 1-Hz bandwidth, ‘The dependence of thermal noise (and some other types of noise) upon T' suggests that low-temperature operation can decrease the noise in analog circuits. This approach becomes ‘more attractive with the observation that the mobility of charge carriers in MOS devices increases at low temperatures [2].° Nonetheless, the required cooling equipment limits the practicality of low-temperature circuits. MOSFETs MOS transistors also exhibit thermal noise. The most significant source is the noise generated in the channel. It can be proved [3] that for long-channel MOS devices operating in saturation, the channel noise can be modeled by a current source connected between the drain and source terminals (Fig. 7.17) with a spectral density:” Te =4kT y 8m 2) 4 Di2=4kT 19m Figure 7.17 Thermal noise of a MOSFET, The coefficient y (not to be confused with the body effect coefficient!) is derived to be equal to 2/3 for long-channel transistors and may need to be replaced by a larger value for submicron MOSFETs [4]. For example, y is about 2.5 in some 0.25-ym MOS devices. It At extremely low temperatures, the mobility drops due to “carrier freezeout” [2]. The actual equation reads 1? = 4K7'y gar, where ga is the drain-source conductance with Vos = 0, ie.e same as R5j!. For long-channel devices, g4s with Vps = 0 is equal to gy, in saturation.{%.7.1 Statistical Characteristics of Noise 203 voltage v(t) to a load resistance R,, is given by 7.) where T denotes the period.' This quantity can be visualized as the average heat produced in Ry by v(1). How do we define Pz, for a random signal? In the example of Fig. 7.2, we expect that xp(t) generates more heat than x4(t) if the microphone drives a resistive load. However, since the signals are not periodic, the measurement must be carried out over a long time: HT? 42 f (7.2) no Re where x(t) is a voltage quantity. Figure 7.3 illustrates the operation on x4(1) and xp(¢); each signal is squared, the area under the resulting waveform is calculated for a long time 7, and the average power is obtained by normalizing the area to T? Figure 7.3. Average noise power. To simplify calculations, we write the definition of Pay as +77 Poy = fim nif dr, (1.3) T itp where Pa, is expressed in V? rather than W. The idea is that if we know Pay from (7.3), then the actual power delivered to a load Ry. can be readily calculated as Pjy/Rz. In analogy with deterministic signals, we can also define a root-mean-square (rms) voltage for noise as J/Pay where Pay is given by (7.3). 7.1.1 Noise Spectrum The concept of average power becomes more versatile if defined with regard to the frequency content of noise. The noise made by a group of men contains weaker high-frequency com- ponents than that made by a group of women, a difference observable from the “spectrum” "To be more rigorous, v(t) should be replaced by v(r)-v*(), where v*(1) is the complex conjugate waveform. 2Strictly speaking, this definition holds only for “stationary” processes [1]214 Chap.7 Noise — Rat Fact ) © Figure 7.19 Layout of a MOSFET indicating the terminal resistances, (b) circuit model, (c) distributed gate resistance. we observe that the unit transistors near the left end see the noise of only a fraction of Re whereas those near the right end see the noise of most of Rg. We therefore expect the lumped resistor in the noise model to be less than Rg. In fact, it can be proved that Ry = R/3 (Problem 7.3). While the thermal noise generated in the channel is controlled by only the transcondue- tance of the device, the effect of Rg can be reduced by proper layout. Shown in Fig. 7.20 are two examples. In Fig. 7.20(a), the gate is contacted on both ends and in Fig. 7.20(b), the . 8 aie 8 8 @) (b) Figure 7.20 Reduction of gate resistance by (a) adding contacts to both sides or (b) folding. device is folded (Chapter 2), each technique reducing Rg by a factor of 4. We will hereafer neglect the thermal noise due to the ohmic sections of MOS devices.Se.7.2 Types of Noise 215 Example 7.4 Find the maximum thermal noise voltage that the gate resistance of a single MOSFET can generate. Solution If the total distributed gate resistance is Rg, then from Fig. 7.18, the output noise voltage due to Rg is given by R 4k (@nro? (727) 7.2.2 Flicker Noise The interface between the gate oxide and the silicon substrate in a MOSFET entails an interesting phenomenon. Since the silicon crystal reaches an end at this interface, many “dangling” bonds appear, giving rise to extra energy states (Fig.7.21). As charge carri- ers move at the interface, some are randomly trapped and later released by such energy states, introducing “flicker” noise in the drain current. In addition to trapping, several other mechanisms are believed to generate flicker noise [3]. Polysilicon SiOz Dangling Bonds n Crystal Figure 7.21 Dangling bonds at the oxide-silicon interface. Unlike thermal noise, the average power of flicker noise cannot be predicted easily. Depending on the “cleanness” of the oxide-silicon interface, flicker noise may assume considerably different values and as such varies from one CMOS technology to another. The flicker noise is more easily modeled as a voltage source in series with the gate and roughly given by = CyWL f* (7.28) where K is a process-dependent constant on the order of 10-?5 V?F, Note that our notation assumes a bandwidth of 1 Hz. Interestingly, as shown in Fig. 7.22, the noise spectral density is inversely proportional to the frequency. For example, the trap-and-release phenomenon associated with the dangling bonds occurs at low frequencies more often. For this reason, flicker noise is also called 1/f noise. Note that (7.28) does not depend on the bias current or the temperature. This is only an approximation and in reality, the flicker noise equation is somewhat more complex [3]. ‘The inverse dependence of (7.28) on WL suggests that to decrease 1/f noise, the device area must be increased. It is therefore not surprising to see devices having areas of several216 Chap. 7 20log V2 Tog? Figure 7.22 Flicker noise spectrum, thousand square microns in low-noise applications. It is also believed that PMOS deviced exhibit less 1/f noise than NMOS transistors because the former carry the holes in a “buriedl channel,” ie,, at some distance from the oxide-silicon interface. Nonetheless, this difference} between PMOS and NMOS transistors is not consistently observed (3). Example 7-5 For an NMOS current source, calculate the total thermal and 1/f noise in the drain current for a band from 1 kHz to | MHz. Solution The thermal noise current per unit bandwidth is given by 1? ,, = 4kT(2/3)gm. Thus, the total thermal ne integrated across the band of interest is ro 2 io Transot = AKT | 38m ) 0 = 10°) (729) 2 6 a2, ~ AKT (5.9m) x 10° A? (730) For 1/f noise, the drain noise current per unit bandwidth is obtained by multiplying the noise voltage at the gate by the device transconductance: Ruy +B. (731) The total 1/f noise is then equal to Ue gp eee i a 732) et tei. f 33) a3) ‘The above example raises an interesting question. What happens to /2 if the lower end of the band, f,, is zero rather than 1 kHz? Equation (7.33) then contains the natura‘Types of Noise 217 logarithm of zero, yielding an infinite value for the total noise. To overcome the fear of infinite noise, we make two observations. First, extending f, to zero means that we are interested in arbitrarily slow noise components. A noise component at 0.01 Hz varies significantly in roughly 10 s and one at 10-® in roughly one week. Second, the infinite flicker noise power simply means that if we observe the circuit for a very long time, the very slow noise components can randomly assume a very large power level. At such slow rates, noise becomes indistinguishable from thermal drift or aging of devices. The foregoing observations lead to the following conclusions. First, since the signals encountered in most applications do not contain significant low-frequency components, our observation window need not be very long. For example, voice signals display negligible energy below 20 Hz and if a noise component varies at a lower rate, it does not corrupt the voice significantly. Second, the logarithmic dependence of the flicker noise power upon ‘fr allows some margin for error in selecting f;. For example, if the band of interest is 80 wide that the total integrated thermal noise power is comparable with the flicker noise contribution, then the choice of f; is quite relaxed. In order to quantify the significance of 1/f noise with respect to thermal noise for a given device, we plot both spectral densities on the same axes (Fig. 7.23). Called the 1/f noise “comer frequency,” the intersection point serves as a measure of what part of the band 201097 t Corner Thermal Figure 7.23 Concept of flicker noise fe F (log scale) comer frequency. is mostly corrupted by flicker noise. In the above example, the 1/f noise comer, fc, of the output current is determined as 2 K ie aut (Fen) = core Ree (7.35) that is, K 3 fo= aw aT (7.36) This result implies that fc generally depends on device dimensions and bias current, Nonetheless, since for a given L, the dependence is relatively weak, the 1/f noise cor ner is relatively constant, falling in the vicinity of 500 kHz to | MHz for submicron transistors. Example 7.6 Fora 100-14m/0.5-zm MOS device with gm = 1/(100),the 1/f noise comer frequenc} to be 500 kHz. If fox = 90 A, what is the flicker noise coefficient, K, in this technology?218 Chap.7 Noise Solution For fox = 90 A, we have Coy = 3.84 fF/m?. Using Eq, (7.36), we write K I 3 = Se 7.3) 3.84 x 100 x 0.5 x 10-15 ° 100" 8 x 1.38 x 10-23 x 300 500 kHz, That is, K = 1.06 x 107% V?F. 7.3 Representation of Noise in Circuits Consider a general circuit with one input port and one output port (Fig. 7.24). How do we quantify the effect of noise here? The natural approach would be to set the input to zero and calculate the total noise at the output due to various sources of noise in the circuit. This is indeed how the noise is measured in the laboratory or in simulations, Figure 7.24 Noise sources in a circuit. Example 7.7 What is the total output noise voltage of the common-source stage shown in Fig. 7.25(a)? @ ) Figure 7.25 (a) CS stage, (b) circuit including noise sources.Representation of Noise in Circuits 219 Solution We model the thermal and flicker noise of My by two current sources: /?,, = 4kT(2/3)gm and Thajp = Kem/(Cox WLf). We also represent the thermal noise of Rp by a current source I? ep 4KT/Rp. The output noise voltage per unit bandwidth is therefore equal to 2 K = 4kT 4KT Sam gh +) RB. 1: ( a"! Cows f 7) 2 CS Note that the noise mechanisms are added as “power” quantities because they are uncorrelated. The value given by (7.38) represents the noise power in I Hz at a frequency f. The total output noise can bbe obtained by integration over the bandwidth of interest. While intuitively appealing, the output-referred noise does not allow a fair comparison of the performance of different circuits because it depends on the gain. For example, as depicted in Fig. 7.26, if a common-source stage is followed by a noiseless amplifier having Yoo Figure 7.26 Addition of gain stage to aCS stage. al a voltage gain A), then the output noise is equal to the expression in (7.38) multiplied by AZ. Considering only the output noise, we may conclude that as A; increases, the circuit becomes noisier, an incorrect result because a larger A, also provides a proportionally higher signal level at the output. That is, the output signal-to-noise ratio (SNR) does not depend on Ay. To overcome the above quandary, we usually specify the “input-referred noise” of cir- cuits. Illustrated conceptually in Fig. 7.27, the idea is to represent the effect of all noise sources in the circuit by a single source, V2,,, at the input such that the output noise Noisy Circuit Noiseless Circuit (a) (b) Figure 7.27 Determination of input-referred noise voltage,Chap.7 Noise 7.21(b) equals that in Fig. 7.27(a). If the voltage gain is Ay, then we must have Veou = A2Vz2,,» that is, the input-referred noise voltage in this simple case is given by the output noise voltage divided by the gain. Example 7.8 For the circuit of Fig. 7.25, calculate the input-referred noise voltage. Solution We have (139) (7.40) ART — + aan Bem * GoW Ff * BRD’ Note that the first term in (7.41) can be viewed as the thermal noise of a resistor equal to 2/(3gm) placed in series with the gate. Similarly, the third term corresponds to the noise of a resistor equal to (g,Rp)~!. We sometimes say the “equivalent thermal noise resistance” of a circuit is equal to Rr, meaning that the total input-referred thermal noise of the circuit in unit bandwidth is equal to 4kT Rr. At this point of our study, we make two observations. First, the input-referred noise and the input signal are both multiplied by the gain as they are processed by the circuit. Thus, the input-referred noise indicates how much the input signal is corrupted by the circuit's noise, i.e., how small an input the circuit can detect with acceptable SNR. For this reason, input-referred noise allows a fair comparison of different circuits. Second, the input-referred noise is a fictitious quantity in that it cannot be measured at the input of the circuit. The two circuits of Figs. 7.27(a) and (b) are mathematically equivalent but the physical circuit is still that in Fig. 7.27(a). In the foregoing discussion, we have assumed that the input-referred noise can be mod- eled by a single Voltage source in series with the input. This is generally an incomplete representation if the circuit has a finite input impedance and is driven by a finite source impedance. To understand why, consider the common-source stage of Fig. 7.28(a), where the input capacitance is denoted by C;, and 1/f noise is neglected for simplicity. From Ea. (7A1), the input-referred noise voltage of the circuit is given by 8kT /(38m)+4kT /(g2 Ro) Now suppose the preceding stage is modeled by a Thevenin equivalent having an inductive output impedance (Fig. 7.28(b)]. Simplifying the circuit for noise calculations as shown in Fig. 7.28(c), we seek to find the output noise as L, increases. Owing to the voltage division between Ls and 1/(Cins), the effect of V2, at the gate of M; and hence at the output vanishes as Ly approaches infinity. This result, however, is incorrect because the output noise of the circuit is equal to (8kT/3)gmR2, + 4kT Rp and independent of Ly and Ci.Representation of Noise in Circuits 221 (b) © Figure 7.28 CS stage including input capacitance, (b) CS stage stimulated by a finite source impedance, (c) Effect of single noise source. Let us summarize the problem. If the circuit has a finite input impedance, modeling the input-referred noise by merely a voltage source implies that the output noise van- ishes as the source impedance becomes large, an incorrect conclusion. To resolve this issue, we model the input-referred noise by both a series voltage source and a parallel current source (Fig. 7.29) so that if the output impedance of the preceding stage assumes large values—thereby reducing the effect of V;,,—the noise current source still flows through a finite impedance, producing noise at the input. It can be proved that V,, and FZ, are necessary and sufficient to represent the noise of any linear two-port circuit [5]. Figure 7.29 Representation of noise by voltage and current sources. How do we calculate V2, and 72,,,? Since the model is valid for any source impedance, we consider two extreme cases: zero and infinite source impedances. As shown in Fig. 7.30(a), if the source impedance is zero, /?,,, flows through V2, and has no effect on the output. Thus, the output noise measured in this case arises solely from V,.,,- Similarly, if the inp is open (Fig. 7.300}, then Vz, has no effect and the output noise is due to only 7Z,,. Let us apply this method to the citcuit of Fig. 7.28.222 Chap.7 Noise Noisy Circuit (b) Figure 7.30 Calculation of input-referred noise (a) voltage, and (b) current. Example 7.9 Calculate the input-referred noise voltage and current of Fig. 7.28, Solution From (7.41), the input-referred noise voltage (excluding 1/f noise) is simply z= Be VE, =4kT 7.82 nin = MTZ ERD Ve) ‘As depicted in Fig. 7.31(a), this voltage generates the same output noise as the actual circuit if the input is shorted. ‘To obtain the input-referred noise current, we open the input and find the output noise in terms of Tj, (Fig. 7.31(b)]. The noise current flows through Cin, generating at the output 2 ) mR. a8) This value must be equal to the output of the noisy circuit when its input is open: vr a. 4kT Veour = (4kT = am + —— ) R3, 4M) Fou = (84758 +o) a ay Figure 7.31Representation of No in Circuits 223 From (7.43) and (7.44), it follows that ART (2 a: "ula [El ee a): as ‘The reader may wonder ifthe use of both a voltage source and a current source to represent the input-referred noise “counts the noise twice.” We utilize the circuit of Fig. 7.28 as an ex- ample to demonstrate that this is not so. Considering the environment depicted in Fig. 7.32, ‘we prove that the output noise is correct for any source impedance Zs. Assuming Zs is noise- Figure 7.32 CS stage stimulated by a source impedance. less for simplicity, we first calculate the total noise voltage at the gate of M; dueto V,,, and z I ;,- How is this voltage obtained: by superposition of voltages or powers? The two sources and [2,, are in general correlated simply because they may represent the same noise mechanisms in the circuit, In fact, Eqs. (7.42) and (7.45) can be respectively rewritten as 1 Vajin = Vaan + Vn,RD (7.46) Tnsin = CinS Vn. + Vn,RD> (7.47) &mRo where V,,mi denotes the gate-referred noise voltage of M; and Vp.xp the noise voltage of Rp. We recognize that V,,yi and V,,eo appear in both V,,i, and Jp.in, creating a strong, correlation between the two. Thus, the calculations must use superposition of voltages—as if Vp,in and J, in Were deterministic quantities. Adding the contributions of Vp, and Jy, i, at node X in Fig. 7.32, we have Vax = Vain (7.48) T +Z; +Z: Ca Ce + IninZs ~~ ZsCins +1 * (7.49)224 Chap.7 Noise ‘Substituting for V,,in and Jy,in from (7.46) and (7.47), respectively, we obtain 1 [ran 1 Bp Vn + CinsZs (Vom + ao ¥a) | 50) 8mRo &mRp * ZsCns +1 = Van + Vn,RD- (7.51) &mRo Note that V,,x is independent of Zs and Cin. It follows that Vizour = Sn Rb View (732) = 4kT (em + z) Rb, (7.53) the same as (7.44). 7.4 Noise in Single-Stage Amplifiers Having developed basic mathematical tools and models for noise analysis, we now study the noise performance of single-stage amplifiers at low frequencies. Before considering specific topologies, we describe a lernma that simplifies noise calculations. Lemma_ The circuits shown in Fig. 7.33(a) and (b) are equivalent at low frequencies if ‘V2 = [2/g2, and the circuits are driven by a finite impedance. Proof. Since the circuits have equal output impedances, we simply examine the output short-circuit currents (Figs. 7.33(c) and (d)]. It can be proved (Problem 7.4) that the output noise current of the circuit in Fig. 7.33(c) is given by Trout eee (7.54) "= Z5(@m + Wro) +1 os) and that of Fig. 7.33(d) is nV hut = “ as Zs(8m + 1/ro) +1" Equating (7.54) and (7.55), we have V, = In/&m- This lemma suggests that the noise source can be transformed from a drain-source curea toa gate series voltage for arbitrary Zs.Noise in Single-Stage Amplifiers 225 Yoo 2. Virout Verout eo 2 My, Zs 25 ® o Yoo 1, nroutt nou oo 72 M, . Zs © @ Figure 7.33 Equivalent CS stages. 7.4.1 Common-Source Stage From Example 7.8, the input-referred noise voltage per unit bandwidth of a simple CS stage is equal to a 2 1 Kil v2, T(—+5— = 7.56) min = Ak (sr * am) * away 2 From the above lemma, we recognize that the term 4kT[2/(3g,.)] is in fact the thermal noise current of M; expressed as a voltage in series with the gate. How can we reduce the input-referred noise voltage? Equation (7.56) implies that the transconductance of M; must be maximized. Thus, the transconductance must be maximized if the transistor is to amplify a voltage signal applied to its gate (Fig. 7.34(a)} whereas it must be minimized if the transistor operates as a current source (Fig. 7.34(b)]. Vout Io. My Yeh m, Figure 7.34 Voltage amplification (@) ) versus current generation.226 Chap.7 Noise Example 7.10 Calculate the input-referred thermal noise voltage of the amplifier shown in Fig. 7.35(a), assuming both transistors are in saturation. Also, determine the total output thermal noise if the circuit drives a load capacitance Cz. What is the output signal-to-noise ratio if a low-frequency sinusoid of amplitude Vm is applied to the input? Yoo YoE me Vout Vine my @ O) Figure 7.35 Solution Representing the thermal noise of My and M by current sources (Fig. 7.35(b)] and noting that they are uncorrelated, we write a : = 4kT (jen + Ft) (roillroay. (757) Since the voltage gain is equal to gmi1(ro1 lIro2), the total noise voltage referred to the gate of My is = = : 1 Baie. 7.58 Vn aur (Fem + 36 ) 138) aur (=? 4 28m). 9) Semi” 3 52, Equation (7.59) reveals the dependence of V2, upon gmi and gm2, confirming that gm? must be minimized because Mz serves as a current source. ‘The reader may wonder why M; and Mz in Fig. 7.35 exhibit different noise effects. After alli the noise currents of both transistors flow through ro1 iro2, why should gy be maximized and gaa minimized? This is simply because, as gmx increases, the output noise voltage tises in proportion VEmi Whereas the voltage gain of the stage increases in proportion to gm1. AS a result, the input referred noise voltage decreases. To compute the total output noise, we integrate (7.57) across the band: a _ [Par (2,. 22 df Vpout.tor ART (58m + 58m 02° 1.80) [780 Gen + em) onto? ros TORT : Using the results of Example 7.1, we have oe kT 2 (Sm m2 Xr llro2) —. (7.61 Vaoursor = 3(8mt + &maXolroave i)Noise in Single-Stage Amplifiers 227 An input sinusoid of amplitude Vm yields an output amplitude equal to gmi(ro1llro2)Vm. The output SNR is equal to the ratio of the signal power and the noise power: snuGosteon vn 1 SN Royy = | Sot 02 | 7.62 [ v2 (2/3\Gm1 + &m2X(ro1llro2MkT/CL) a 2 rosin = 3CL_ Smroiliron) y, co © ART ami + Bm ‘We note that to maximize the output SNR, Cy, must be maximized, ice, the bandwidth must be mini- mized. Of course, the bandwidth is also dictated by the input signal spectrum. This example indicates that it becomes exceedingly difficult to design broadband circuits while maintaining a low noise. Itis also important to observe from (7.56) that the noise contributed by Rp in Fig. 7.25(a) decreases as Rp increases. This is again because the noise voltage due to Rp at the output is proportional to /Rp while the voltage gain of the circuit is proportional to Rp. Example 7.11 Calculate the input-referred 1/f and thermal noise voltage of the circuit depicted in Fig. 7.36(a) assuming My and Mz are in saturation. Vpp a a2 . 2 oom hegre : Vino Ms Ohm, (a) (b) Figure 7.36 Solution ‘We model the 1/f and thermal noise of the transistors as voltage sources in series with their gates [Fig. 7.36(b)]. The noise voltage at the gate of Mz experiences a gain of gm2(Rollroil7o2) as it appears at the output. The result must then be divided by gmi(Rpliro1 li'o2) to be referred to the main input. The noise current of Rp is multiplied by Ro liro1 liroz and divided by &mi(Rp i701 \\r02). ‘Thus, the overall input-referred noise voltage is given by Kraig Kye) lakh, +t | Seem 4 Ew ly ee ) Con [A= Win | F* Ro : Vin = 405 (82+ 3\ gui 8m where Kp and Ky denote the flicker noise coefficients of PMOS and NMOS devices, respectively. As expected, the input-referred noise voltage increases if gyq2 increases.