Module 2
Basic Concepts
Modules and Ports
Basic Concepts
Lexical Conventions
Similar to C programming language.
Case sensitive(lower case).
Verilog Contains stream of tokens
Comments
Delimiters
Numbers
Strings
Identifiers
Keywords
Lexical Conventions
1. Whitespace
Blank spaces(\b)
Tabs(\t)
Newlines(\n)
Usually ignored except when it separates tokens.
White space not ignored in strings.
Lexical Conventions
2. Comments
For readability and documentation.
Two ways to write
Single line comment
Multiple line comment
Ex: a = b && c; // This is a one-line comment
/ * This is a multiple line
comment * /
/ * This is / * an illegal * / comment * /
Lexical Conventions
3. Operators
Operators are of three types
Unary
a = ~ b; // ~ is a unary operator. b is the operand
Binary
a = b && c; // && is a binary operator. b and c are
operands
Ternary
a = b ? c : d; // ?: is a ternary operator. b, c and d
are operands
Lexical Conventions
4. Number Specification
Two types od number specification in Verilog
Sized
Unsized
a. Sized
Sized numbers are represented as
<size> ‘<base format> <number>.
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.
Lexical Conventions
b. Unsized
Numbers that are specified without a <base
format> specification are decimal numbers by
default.
Numbers that are written without a <size>
specification have a default number of bits that is
simulator- and machine-specific (must be at least
32).
23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'021 // This is a 32-bit octal number
Lexical Conventions
X or Z values
Unknown value -> x
High Impedance -> z
12'h13x // This is a 12-bit hex number; 4 least
significant bits unknown
6'hx //This is a 6-bit hex number
32'bz //This is a 32-bit high impedance
number
Lexical Conventions
Negative Numbers
Minus sign before the size.
-8'd3 // 8-bit negative number stored as 2's
complement of 3
-6’sd3 // Used for performing signed integer
math
4'd-2 // Illegal specification
Lexical Conventions
Underscore characters and question marks
An underscore character “_" is allowed anywhere in a
number except the first character.
Underscore characters are allowed only to improve
readability of numbers and are ignored by Verilog.
A question mark "?" is the Verilog HDL alternative for z
in the context of numbers.
12'b1111_0000_1010 // Use of underline characters
for readability
4'b10?? // Equivalent of a 4'b10zz
Lexical Conventions
5. Strings
“Sequence of characters enclosed by double
quotes”
Should contain single line without carriage
return (cannot be on multiple lines)
Strings are treated as a sequence of one-byte
ASCII values.
"Hello Verilog World" // is a string
“a / b” // is a string
Lexical Conventions
6. Identifiers and Keywords
Keywords are special identifiers reserved to define the
language constructs.
Identifiers are names given to objects so that they can be
referenced in the design.
Identifiers
Alphanumeric characters, underscore, dollar sign.
Case sensitive.
Should start with alphabetic character or underscore.
reg value; // reg is a keyword; value is
an identifier
input clk; // input is a keyword, clk is
an identifier
Lexical Conventions
7. Escaped Identifiers
Escaped identifiers begin with the backslash ( \ )
character and end with whitespace (space, tab, or
newline).
Any printable ASCII character can be included in
escaped identifiers.
\a+b-c
\**my_name**
Data Types
1. Value Set
Verilog supports four values and 8 strengths
to model the functionality of real hardware.
Value levels
Value Level Condition in Hardware Circuits
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state
Data Types
Strength levels
Strength Level TYPE Degree
Supply Driving strongest
Strong Driving
pull Driving
large Storage
weak Driving
medium Storage
small Storage
highz High Impedance weakest
Data Types
If two signals of unequal strengths are driven on
a wire, the stronger signal Prevails
For example, if two signals of strength strong1
and weak0 contend, the result is resolved as a
strong1.
If two signals of equal strengths are driven on a
wire, the result is unknown. If two signals of
strength strong1 and strong0 conflict, the result
is an X
.
Data Types
2. Nets
Nets represent connections between hardware elements.
Just as in real circuits, nets have values continuously driven on them by
the outputs of devices that they are connected to.
Nets are declared primarily with the keyword wire.
The terms wire and net are often used interchangeably.
Nets are one bit value by default unless they are explicitly declared as
vectors.
The default value of a net is Z (if no driver)
Data types
wire o; // Declare net o for the above
circuit
wire a,b; // Declare two wires a,b for the
above circuit
wire d = l'bO; // Net d is fixed to logic
value 0 at declaration.
Data Types
3. Registers
Registers represent data storage elements. Registers
retain value until another value is placed onto them.
Unlike a net, a register does not need a driver. Verilog
registers do not need a clock as hardware registers do.
Values of registers can be changed anytime in a simulation
by assigning a new value to the register.
Register data types are commonly declared by the keyword
reg. The default value for a reg data type is X.
Data Types
Ex: reg reset; // declare a variable reset that
can hold its value
initial // this construct will be
discussed later
begin
reset = 1'b1; //initialize reset to 1 to reset the
digital circuit.
#100 reset = 1'b0; // after 100 time units reset is
deasserted.
end
Data Types
Registers can also be declared as signed
variables.
Such registers are used for signed
arithmetic.
Ex: reg signed [63:0] m; // 64 bit signed value
Data Types
4. Vectors
Nets or reg data types can be declared as vectors (multiple bit
widths). If bit width is not specified, the default is scalar (1-bit).
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
reg clock; // scalar register, default
reg [0 : 40] virtual_addr; // vector register, virtual address 41 bits
wide
Vectors can be declared at [high# : low#] or
[low# : high#], but the left number in the squared brackets is
always the most significant bit of the vector.
Data Types
Vector part select
busA[7] // bit # 7 of vector busA
bus[2:0] // Three least significant bits of vector
bus,
// using bus[0:2] is illegal because the significant
bit //should always be on the left of a range
specification
Virtual_addr[0:1] //TWO most significant bits of
vector virtual_addr
Data Types
Variable Vector part select
O [<starting bit >+:width] - part-select
increments from starting bit
O [<starting bit >-:width] - part-select
decrements from starting bit
Data Types
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
//Using a variable part select, one can choose parts
byte = data1[31-:8]; //starting bit = 31, width =8 => data[31:24]
byte = data1[24+:8]; //starting bit = 24, width =8 => data[31:24]
byte = data2[31-:8]; //starting bit = 31, width =8 => data[24:31]
byte = data2[24+:8]; //starting bit = 24, width =8 => data[24:31]
Data Types
The starting bit can also be a variable. The width has
to be constant. Therefore, one can use the variable part
select in a loop to select all bytes of the vector.
for (j=0; j<=31; j=j+1)
byte = data1[(j*8)+:8]; //Sequence is [7:0], [15:8]...
[255:248]
//Can initialize a part of the vector
data1[(byteNum*8)+:8] = 8'b0; //If byteNum = 1, clear
8 bits [15:8]
Data Types
5. Integer, Real, and Time Register Data Types
Integer
An integer is a general purpose register data type used for
manipulating quantities. Integers are declared by the keyword
integer.
The default width for an integer is the host-machine word size,
which is implementation specific but is at least 32 bits.
Registers declared as data type reg store values as unsigned
quantities, whereas integers store values as signed quantities.
integer counter; // general purpose variable use as
a counter.
initial
counter = -1; // A negative one is stored in the
counter
Data Types
Real
Real number constants and real register data types
are decIared with the keyword real.
They can be specified in decimal notation (e.g., 3.14)
or in scientific notation (e.g., 3e6, which is 3 X 106).
their default value is 0.
When a real value is assigned to an integer, the real
number is rounded off to the nearest integer.
Data Types
real delta; // Define a real variable called
delta
initial
begin
delta = 4e10; // delta is assigned in
scientific notation
delta = 2.13; // delta is assigned a value
2.13
end
integer i; // Define an integer i
initial
i = delta; // i gets the value 2 (rounded
value of 2.13)
Data Types
Time
Verilog simulation is done with respect to simulation time.
A special time register data type is used in Verilog to store
simulation time.
A time variable is declared with the keyword time. The width for
time register data types is implementation specific but is at
least 64 bits
time save_sim_time; // Define a time variable save_sim_time
initial
Save_sim_time = $time; // Save the current simulation
//time
Simulation time is measured in terms of simulation seconds (s)
Data Types
6. Arrays
Arrays are allowed in Verilog for reg, integer, time, and vector register data
types. Arrays are not allowed for real variables.
Arrays are accessed by <array-name> [<subscript>]
Vector is a single element that is n bit wide
Array are multiple elements that are 1 bit or n bit wide
examples
integer count[0:7]; //an array of 8 count variables
reg bool[31:0]; //Array of 32 one_bit boolean register variables
time chk_point[1:100]; //Array of 100 time checkpoint variables
reg [4 : 0] port_id[0 : 7]; //Array of 8port_ids; each port_id is 5 bits wide
integer matrix[4:0][0:255]; // Two dimensional array of integer
Wire [7:0] w_array2 [15:0]; //Declare an array of 8 bit vector wire
Wire w_array1 [7:0] [5:0]; //Declare an array of single bit vector wires
Reg [63:0] array_4d [15:0][7:0]{7:0][255:0] //Four Dimesional Array
Data Types
Examples of assignments to elements of array
1. count[5] // 6th element of array of count variables
2. chk_point[100] //100th time check point value
3. port_id[3] //4th element of port_id array. This is a 5-
bit value.
4. matrix[1][0] = 33559; // set values of element indexed by
[1][0] to 33559
5. array_4d [0] [0] [0] [0] [15:0] = 0; // clear bits 15:0 of the
register accessed by indices [0]
[0] [0] [0]
6. port_id = 0; // illegal syntax
7. Matrix [1] =0; // illegal syntax
7. Memories Data Types
Memories are modeled in Verilog simply as an array of registers. Each
element of the array is known element or word.
reg mem1bit[0:1023]; //memory mem1bit with 1K 1-bit words
reg [7 : 0] membyte [0 : 1023]; // memory membyte with 1K 8-bit words
(bytes)
membyte[511] // fetches 1 byte word whose address is
511.
8. Parameters
Verilog allows constants to be defined in a module by the keyword
parameter.
parameter port_id = 5; //Defines a constant port_id
parameter cache_line_width=256; //constant defines width of
cache line
Data Types
9. Strings
Strings can be stored in reg. The width of the register
variables must be large enough to hold the string.
Each character in the string takes up 8 bits (1 byte).
reg [8*18:1] string_value; //Declare a variable that is 18
bytes wide
initial
String_value = "Hello Verilog World"; // String can be stored in
variable
Data Types
O Special characters can be Displayed only
when they are preceded by escape
characters.
System Tasks and Compiler
Directives
1. System Tasks
Verilog provides standard system tasks to do certain routine
operations.
All system tasks appear in the form $<keyword>.
Displaying information
$display is the main system task for displaying values of variables
or strings or expressions.
$display(pl, p2, p3 ,....., pn);
pl, p2, p3, ..., pn can be quoted strings or variables or
expressions.
A $display inserts a newline at the end of the string by default.
A $display without any arguments produces a new line
Format Display
%d or %D Display variable in decimal
%b or %B Display variable in binary
%s or %S Display string
%h or %H Display variable in hex
%c or %C Display ASCII character
%m or %M Display hierarchical name (no argument required)
%v or %V Display strength
%o or %O Display variable in octal
%t or %T Display in current time format
%e or %E Display real number in scientific format (e.g., 3e10)
%f or %F Display real number in decimal format (e.g., 2.13)
%g or %G Display real number in scientific or decimaI,
System Task
$Display task examples
//Display the string in quotes
$display("Hello Verilog World");
-- Hello Verilog World
//Display value of current simulation time 230
$display ($time) ;
-- 230
//Display value of 41-bit virtual address 1fe0000001c and
time 200
reg [0:40] virtual_addr;
$display("At time %d virtual address is %h”, $time, virtual_addr);
-- At time 200 virtual address is 1fe0000001c
System Task
//Display Value of port_id 5 in binary
Reg [4:0] port_id;
$display(“ID of the port is %b”, port_id);
-- ID of the port is 00101
// Display X characters
reg [3:0] bus;
$display(bus value is %b, bus);
bus value is 10xx;
//Display Hierarchical name
$display(“ This string is display from %m level of
hierarchy”);
This string is display from top.p1 level of hierarchy
System Task
// Display special characters newline %
$display(“This is a \n multiline string with a
%% sign”);
--This is a
--multiline string with a % sign”
System Task
Monitoring information
Verilog provides a mechanism to monitor a signal
when its value changes.
This facility is provided by the $monitor task.
$monitor(p1 ,p2,p3 ,...., pn);
The parameters pl, p2, ... , pn can be variables,
signal names, or quoted strings.
Unlike $display, $monitor needs to be invoked only
once.
Only one monitoring list can be active at a time.
System Task
If there is more than one $monitor statement in your
simulation, the last $monitor statement will be the
active statement.
The earlier $monitor statements will be overridden.
Two tasks are used to switch monitoring on and off.
$monitoron;
$monitoroff;
Monitoring is turned on by default during simulation.
System Task
Examples
//Monitor time and value of the signals clock and reset
//Clock toggles every 5 time units and reset goes down at 10
time unit:
initial
begin
$monitor($time,” Value of signals clock = %b reset = %b",
clock, reset),
end
Partial output of the monitor statement:
-- 0 Value of signals clock = 0 reset = 1
-- 5 Value of signals clock = 1 reset = 1
-- 10 Value of signals clock = 0 reset = 0
System Task
Stopping and finishing in a simulation
The task $stop is provided to stop during a simulation.
Usage: $stop;
The $stop task puts the simulation in an interactive mode.
The designer can then debug the design from the interactive
mode.
The $stop task is used whenever the designer wants to
suspend the simulation and examine the values of signals in
the design.
The $finish task terminates the simulation.
Usage: $finish;
System Task
Example
// Stop at time 100 in the simulation and examine the results
// Finish the simulation at time 1000 units
initial
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time
//=100
#900 $finish; // This will terminate the simulation at
//time = 1000
end
Compiler Directives
'define
The 'define directive is used to define text macros in
Verilog
//define a text macro that defines default word size
//Used as 'WORD_SIZE in the code
'define WORD_SIZE 32
//define an alias. A $stop will be substituted wherever 'S appears
'define S $stop.
//define a frequently used text string
'define WORD_REG reg [31:0]
Compiler Directives
'include
The 'include directive allows you to include entire contents
of a Verilog source file in another Verilog file during
compilation.
This directive is typically used to include header files,
which typically contain global or commonly used
definitions
// Include the file header.v, which contains declarations in the main verilog
file design.v
'include header.v
...
...
<Verilog code in file design.vz
MODULES AND PORTS
MODULE
Example – SR Latch
Components of SR Latch
Design Block
//module name and port list
//SR_latch module
Module SR_latch(Q, Qbar, Sbar, Rbar);
//port declarations
Output Q, Qbar;
Input Sbar, Rbar;
//Instantiate lower level modules
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
//endmodule statement
endmodule
Stimulus block
//module name and port list
//stimulus block
Module Top;
//Declarations of wire, reg and other variables
Wire q, qbar;
Reg set, reset
//Instantiate lower level modules
SR_latch m1(q, qbar, ~set, ~reset);
//Behavioral block
initial
begin
$monitor($time, “set = %b, reset = %b, q = %b\n”,
set, reset, q);
set =0; rest = 0;
#5 reset =1;
#5 reset =0;
#5 set =1;
end
//endmodule statement
endmodule
PORTS
O List of Ports
Port Declaration
Example -1
Example -2
Example -3
ANSI C Style Port Declaration Syntax
Port Connection Rules
Port Connection Rules
Inputs
internally – always nets
Externally - reg or net.
Outputs
Internally – reg or net
Externally - net
Inouts
Internally and externally always nets
Width matching
Legal to connect internal and external items of different
sizes.
Unconnected Ports
Verilog allows ports to remain unconnected.
Fulladd4 fa0(SUM, , A, B C_IN);
Example of illegal port Connection
Connecting Ports to External Signals
1. Connecting by ordered list
2. Connecting ports by name
Unconnected ports can be dropped
Hierarchical Names
Hierarchical name referencing
to refer module instances, signal or variable
which are all defined as identifiers.
List of identifiers are separated by dots for
each level of hierarchy.
Top level module is called root module
because it is not instantiated anywhere. It is
the starting point.