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RTL Simulation and Synthesis With PLDs QP Mid-1

This document contains a midterm exam for an RTL Simulation and Synthesis with PLDs course. The exam contains 3 questions worth 10 marks each, for a total of 30 marks. Question 1 involves designing a sequence detector circuit and explaining clock issues. Question 2 asks the student to write VHDL for the control logic of a vending machine. Question 3 is a short note on the ASIC design flow. The exam is for an M.Tech programme in the Department of Electronics and Communication Engineering and covers course outcomes at Bloom's taxonomy levels 1-6.

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1K views1 page

RTL Simulation and Synthesis With PLDs QP Mid-1

This document contains a midterm exam for an RTL Simulation and Synthesis with PLDs course. The exam contains 3 questions worth 10 marks each, for a total of 30 marks. Question 1 involves designing a sequence detector circuit and explaining clock issues. Question 2 asks the student to write VHDL for the control logic of a vending machine. Question 3 is a short note on the ASIC design flow. The exam is for an M.Tech programme in the Department of Electronics and Communication Engineering and covers course outcomes at Bloom's taxonomy levels 1-6.

Uploaded by

baburao_kodavati
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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AUTONOMOUS

Department of Electronics and Communication Engineering


MID-I QUESTION PAPER –NOVEMBER-2019

Course Code:
Programme: M. Tech
Year / Sem: I/I UR19-PC-PG-EC101
(VLSI&ES)
Date: 11.11.2019
Course Name: RTL Simulation
Total Marks: 30M Time: 90 min
and Synthesis with PLDs
CO: Course Outcome Level: Bloom’s Taxonomy (Level 1-6)
Answer All questions (3X10=30M)
CO
Level Q.No Question
no.
A) Design a one-input one-output sequence
6 1 detector that produces an output value 1 every
1 time the sequence 0101 is detected and an output
2 value 0 at all other times.
B) Explain different type of Clock issues.
3 6 2 Write a VHDL for the Control Logic of a Vending Machine.
2 6 3 Write a short note on ASIC Design Flow.

AUTONOMOUS
Department of Electronics and Communication Engineering
MID-I QUESTION PAPER –NOVEMBER-2019

Course Code:
Programme: M. Tech
Year / Sem: I/I UR19-PC-PG-EC101
(VLSI&ES)
Date: 11.11.2019
Course Name: RTL Simulation
Total Marks: 30M Time: 90 min
and Synthesis with PLDs
CO: Course Outcome Level: Bloom’s Taxonomy (Level 1-6)
Answer All questions (3X10=30M)
CO
Level Q.No Question
no.
A) Design a one-input one-output sequence
6 1 detector that produces an output value 1 every
1 time the sequence 0101 is detected and an output
2 value 0 at all other times.
B) Explain different type of Clock issues.
3 6 2 Write a VHDL for the Control Logic of a Vending Machine.
2 6 3 Write a short note on ASIC Design Flow.

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