MENTOR GRAPHICS PROCEDURE

INTRODUCTION:
This document gives a overview of how to design & simulate with Mentor Graphics tools.
There are five basic steps:
1. Design the schematic in Pyxis.
2. Simulate the schematic and check for parameters.
3. Layout the schematic in Pyxis.
4. Perform Physical Verification using Caliber which includes DRC, LV, PEX & Net list Extraction.
5. Back annotation of parasitic into the schematic.

Invoking to Mentor Graphics Tools:

On desktop, right click, select open in terminal, in terminal Window enter the following commands

Type mkdir new (Creating working directory)( Only for the 1st time)
Type cd new (entering into working directory) now we are in work directory

Type csh and press enter.

 Type source /Mentor_Graphics/cshrc/ams_2009.cshrc and press enter

Type dmgr_ic & and press enter

Now the Pyxis Project Manager will open
CREATING A PROJECT:
To create a new project click on File…New project, this will invoke the new project window as shown.

[NOTE: Check that the project path should be in the directory of the file we created if not change its
directory to the created folder]

in project path click browse and give file name, then click on
Next technology libraries have to be added to the project. In order to add the technology files
browse and goto
/home/software/mgc/FOUNDRY/GDK/Pyxis_SPT_HEP/ic_reflibs/tech_libs/generic13, then click ok
Again click on OK then manage external/logic libraries window will pop up as shown.

Click on the Add Standard Libraries. The libraries will be added up as shown below and
click
on OK.
Then the pyxis project manager window will be shown where the technology libraries are added
to the project and are placed below the project name.

CREATING A LIBRARY:
Now Right Click on your project, New---Library---give the Library Name...click OK.
CREATING A SCHEMATIC CELL VIEW:
Now to create a schematic, right click on the Library name and select new schematic or click on
the new cell and select the icon in the icon bar.

Now name the schematic/cell name. and click on OK

which in turn leads to the pyxis schematic editor window as shown.

CREATING A SCHEMATIC:
In this section you will become familiar with placing primitive analog devices for a inverter.
You‟ll learn how to:
• place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• route devices
• edit device parameter values
• name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using eldo
• view results

CREATING AN INVERTER:
Placing devices:
From the left icon bar press on add instance icon or press “I”

Double click on generic13 in the library list. And then follow the path to select pmos from
$generic13/symbols/pmos as shown in the figure.
Select the pmos and click on OK to place the pmos on the workspace

And then follow the path to select nmos from $generic13/symbols/nmos

Select the nmos and click on OK to place the nmos on the workspace
ADDING THE PORTS AND CONNECTING THE DEVICES:
Now Click Library

Select generic library and add portin, portout, VDD and ground
Adding Wires to a Schematic:
Click the wire (narrow) icon in the schematic window.
(or)
goto ADD, select wire

In the schematic window, click on a pin of one of your components as the first point for your wiring. A
diamond shape appears over the starting point of this wire.
Follow the prompts at the bottom of the design window and click left on the
destination points for your wire. A wire is routed between the source and destination
points.
Complete the wiring as shown in figure and when done wiring press ESC key in the
schematic window to cancel wiring.

Now rename the ports, first select the port, then press 'Q', in the NET name change to 'input' then similarly
select output port change to 'output' then click ok.
CHANGING DEVICE PROPERTIES:

In order to change the properties of the devices on the workspace click on the device then press Q, the
corresponding device properties will be shown in the object editor as shown.
Now change Transistor width and length as below.

Type Length Width

PMOS 0.13 u 0.52 u
NMOS 0.13 u 0.25 u

Final schematic should be like this

check for errors by selecting check & save option in the icon bar.

This will result to a window which shows the error report where the errors and warnings in the
schematic can be seen in the Transcript Area.
GENERATING THE SYMBOL:

Now Goto ADD, Generate symbol.

Select Replace existing & activate symbol options. Click Ok.

Symbol gets generated for you.
Change the shape of symbol if required from choose shape.
Then click on OK which leads to the pyxis symbol window.
Save the symbol.
Then symbol will be like this
then again goto file choose check/save.

Close schematic window and come back to Project navigator

TEST BENCH CREATION:
Now to create a Test bench create a schematic , right click on the Library name and select new
schematic or click on the new cell and select the icon in the icon bar.
Now name the schematic/cell name. and click on OK

[Note : Here the schematic name and the cell name given should be different from those given before.]
opens pyxis Schematic
Goto ADD, Instance..choose symbol then select your symbol.
Now goto, library, generic library, add input and output ports then VDD and Ground.
Now add Sources from sources Library i.e. DC and PULSE V source and make the necessary connections
as shown below.

Right click on the Pulse Source and select Edit Properties

Change the values of the below mentioned parameters and apply the changes.
Initial = 0V, Pulse = 5V, Delay = 1nS,Period (If required)
The final symbol is ….

Next click on check & save icon in the icon bar. This will result to a window which shows the error report
where the errors and warnings in the symbol can be seen in the Transcript area.
SIMULATING THE SCHEMATIC:
When you have no errors go to... context mode then select enter simulation mode or click simulation
tap in left side panel.
Click New design Configuration, then give configuration name then click ok… then ok.
Now click Analysis tab in right side panel and disable OP and enable DC

Now click on sweep type, choose source and add Pulse V source which is connected at input side.
Start : 0 Stop :3.3 Step : 0.1

Now enable TRAN in the same window, give start time as 0n and Stop time as 500n (Optional)
Click on Apply.

Now click on Outputs tab.

Minimize setup simulation window and select input and output ports and add in outputs for DC and TRAN
analysis.
Now Click Apply then OK and Run.
Now Go to Results tab, click on view waves, then waveform database (EZ wave window).
In wave form database, expand then double click on DC
Now double click on TRAN tab

Now close the waveform window.

To see the power dissipation, goto results, ascii files then click simulation log, then scroll down for Power
dissipation.
CREATING A LAYOUT:
Goto Proect—Library—choose your schematic

Right click on schematic, new...layout...then click Ok..again Ok (no need to change any names)
Now goto, MGC—setup..view as Default and enable lef tright tilling..then click ok

Now window is like below...,

Now goto Setup...SDL...then
Component type...asim_model
prompt user
SDL port styles...select M1 then click ok.
Now select PMOS, click 'inst' in the right-side panel.

Now place the instance in left panel (layout panel).

Similarly repeat for NMOS also.,

now click on port tab in right panel and place the ports as below, then expand layout window.

Now we need to add devices I.e N-well for PMOS and P-Sub for NMOS.

Goto ADD...select Device, then press Q, in the device name, choose $via_s, then choose N-well and click
ok
Goto View...ALL

Now select the device and move towards PMOS as shown below.
Similarly repeat for NMOS also.
Routing:
Goto Tools, Iroute..then Iroute.

Change routing to POLYG by pressing space button continuously. Make the poly routing
Now connect the input port, for via press space and take via as below.

Output port and gnd port

goto ADD...text on ports.

save your layout.

Physical Verification Using Calibre tool.

Goto Tools, Calibre..Run DRC.

Tools, Calibre..Run LVS..

click comparison results. It should be correct as shown click on schematic and compare layout VS
schematic.