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VHDL Homework

This document contains questions about VHDL concepts including: 1. Identifying regions in a VHDL program such as the library clause, use clause, entity declaration, etc. 2. Understanding component instantiation and how it allows different implementations of the same interface. 3. Recognizing that libraries contain compiled design units and packages contain reusable declarations.

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Raja Ram
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88 views4 pages

VHDL Homework

This document contains questions about VHDL concepts including: 1. Identifying regions in a VHDL program such as the library clause, use clause, entity declaration, etc. 2. Understanding component instantiation and how it allows different implementations of the same interface. 3. Recognizing that libraries contain compiled design units and packages contain reusable declarations.

Uploaded by

Raja Ram
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Homework 1 :

CheckYourUnderstanding lec 1 2 3 ee721 2019


SBP
7th August 2019

1
1 Learn to identify following regions in a VHDL program : Library clause,
use clause, entity declaration, port declaration of entity, architecture, dec-
laration region of architecture , body of architecture , package declaration
, package body.
2 In which of the above regions would you find a statement like the following
?

uut : nand_gate port map ( a => sig_a , b => sig_b , c => sig_c );

3 Where would you find the declarations of sig a, sig b, sig c ? ( assuming
that they are signals that are not ports )
4 What is ”nand gate” in the above ? Assume that it happens to be name
of an entity. However in the above statement it is regarded as a name of
something else ? What is it ?
5 Component is like a specification of socket-compatible chip. An instance of
component xyz means an instance of any entity whose ports are compatible
with those of component xyz.
6 For instance, consider the following component declaration.

component fourbitadder port (


a,b : in std_logic_vector( 3 downto 0 );
cin : in std_logic ;
sum : out std_logic_vector( 3 downto 0 ) ;
cout : out std_logic );
end component ;

7 Further suppose there is an entity ripplecarry4bitadder in library abclib


and another entity carrylookahead4bitadder in library pqrlib.
Then we can have following usage of ”component instantiations”.

1
adder4_first : fourbitadder port map ( ..... ) ;
adder4_another : fourbitadder port map ( ..... ) ;

Somewhere else it would be specified ( in appropriate vhdl syntax ) that


the
– instance adder4 first of component fourbitadder is to be created from
entity ripplecarry4bitadder from abclib library, and
– instance adder4 another of component fourbitadder is to be created
from entity carrylookahead4bitadder from pqrlib library,
8 Note that both these instances adder4 first and adder4 another of compo-
nent fourbitadder are socket-compatible, even though they could be con-
structed from possibly different entities ( from possibly different libraries
).
9 Such 2 different instances of the same component , could also be created
using different architectures of the same entity. This is illustrated below.

entity nand_gate is
port ( a,b : in bit ; c : out bit ) ;
end nand_gate ;

architecture a1 of nand_gate is
begin
c <= a nand b ;
end a1;

architecture a2 of nand_gate is
begin
process ( a,b )
begin
if ( a=’0’ and b=’0’ ) then c <= ’1’ ;
elsif ( a=’0’ and b=’1’ ) then c <= ’1’ ;
elsif ( a=’1’ and b=’0’ ) then c <= ’1’ ;
else c <= ’0’ ;
end if ;
end process ;
end a2;

library ieee; use ieee.numeric_bit.all;

entity nand_gate_test is end nand_gate_test ;

architecture a1_test of nand_gate_test is


component comp_nand_gate port ( a,b:in bit ; c : out bit );

2
end component;
for inst0 : comp_nand_gate use entity work.nand_gate( a1 ) ;
for inst1 : comp_nand_gate use entity work.nand_gate( a2 ) ;
signal sig_a , sig_b , sig_c0 , sig_c1 : bit ;
begin
inst0 : comp_nand_gate port map
( a=>sig_a , b=>sig_b, c=>sig_c0 );
inst1 : comp_nand_gate port map
( a=>sig_a , b=>sig_b, c=>sig_c1 );
stim_process : process
begin
for i in 0 to 3 loop
( sig_a, sig_b ) <= bit_vector ( to_unsigned( i , 2 ) );
wait for 10 ns ;
end loop;
( sig_a, sig_b ) <= bit_vector ( to_unsigned( 0 , 2 ) );
wait for 10 ns ;
wait ;
end process ;
end a1_test;

10 Explain the following ghdl commands and their results.

prompt> ghdl -a --workdir=work nand_gate_with_test.vhd


prompt> ghdl -e --workdir=work nand_gate_test
prompt> ghdl -r --workdir=work nand_gate_test
--stop-time=200ns --vcd=wave.vcd
prompt> gtkwave wave.vcd

3
11 A design unit ( i.e. entity / architecture / package / package body /
configuration ) is so called because vhdl compiler/analyzer can compiler
it separately ( these could be in separate files ).
12 What (in your opinion ) is the natural rationale behind regarding entity,
package as primary design unit , and on the other hand, architecture and
package body as secondary design unit ?
By the way, something important called ”configuration” too is a primary
design unit ( I have not brought it up yet ).
13 What does a (vhdl) library contain ? Ans : compiled versions of design
units , i.e. package/package-body, entity/ architectures, configuration (
not introduced so far ). etc.
14 What does a package contain ?
15 Give one example, how a package makes life less tedious for vhdl program-
mer ?
16 In which package of which library , basic declarations of fundamental types
such as bit , bit vector , boolean , integer , character , string etc. are kept
?
17 Why haven’t we noticed any use clause associated with this a package ?
18 Given the following component declaration

component FULLADDER
port ( a, b, c: in std_logic;
sum, carry: out std_logic);
end component;

what does the following ”component instantiation” statement means ?

FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));

19 Show the more preferred ( alternate ) manner of ”component instantiation


” equivalent to the above ( i.e. the one that explicitely specifies association
between the port names and the names of connected signals ).

FA0: FULLADDER
port map ( a => a(0), ?????? );

20 What did the package my pkg1 , shown in lecture 3, contain ? Where is


the actual definition of a function declared inside a package kept ?
21 VHDL synthesis tool would replace every invocation of a ( pure ) function
with a combinational logic block whose inputs are ?????????? and whose
output is ??????????

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