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Steps To Implement The Half Adder in The FPGA Using Xilinx ISE

This document outlines the steps to implement a half adder in an FPGA using Xilinx ISE: 1. Create a new project in Xilinx ISE and generate a VHDL file with input and output ports. 2. Write VHDL code for the half adder behavior and check for syntax errors. 3. Create a test bench file to simulate and verify the design's operation. 4. Synthesize, implement, and generate a programming file for the targeted FPGA. The half adder can then be tested on the FPGA by applying inputs and observing the outputs.

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252 views

Steps To Implement The Half Adder in The FPGA Using Xilinx ISE

This document outlines the steps to implement a half adder in an FPGA using Xilinx ISE: 1. Create a new project in Xilinx ISE and generate a VHDL file with input and output ports. 2. Write VHDL code for the half adder behavior and check for syntax errors. 3. Create a test bench file to simulate and verify the design's operation. 4. Synthesize, implement, and generate a programming file for the targeted FPGA. The half adder can then be tested on the FPGA by applying inputs and observing the outputs.

Uploaded by

Anonymous naEAR9ad
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© © All Rights Reserved
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Steps to implement the Half adder in the FPGA using Xilinx ISE

Step 1 Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start-
Programs- Xilinx ISE

Step 2 Create a new project In the window go to FILE -New project.

Specify the project name and location and say NEXT

Select Device. Use the pull-down arrow to select the Value for each Property Name.
Click in the field to access the pull-down list.

Say FINISH. Project summary is seen.

Step 3: Creating a new VHD file Click on the symbol of FPGA device and then right click􀃆 Click on
new source-VHDL module and give the File name
Then say Next􀃆Define ports.In this case • a and b are the input ports defined as in

• sum and carry are output ports defined as out after this say Next twice and then Finish

Skeleton of the design is shown in the VHDL editor.


Step 4: Writing the Behavioural VHDL Code in VHDL Editor

Sample code is given below for this experiment.

Step 5 Check Syntax Run the Check syntax 􀃆 Process window􀃆 synthesize􀃆check syntax >, and
remove errors if present.

Step 6 Creating a test bench file

Verify the operation of your design before you implement it as hardware. Simulation

can be done using ISE simulator. For this click on the symbol of FPGA device and

then right click􀃆 Click on new source 􀃆Test Bench Waveform and give the name 􀃆

Select entity􀃆Finish.
Select the desired parameters for simulating your design. In this case combinational

circuit and Simulation time.

Step 7: Simulate the code

Simulation Tools
ISE tool supports the following simulation tools:

• HDL Bencher is an automated test bench creation tool. It is fully integrated with

Project Navigator.

• ModelSim from Model Technology, Inc., is integrated in Project Navigator to

simulate the design at all steps (Functional and Timing). ModelSim XE, the Xilinx

Edition of Model Technology, Inc.’s ModelSim application, can be installed from the

MTI CD included in your ISE Tool

In source Window from the Drop-down menu select Behavioural Simulation to view the

created test Bench file.

Click on test bench file. Test bench file will open in main window. Assign all the signals

and save File. From the source of process window. Click on Simulate Behavioral

Model in Process window.


Verify your design in wave window by seeing behaviour of output signal with respect to

input signal. Close the ISE simulator window


Step 8: Synthesize the design using XST.

Translate your design into gates and optimize it for the target architecture. This is the

synthesis phase.

Again for synthesizing your design, from the source window select,

synthesis/Implementation from the drop-down menu.

Highlight file in the Sources in Project window. To run synthesis, right-click on Synthesize, and the
Run option, or double-click on Synthesize in the Processes for

Current Source window. Synthesis will run, and

• a green check 􀃆will appear next to Synthesize when it is successfully

completed.

• a red cross 􀃆indicates an error was generated and

• a yellow exclamation ! mark indicates that a warning was generated, (warnings


are OK).

Check the synthesis report.

If there are any errors correct it and rerun synthesis..

Step 9: Create Constraints File(UCF)

Click on the symbol of FPGA device and then right click􀃆 Click on new source

􀃆Implementation Constraints File and give the name 􀃆 Select entity􀃆Finish.

Click on User Constraint and in that Double Click on Assign Package Pins option in

Process window. Xilinx PACE window opens. Enter all the pin assignments in PACE.,

depending upon target device and number of input and outputs used in your design.

(sample code is given below for given design.)


Step 10: Implementing a Design

Once synthesis is complete, you can place and route your design to fit into a Xilinx

device, and you can also get some post place-and-route timing information about the

design. The implementation stage consists of taking the synthesized netlist through

translation, mapping, and place and route.

To check your design as it is implemented, reports are available for each stage in the

implementation process. Use the Xilinx Constraints Editor to add timing and location

constraints for the implementation of your design. This procedure runs you through the

basic flow for implementation.

Right-click on Implement Design, and choose the Run option, or double left-click on

Implement Design.
Step 11: Generating Programming File

Right-click on Generate Programming File, choose the Run option, or double left-click

on Generate Programming File. This will generate the Bit stream

Step 12 Downloading in Boundary Scan Mode.

Note : Xilinx provides 2-tools for downloading purpose, viz.

• iMPACT - is a command line and GUI based tool

PROM File Formatter


Procedure for downloading using iMPACT

• Boundary Scan Mode

1. Right click on “Configure Device (iMPACT)” -> and Say RUN or Double click

on “Configure Device (iMPACT)”.

2. Right click in workspace and say Initialize chain .The device is seen.

3. Right click on the device and say Program.


If the device is programmed properly, it says Programming Succeeded or else.

Programming Failed. The DONE Led glows green if programming succeeds.

Note:

Before downloading make sure that Protoboard is connected to PC's parallel port with

the cable provided and power to the Protoboard is ON.

Step 13: Apply input through DIP Switches, output is displayed on LEDs

Step 14: Configuration through PROM: Generating PROM file:

FPGA can also be configured in Master Serial Mode through PROM. For this you need

to program the PROM through a .mcs file.

Right click on “Generate PROM,ACE or JTAG file” -> and Say RUN or Double click on

“Generate PROM,ACE or JTAG file”


Specify the PROM file name and location where it is to be generated.

Specify the desired parameters of the PROM on board and say ADD then FINISH
Say Generate File from the Process Window.

PROGRAMMING THE PROM

Note: Check the Jumper setting on the board. Refer the Chapter jumper Setting

Similar to Step 12.Initialize chain through iMPACT. PROM and FPGA devices on

board are seen .Assign the generated mcs file and bit file as desired.
Right click the PROM symbol and say PROGRAM.

Now, whenever the board is powered on in master serial mode, FPGA is configured

through PROM automatically.


Conclusion:

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