IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014),May 09-11,2014,Jaipur,India

Design of Low Power Current Starved VCO with

Improved Frequency Stability
R.RJagtap S.D.Pable
Department of Electronics and Telecommunication Department of Electronics and Telecommunication
Engineering, Matoshri College of Engineering & Research Engineering, Matoshri College of Engineering & Research
centre, Eklahare-Nashik, University of Pune, India centre, Eklahare-Nashik, University of Pune, India

Abstract- Voltage Controlled Oscillator (VCO) plays a vital role [7]. As technology scaling is moving towards the nanometre
in deciding the performance of VLSI circuits. Lot of research work scale various efforts put towards designing and optimizing the
is carried out on VCO from the past decades to achieve higher performance of analog and mixed signal circuits. Optimization
frequency, low power, low operating voltage, lower phase noise, and
of VCO consists of a number of design specifications, as well
to increase tuning range. This paper mainly explores design of
as power optimization, particularly for portable applications.
current starved voltage controlled ring oscillator for ultra low power
applications. The performance comparison is done with respect to
With the introduction of nanometre CMOS processes, geared
frequency stability and power consumption characteristics at 32nm towards low-power portable designs, there is a need to
technology node. Proposed C.S.D. T connection of VCO shows 48% investigate alternate design strategies to have better VCO
higher speed at the cost of 18.9% increased power consumption over performance.
conventional VCO at Vvv=O.4v. Furthermore, this paper explores [t is necessary to investigate the performance comparison
effect of temperature variations on VCO performance. Proposed using power dissipation and frequency stability design metrics.
VCO shows less sensitivity to temperature variation over However, low power is a key requirement for battery operated
conventional VCO.
devices. This paper mainly explores the techniques to have
ULP with enhanced speed for moderate throughput using
Keywords - Current starved; DTMOS; C.S.DT VCO.
DTMOS techniques. Rest of the paper is organized as follows.
Section II describes the current starved VCO and previous
I. INTRODUCTION
work done. Section III describes the DTMOS technique.
Section IV investigates the performance of current starved
[n recent years, most of the research work is targeted VCO for different DT connections. Section V explores effect
towards minimizing the energy consumption at device and/or of temperature variations on VCO performance. Section V[
system [evel to increase the battery life span for embedded finally draws the conclusion.
applications [1-4] Ultra-low power (ULP) demand is mainly
driven by applications like wireless sensors; body based II. CURRENT STARVED VCO
sensors, and implanted medical electronics. To achieve
enhanced power efficient designs, numerous power reduction The VCO is commonly used for clock generation in phase
techniques have been proposed in previous research including lock loop circuits. The clock may vary typically by +/-50% of
optimization of device parameters, architecture level its central frequency. Therefore, VCO plays a critical role in
optimization and supply voltage (V DD ) scaling among all communication systems, providing periodic signals required
techniques, the most successful one is V DD scaling to even for timing in digital circuits and frequency translation in radio
below the threshold voltage (V Ih ) of the device [1-2]. frequency circuits. Their output frequency is a function of a
Subthreshold circuits are operated at V DD lower than V th to control input voltage. An ideal voltage-controlled oscillator is
satisfy the ULP demand of portable devices having a circuit whose output frequency is a linear function of its
performance as a secondary requirement. Subthreshold control voltage. Most application required tunable oscillator,
operation of digital circuit has become a popular design i.e. their output frequency be a function of a control input,
approach to achieve ULP [3-4]. Thus, in future for CMOS usually a voltage. Lot of research work has been carried out on
technologies, it is expected that subthreshold operation will designing high performance VCO [8-11]. However, with rapid
take over super-threshold for ULP moderate frequency range emerge of portable applications, there is need to reduce the
applications. power consumption significantly. Different VCO topologies
A VCO is an important building block in phase locked have been explored by the researchers based on power
loops (PLL) which decides the power consumed by the PLL consumption and maximum operating frequencies.
and area occupied by the PLL [5-6]. VCO also represent a VCOs are implemented using ring oscillator. The ring
critical component in many RF transceivers and are commonly oscillator works by controlling the charging and discharging of
associated with signal processing tasks like frequency selection the gate capacitance of the next inverter. Decreasing the peak
and signal generation [7]. Transceivers for wireless available charging current increases the time to charge and
communication system contain low-noise amplifiers, mixers, discharge the gate capacitance; consequently, the frequency is
digital signal-processing chips, filters, and phase-locked loops

[978-1-4799-4040-0114/$31.00 ©2014 IEEE]

 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014),May 09-11,2014,Jaipur,India

decreased. Ring oscillators generate high frequency up to few

GHz. ([)
Authors [5] compared the performance of a current
starved VCO and source coupled VCO with the design Where, Vbs is the source-bulk voltage, V thO the threshold
experiment and with the qualitative evaluation. Measurement voltage for Vbs= 0, Ie is body effect factor and \Iff is Fermi
results showed that in chip area, power consumption, and potential [12-13].
tunable frequency range, a RC based current starved VCO is Digital sub-threshold logic circuits have recently been
superior to a source coupled VCO. Also, the relative proposed for applications in the ultra-low power end of the
performance difference between ring VCO and LC VCO will design spectrum, where the performance is of secondary
be almost constant in the future. Power consumption and chip importance. To improve switching performance of the sub­
area of both PLLs will decrease as technology scale down. threshold logic family with comparable energy/switching use
The schematic of current-starved VCO is as shown in of sub-DTMOS (sub-threshold Dynamic Threshold MaS)
Fig.l. Its operation is similar to the ring oscillator. M2 and M3 transistors is essential. The stability of sub-threshold DTMOS
operate as an inverter, while MI and M4 operate as current logic to temperature and process variations eliminates the need
sources. The current sources, Ml and M4, limit the current of additional stabilization scheme that may be required for
available to the transistor M2 and M3. [n other words, the regular sub-threshold MaS logic families to ensure proper
inverter is starved for current. The drain currents of M5 and operation in the sub-threshold region.
M6 are the same and are set by the input control voltage. The
currents in M5 and M6 are mirrored in each inverter/current [V. PERFORMANCE ANALYSIS OF CURRENT STARVED VCO
source stage. Consequent by the change in V control induces a CONFIGURATlONS
global change in the inverter currents.
This section explores performance optimization of current
VDD VDD VDD VDD starved VCO using DTMOS. Furthermore, it focuses on design
parameters and circuit description for low power consumption
and better frequency stability. Frequency response of the
current starved VCO is as shown in Fig.3. Five inverters have
been designed to create the basic ring oscillator. The buffer
inverter is situated on the right side of the layout, through

... � which output is taken. V DD is chosen as OAV so as to operate

VCO in weak inversion regime to achieve low power. The Fig.
4 shows physical layout for VCO.
The oscillation frequency of current starved VCO for 'N' [[2-
[3],
fose = 1/ N ( t1 + t2 ) (2)
fose = [ / (N * C total * V DD )
Fig. I. Five Stage Current-Starved VCO (3)

�- - -,
III. DTMOS Where, t1 and t2 are time taken to charge C total from zero and
V DD to V sp respectively.

WlI •••
, ...
.. •••• •• •••• " '
,,, •••• •• •••• ••••• "1
--,--
,, 1 .. Ill. ... ... ... .
. - - - -- - - - - -
... ... .. . .. ... ... - ... ... t

�:�. - �: �:�- � - �-�-f

lIlo _ _- - - - - - - - - - . . .

"'"
�------- --; au. ...... . ... . . . . . . .. . . . .. .. .. ..

- -

-
:, t

-
_ _ -
1&11 •••••• • •• • • • • • • • • • • •• •• •• •• •• _ .. .. .. . . .. . . .. .. .. . . . . . . . · ·· ·· ·· ·· ··

Fig. 2. DIMOS Implementation of NMOS ,00. f· , "':

9:10 --- i - -- - - - -- - t- - .. . ·· · ··· · l: ·· · ·· . .. . .. . .. .l.-
: : 1
An effective method for reducing power consumption is : r j
reduction the V DD. A constraint to implementing digital and
analog circuits at low-voltage is the threshold voltage. Fig. 3. Output performance of the current starved for a five inverter chain
DTMOS technique is the best idea for reduction threshold using,32nm VLSI technology.
voltage in dynamic mode of MOSFET. [n DTMOS technique,
the bulk is tied to gate as shown in Fig.2.
The DTMOS technique reduces the transistor off-state
leakage current and also reduces the threshold voltage during
on-state (Vbs > 0) according to equation (1) as shown below,
 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014),May 09-11,2014,Jaipur,India

300 r-----�----�--�

_Conv.VCO
250 _ ROOTVCO
_CSOTVCO
200 c=JOTVCO
�
"
--;:: 150
OJ
�
o
0.. 100

50

o
0. 4 V 0. 2 V
Diflerent VCO Configurations

Fig. 4. Layout of Current Starved VCO Fig. 6. Different VCO configurations with respect to power at Vc=O.4 V and
Vc=0.2V

Fig.5 shows performance comparison of VCO for 500

different possibility configuration of DT connections. As
shown in Fig.5 and Fig.6 Current source transistors connected
400
as DTMOS (C.S. DTMOS). This configuration shows 48%
higher speed with 18.9% increase in power consumption over N
.<::
Conventional VCO (Conv.VCO) at V DD=O.4V. In CS DTMOS 2: 300
>:
t)
only current source MOSFETs are DTMOS connected and c
(])
remaining transistors are conventional. It is also observed from ::::J
rr 200
Fig.5 and Fig.6 that CS DTMOS technique improves �
LL
frequency by 51% at the cost of 26% increased power ---e--- CS DT VCO
10
dissipation at Vc=O.2V. Frequency response of C.S. DTMOS --+- Cony. VCO
VCO is better than that of conv. VCO, R.O DTMOS, and all
0
transistors connected in DT MOS configuration (DT-MOS 0.1 0.2 0.3 0.4 0.5
VCOs). Control Voltage (Ve) in V
Hence, from Fig. 5 and Fig. 6 it is investigated that C.S.
DTMOS configuration shows is much better frequency Fig. 7. Frequency as a fimction of Control Voltage at V DD=O.4V
response than the other configurations. Proposed C.S. DTMOS
enhance the frequency response with moderate increase in Fig. 7 and Fig. 8 investigate the performance difference of CS
power consumption as compared to conv.VCO. Increase in DT VCO and Cony. VCO. It is clear that CS DT VCO shows
power consumption is in nW range so can be ignored for ULP better frequency response at almost same power consumption.
and moderate through put applications.
1200
350 ,-----�----�--__,
1000 --e-- CS DT VCO
300 _RO DT VCO
c=::J DT VCO -+- COllY. VCO
�. 250 _Conv.VCO �
800
N
_CS DT VCO �
�
� 200
'"
'-'
... 600
II)
g �
� 150 0
CT � 400
�
U..; 100
200
50

o
0.4 V 0.2V 0.1 0.2 0.3 0.4 0.5
Diflerential VCO Configuration Control Voltage (V)
Fig. 5. Different VCO configurations with respect to frequency at Vc=O.4 V
Fig. 8. Power as a function of Control Voltage at V DD=O.4V
and Vc=O.2V
 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014),May 09-11,2014,Jaipur,India

100 r---�----�--�
v. EFFECT OF TEMPERATURE VARIATION ON VCO
--+- ConvVCO
PERFORMANCE
---e--- CS DT VCO
80
2
N
10 I
6
1 Subthreshold i')' 60
10 c
Q)
:::J
0-
0
�
;:;: 10 LL
�
1J -I
10
�
.� 2��--�------�----�----�-----"
r5 10
-2
20 40 60 80 100 120
Temperature C c)
-3
10

Fig. II. Eflect of temperature on frequency of current starved VCO at V DD

-4
10 =OAV and Vc=O.2V
0 400 600
Supply voltage (mV)

30 .---�----�---.
Fig. 9. I-V chracteristics of Si- MOSFET at different temperature [15] .
--+- Conv . VCO
25
This section explores the effect of temperature variation on --e- CS DT YCO
subthreshold VCO circuit performance. Unlike super­
threshold, where due to the high gate-overdrive, the mobility � 20

dominates and hence, transistors drain current (ION) decreases

with increase in temperature, the subthreshold current (lsub)
increases exponentially with temperature as shown in Fig. 9
[14-15]. Therefore, it is necessary to investigate the effect of
temperature variation at different biasing conditions under
subthreshold region.
5 L---�----�--�
Fig. 10 and Fig. 11 shows, the effect of temperature 20 40 60 80 100 120
variation on the frequency and power dissipation at different Temperature (0 C)
Vc. [t is clear from Fig.IO that, by using DTMOS
configuration up to 800C frequency response is stable as
Fig. 12. Eflect of temperature on power of current starved VCO at V DD
compared to Conv.VCO. However, Fig. 11 shows that at
=OAV and Vc=O.2V
smaller value of control voltage frequency response of VCO is
changes significantly. Fig. 12 shows, effect of temperature
VI. CONCLUSION
vanatIOn on power consumption for different biasing
conditions. DT MaS configuration shows penalty in power
consumption. Exponential growth of portable applications attracts the
researchers towards subthreshold operating region. This paper
340 investigated the performance of Current starved VCO.
..,.. Different configurations of DT Connections have been
32
N' 300 � ConvVCO investigated. It is proposed that CS DT VCO gives better
� ---e--- cs DTVCO frequency response over the conv.VCO and other
6280
r;-' configurations. Effect of temperature vanatIOns on
§j 260 performance of VCO is also explored for different biasing
�
i':!
'-'-< 240 conditions.
220
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200
20 40 60 80 100 120
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 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014),May 09-11,2014,Jaipur,India

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