EE577b: VLSI System Design Verilog Examples

EE577b: VLSI System Design
Verilog Examples
Professor Peter A. Beerel
Borrowed from Gandhi Puvvada EE560 notes (previously EE599)

Power point presentation transcribed by Sunan Tugsinavisut
Examples of Combinational Circuits
Include all input signals to sensitivity list

(Example I).
Avoid inferred latch in combinational circuits

y Missing “else statement” (example II).
y Missing “variable assignment” (example III).
y Missing “conditions” (example III and IV).
January, 00 P. A. Beerel 2
1
Solutions to avoid inferred latch
Assign default value at the beginning (example IV).
Assign outputs for all input conditions (example III).
Use “else” (instead of “else if”) for the final priority

branch (example II).
Combinational Circuit Example I
z Include all input signals to sensitivity list.
// Poor coding for AND gate.

always @(a) // missing “b” signal
begin
if ((a == 1’b1) and (b == 1’b1))
// if “a” and “b” is 1
c = 1’b1; // set “c” to 1
else
c = 1’b0; // o.w., set “c” to 0
end
2
Combinational Circuit Example I
z Recommended coding for AND gate.
always @(a or b) // include both “a” and “b”

begin // in sensitivity list.
if ((a == 1’b1) and (b == 1’b1)) // if “a” and “b” is 1
c = 1’b1; // set “c” to 1
else
c = 1’b0; // otherwise, set “c” to 0
end
Combinational Circuit Example II
z Poor coding style: missing “else statement”.

always @(a or b)
begin
if (a == 1’b1)
q = b;
// missing “else statement” infers latch.
end
end
3
Combinational Circuit Example II
z Recommended coding style.
always @(a or b)
begin
if (a == 1’b1)
q = b;
else // include “else statement”
q = 1’b0;
end
Combinational Circuit Example III
z Missing assignments and condition .
always @(d)
begin
case (d)
2’b00: z = 1’b1; // missing “s” assignment
2’b01: z = 1’b0; // missing “s” assignment
2’b10: z = 1’b1; s = 1’b1;
// missing condition “2’b11”.
endcase
end
4
Combinational Circuit Example III
z Recommended coding style.

always @(d)
begin
case (d)
2’b00: z = 1’b1; s = 1’b0;
2’b01: z = 1’b0; s = 1’b0;
2’b10: z = 1’b1; s = 1’b1;
default: z = 1’b0; s = 1’b1;
endcase
end
Combinational Circuit Example IV
z Poor coding style: missing condition
always @(g, a, b)
begin
if (g == 1’b1)
q = 0;
else if (a == 1’b1)
q = b;
// missing case “g = 0” and “a = 0”.
end
5
Combinational Circuit Example IV
z Recommended coding style
always @(g, a, b)
q = 0; // default assignment to avoid
begin // missing condition.
if (g == 1’b1)
q = 0;
else if (a == 1’b1)
q = b;
end
Sequential process assignment
z Use non-blocking assign. in always @(posedge clk)

block
// Poor coding style
always @(posedge clk)
b = a; // assignment of values depends on which
always @(posedge clk) // always block scheduler chooses
a = b; // first
// Recommended coding style

always @(posedge clk) begin
b <= a; // both signals are assigned at the clk edge
a <= b;
end
6
Sequential circuit with sync reset
z Process with synchronous reset.

begin
if (rst == 1’b1) // synchronous when “rst” is 1
begin
… // reset condition
end
else
begin
...
end
end
Sequential circuit w/ async reset
z Process with asynchronous reset

always @(posedge clk or posedge rst)
begin
if (rst == 1’b1) // async. reset when “rst” is 1
begin
… // reset condition
end
else
begin
…
end
end
7
Example of D-FF w/ asynch reset
module ASYNC_FF (d, clk, rst, q);

input d;
input clk;
input rst;
output q;
req q;
always @posedge clk or negedge RST)

if (!RST) // reset when “RST” is 0
q <= 0; // set “q” to 0
else // at the positive clk edge
q <= d; // set “q” to input “d”
FSM Coding Styles
I. Separate state memory (SM), next state logic

(NSL), and output function logic (OFL)
(Preferred for EE577b)
y Combinational logic delay can be easily incorporated
y Critical path analysis is easier to understand and analyze
II. Combine state memory (SM) with next state

logic (NSL)
y Fewer processes
8
FSM with async reset (Style I)
parameter IDLE = 2’b00;
RW_CYCLE = 2’b01;
INT_CYCLE = 2’b10;
DMA_CYCLE = 2’b11;
ADD1MUL1 = 3’b001;
ADD2MUL1 = 3’b011;
...
reg [1:0] STATE, NEXT_STATE;
// State memory module

always (posedge CLK or negedge RESET)
if (!RESET) // asynchronous reset
STATE <= IDLE;
else // state assignment at clk edge
STATE <= NEXT_STATE;
// Next state logic (NSL) module (combinational)

always (STATE or RW or INT_REQ or DMA_REQ) begin
NEXT_STATE = STATE; // default assignment
case (STATE)
IDLE:
if (INT_REQ)
NEXT_STATE = INT_CYCLE; // next state assign.
else if
...
RW_CYCLE:
...
endcase
end
9
// Output function logic (OFL) module (combinational)

always (STATE or RW or INT_REQ or DMA_REQ) begin
mux_sels = ADD1MUL1; // default assignment
op_codes = OP1;
case (STATE)
IDLE:
if (INT_REQ)
mux_sels = ADD2MUL1; // assignment to mux selects
op_codes = OP1;
else if
...
RW_CYCLE:
...
endcase
end
FSM with Async Reset (Style II)

reg [1:0] STATE; // do not need NEXT_STATE var
always (posedge CLK or negedge RESET)
if (!RESET) // asynchronous reset
STATE <= IDLE;
else begin
case (STATE) // combined state memory and
IDLE: // next state logic
if (INT_REQ)
STATE <= INT_CYCLE;
else if
...
RW_CYCLE: // statements
...
endcase
end
10
Synchronous RTL Coding Styles
General Requirements
y Register transfers on only clock edges.
y Combinational logic computes values to be depositid
before clock edge.
Full-Custom Design: 2-Step Coding Process

y First Step: Behavioral RTL
x Data flow and control steps specified
y Second Step: Structural RTL
x Structure of datapath and interface to control defined
Behavioral RTL coding
General Description
y One or more clocked process(es) to describe the
control unit (CU) and datapath (DPU)
x No distinct combinational logic blocks
Two Forms
y Separate CU and DPU (Recommended!)
x Helps ensure correctness and synthesizability
y Combined CU and DPU
x Not recommended!
x Disadvantage: data registers do not need to be reset but
they are coded under a process sensitive to reset (needed
because control registers must be reset).
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Benefits of Behavioral RTL
Easy
y Do not have to visualize or explicitly specify...
x datapath component boundaries
x functional unit allocation and binding
x control signals such as mux_sel or op_codes
Helpful
y For ASIC Design: synthesis tools (e.g., design compiler)
can do function unit allocation and bining, mux and
op_code synthesis
y For full-custom design: helps guide and validate structural
RTL code
Separate CU and DPU Example

// Separate control unit processes.
always @(posedge clk or negedge rst_b) begin
if (rst_b == 1’b0)
state <= I_STATE;
else begin
case (state)
I_STATE:
if (start == 1’b1)
state <= C_STATE;
…
endcase
end
end
12
Separate CU and DPU Ex. (con’t)
// Separate DPU process.
// The OFL is implicitly treated as part of the DPU
// Muxes are not needed; they are implicit
// Registers are not needed; they are implicit
always@(posedge clk)
begin
case (state)
I_STATE:
x <= xin;
y <= yin;
C_STATE:
if (x >= y)
x <= x - y;
…
endcase
end
Combined CU and DPU Example

// Combined CU and DPU process
always @(posedge clk or negedge rst_b)
begin
if (rst_b == 1’b0)
state <= I_STATE;
else begin
case (state)
I_STATE: …
C_STATE:
if (x >= y)
x <= x - y; // DPU section
else
state <= D_STATE; // CU section
…
endcase
end
end
13
Structural RTL Coding
Create structural description of datapath unit
y Must visualize and specify functional units, muxes, mux_sel,
op_code_sel, registers etc…
y Must specify interface between control and datapath units
Advantages of structural RTL coding

y Not limited to tools: can model advanced logic and clocking styles
x Dynamic, self-resetting logic functional blocks
x Two-phase clocking, pulse-mode clocking, asynchronous
y Most errors in full-custom design are at block interfaces
x Structural RTL coding makes these interfaces expicit which facilitates
their validation
x Facilitates concurrent component design
Structural RTL Coding

Create structural description of datapath unit
y Must visualize and specify functional units, muxes, mux_sel,
op_code_sel, registers etc…
y Must specify interface between control and datapath units
Advantages of structural RTL coding

y Can model advanced logic and clocking styles
x Dynamic, self-resetting logic functional blocks
x Two-phase clocking, pulse-mode clocking, asynchronous
y Most errors in full-custom design are at block interfaces
x Structural RTL coding makes these interfaces expicit which facilitates
their validation
y Thus, Structural RTL Coding is preferred for EE577b!
14
Structural RTL Example
z Example of circuit
z Top level circuit verilog example
z Datapath unit example
z Datapath unit components example
y 8-bit wide, 2 to 1 Multiplexor
y 8-bit positive edge flip-flop
y 8-bit ALU
zControl unit example
y Next state logic
y State memory
y Output functional logic
Example of circuit
Mux_1
...
Reg _1
Datapath Unit
...
ALU
Mux_2
Reg _2
alu_out
...
clk
start Mux_sel1 Mux_sel2 opcode en1 en2

Control Unit (FSM)
done
15
Top level circuit verilog example
‘include “cu.v” // file “cu.v” implements control logic unit

‘include “dpu.v” // file “dpu.v” implements datapath unit
module top; // top level module

wire start;
wire done
wire clk;
… // declare interface wires b/w modules or external signals
(module name) (instant name)

cu u1(interface parameters); // interface signals b/w modules
dpu u2(interface parameters); // in this case “cu” and “dpu”
endmodule
Datapath unit example (dpu.v)
‘include “mux.v”
‘include “alu.v”
‘include “reg.v”
module dpu(interface signals both inputs and outputs);

// define interface wires b/w modules and external signals
// In the design, we have 5 components as followings,

(module name) (instant name)
mux_2_1 mux1(interface parameters);
mux_2_1 mux2(interface parameters);
pos_ff reg1(interface parameters);
pos_ff reg2(interface parameters);
alu alu(interface parameters);
endmodule
16
8-bit wide, 2 to 1 Multiplexor (mux.v)
module mux_2_1(sel, in0, in1, out)

input sel
input [7:0] in0, in1;
output [7:0] out;
reg [7:0] out;
always @(sel, in1, in2) begin

case(sel)
0: out = in0;
1: out = in1;
endcase
end
endmodule
8-bit positive edge flip-flop (reg.v)
module pos_ff(clk, in, en, out)

input clk, en;
input [7:0] in;
output [7:0] out;
reg [7:0] out;
always @(posedge clk) begin

if (en == 1’b1)
in = out;
end
endmodule
17
8-bit ALU (alu.v)
module alu(in0, in1, opcode, out)

input [7:0] in0, in1;
input [1:0] opcode;
output [7:0] out;
reg [7:0] out;
always @(in0 or in1 or opcode) begin

case (opcode)
0: out = in0 ^ in1;
1: out = in0 + in1;
2: out = in0 >> 1;
3: out = in1 << 1;
default: out = 8’b0;
endcase
end
endmodule
Creating clock and reset signal
reg CLK;
parameter PERIOD = 50; // clock period
initial CLK = 0; // initialize clock signal
// clock generator
always #(PERIOD/2) CLK = !CLK;
// reset generator
always begin
RESET = 1;
# (3 * PERIOD) RESET = 0;
end
18
Creating clock and reset signal (con’t)
parameter INITIAL_CLOCK= 1;
parameter MAX_CYCLES = 100;
parameter SIM_END = PERIOD * MAX_CYCLES;
always begin
while ($time < SIM_END) begin
CLK = INITIAL_CLOCK;
#(PERIOD/2);
CLK = !INITIAL_CLOCK;
#(PERIOD/2);
end
$finish
end
Simple delay model
Delay model for FF

q <= #10 d // intra-delay assignment
y At the clk edge “d” is sampled and q gets samled
value after 10 time units.
“assign delay model”
assign #10 c <= a ^ b; (wrong)
assign c <= #10 a ^ b; (illegal)
assign #10 c = a ^ b; (correct)
y “c” is evaluated to a xor b, but it is assigned in next
10 time units.
19
Simple delay model (con’t)
Other examples
wire #6.5 z = a & b;
or #10 u3(C, A, B);
Modeling rise and fall times
assign #(rise, fall) c = a ^ b;
or #(10, 25) u3(C, A, B);
buf #(10, 25, 35) zbuf(z, a, en);
Third delay parameter is the delay to high
impedance state.
System functions
z $random and $time

‘timescale 10ns/ 1ns // (time unit reference/precision)
model dollartime();
reg [15:0] value1;
reg [7:0] value2;
parameter delay1 = 2.67; // delay1 = 2.67 x 10ns
initial begin
value1 = $random;
value2 = $random;
#delay1 $display(“%0d %b”, $time, value1);
end
endmodule
20
System functions (con’t)
z $finish, $stop and $save

initial begin
wait (buffer_empty);
$finish; // terminate simulation
end
always @(disk_full)
if (disk_full)
$stop; // interrupt simulation and enter interactive mode
Initial forever #1000

$save (“checkpoint.dat”); // save allows the current simulation
// data to be saved to file
Integers vs Registers
z Integers are signed.

z Registers and nets are unsigned.
z Performing signed arithmetic use integer or
explicitly model the sign extension using
register.
z Registers can be assigned negative values,
but being treated as unsigned value.
21
Integers vs Registers (con’t)
Data type Interpretation by arithmetic

operators.
Data Interpretation
Type
net Unsigned
reg Unsigned
Integer Signed, 2’s
complement
time Unsigned
real Signed,
floating point
Testbench
Purpose
z To test your design you have to write a testbench
Description
z The testbench is a piece of verilog code that interacts
with your design.
z You can apply inputs and observe and store the
outputs.
22
Testbench Template
The Testbench
R e s e t
k lC
(DUT)
Design
Inputs Uhder Outputs
Test
Testbench Example
module TestBench;
reg Clk , Reset, ShiftReg ;
reg [9:0] DataIn, Packets[0:999];
Here the shift register is intantiated
wire [9:0] DataOut ; in the testbench to be tested
parameter L=10;
ShiftRegister DUT(ShiftReg, Clk, Reset, DataIn, DataOut);
Here all the signals are stored

initial in a database to be viewed later
begin
$shm_open("ShiftRegister.shm");
$shm_probe("AS");
#8000 $shm_close();
#200 $finish;
end
23

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What are some common mistakes made in combinational circuit design in Verilog?

What are some common mistakes made in combinational circuit design in Verilog?

What are some recommended coding styles to avoid inferred latches in combinational circuits?

What are some recommended coding styles to avoid inferred latches in combinational circuits?

EE577b: VLSI System Design

Professor Peter A. Beerel

Borrowed from Gandhi Puvvada EE560 notes (previously EE599)

Examples of Combinational Circuits

Include all input signals to sensitivity list

Avoid inferred latch in combinational circuits

Assign default value at the beginning (example IV).

Assign outputs for all input conditions (example III).

Use “else” (instead of “else if”) for the final priority

Combinational Circuit Example I

z Include all input signals to sensitivity list.

// Poor coding for AND gate.

z Recommended coding for AND gate.

always @(a or b) // include both “a” and “b”

Combinational Circuit Example II

z Poor coding style: missing “else statement”.

z Recommended coding style.

Combinational Circuit Example III

z Missing assignments and condition .

z Recommended coding style.

Combinational Circuit Example IV

z Poor coding style: missing condition

z Recommended coding style

Sequential process assignment

z Use non-blocking assign. in always @(posedge clk)

// Recommended coding style

z Process with synchronous reset.

Sequential circuit w/ async reset

z Process with asynchronous reset

module ASYNC_FF (d, clk, rst, q);

always @posedge clk or negedge RST)

FSM Coding Styles

I. Separate state memory (SM), next state logic

II. Combine state memory (SM) with next state

// State memory module

FSM with async reset (Style I)

// Next state logic (NSL) module (combinational)

// Output function logic (OFL) module (combinational)

FSM with Async Reset (Style II)

Full-Custom Design: 2-Step Coding Process

Behavioral RTL coding

Separate CU and DPU Example

Combined CU and DPU Example

Advantages of structural RTL coding

Structural RTL Coding

Advantages of structural RTL coding

start Mux_sel1 Mux_sel2 opcode en1 en2

‘include “cu.v” // file “cu.v” implements control logic unit

module top; // top level module

(module name) (instant name)

Datapath unit example (dpu.v)

module dpu(interface signals both inputs and outputs);

// In the design, we have 5 components as followings,

module mux_2_1(sel, in0, in1, out)

always @(sel, in1, in2) begin