CMOS DIGITAL VLSI DESIGN

Combinational Logic Design-IX

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 Pre-charge and Evaluation
VDD
• When CLK=0, the Out node is pre-
charged to VDD through Mp. During this CLK Mp Out
time Me is off which disables the PDN.
• For CLK=1, Mp gets off while Me enables
A CL
the PDN and based on the input C
B
topology of PDN the Out node gets
discharged. Me
• Once the Out node is discharged, it CLK
cannot be charged until the next pre-
charge cycle. Out=CLK+(A.B+C).CLK
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 Properties of Dynamic Logic Gate
• The construction of the PDN is same as static CMOS.
• The number of transistor is substantially lower than in the static case,
(N+2) versus 2N.
• It is non-ratioed. The sizing of PMOS pre-charge device is not
important for realizing proper functioning of the gate.
• It only consumes dynamic power. The overall power dissipation,
however, can be significantly higher compared with a static logic gate.
• These gates have faster switching speeds due to reduced load
capacitance attributed to the lower number of transistor per gate and
also due to the absence of short circuit current.
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 Speed and Power Dissipation of Dynamic Logic Gate
• The main advantage of dynamic logic are increased speed and
reduced implementation area. CLK VDD
out
In4 M4
In3 M3

In2 M2
In1 M1
CLK
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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 Signal Integrity Issues in Dynamic Design
1. Charge Leakage
• Ideally, if the pull-down network is off then output should be at VDD
during the evaluation phase.
• However, this charge gradually leaks away due to leakage currents.

Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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 Charge Leakage Solution- Bleeder Transistor
• The reduction in the output impedance during evaluation phase will
solve the leakage problem.
• This can be achieved by introducing a Bleeder Transistor.
VDD VDD
MbI MbI
CLK Mp Mp
CLK
A Out
Ma Out A Ma
B Mb B Mb
CLK Me CLK Me
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2. Charge Sharing
• Let the initial conditions are- Vout (t=0)=VDD and VX(t=0)=0, then-
 Case-I (∆Vout<VTn)- the final value of VX is VDD-VTn
 Ca 
 Case-II (∆Vout>VTn)- then VX and VDD reach the same value. out DD 
ΔV =-V 
C +C
 a L
VDD
CLK Mp
Ma Out
A
B=0 Mb Ca

CLK Me Cb

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3. Capacitive Coupling
• The relative high impedance of the output node makes the circuit
very sensitive to crosstalk effects. The wire next to a dynamic node
may couple capacitive and destroy the floating node.

Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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4. Clock Feedthrough
• An effect caused by the capacitive coupling between clock input of
the precharge device and the dynamic output node.
• The danger of clock feedthrough is that it may cause the normally
reverse biased junction diodes of precharged transistor to become
forward biased, eventually results in faulty operation.

Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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 Cascading Dynamic Gates
• The direct cascading of two stages of dynamic gates causes
problematic operation because the output of each stage i.e. the input
of next stage is precharged to 1.
VDD V DD

CLK Mp
Mp
Out1 CLK
In Out2

CLK Me Me
CLK
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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 Domino Logic
• A domino logic module consists of an n-type dynamic logic block
followed by a static inverter.
V VDD
DD
CLK CLK
In1
In2 PDN
In3 PDN
In4
In5
CLK Me
CLK Me

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 Properties of Domino Logic
• The introduction of static inverter has an advantage that the fan-out
of the gate is driven by static inverter with a low impedance output,
which increases noise immunity.
• Since each dynamic gate has a static inverter, only non-inverting logic
can be implemented.
• Very high speeds can be achieved: only rising edge delay exists, while
tpHL equals zero.
• The inverter can be used to drive bleeder device to combat leakage
and charge redistribution.

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 Dealing with non-inverting problem of Domino Logic
• A major limitation of domino logic is that only non-inverting logic can
be implemented. The one way to deal this problem is reorganizing
the logic using simple boolean transforms.

Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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• Another (expensive) way to solve the problem is by incorporating
differential logic. This is similar as DCVSL, and called as Dual-rail
Domino.

Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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 np-CMOS
• An alternative approach to cascade dynamic logic is np-CMOS, which
consists two flavors of dynamic logic (n-tree and p-tree).
VDD VDD
CLK Mp CLK
Mp
In1
In2 PDN
In3 PUN
In4
In5
CLK Me
To other M To other
CLK e
P-Blocks
N-Blocks
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 Recapitulation
• The operation of dynamic logic is divided into two major phases-
precharge and evaluation.
• Charge Leakage, Charge Sharing, Capacitive Coupling and Clock Feed-
through are causing signal integrity issues.
• To increase the noise immunity, the domino logic is proposed which
consist a static inverter in the dynamic logic block.
• np-CMOS is an alternative approach to cascade the dynamic logic.

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Thank You

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