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VHDL Assignment 1

The document provides VHDL code implementations of multiplexers, demultiplexers, encoders, and decoders using case and if-else statements. Specifically, it implements: 1) An 8:1 multiplexer and 1:8 demultiplexer using case statements. 2) An 8:1 multiplexer, 1:8 demultiplexer, 3:8 decoder, and 8:3 encoder using if-else statements.

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Bharat Ch
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155 views7 pages

VHDL Assignment 1

The document provides VHDL code implementations of multiplexers, demultiplexers, encoders, and decoders using case and if-else statements. Specifically, it implements: 1) An 8:1 multiplexer and 1:8 demultiplexer using case statements. 2) An 8:1 multiplexer, 1:8 demultiplexer, 3:8 decoder, and 8:3 encoder using if-else statements.

Uploaded by

Bharat Ch
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1. Implement 8:1 multiplexer using case statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity mux_8_1 is
Port (a: in BIT_VECTOR (7 downto 0);
s: in BIT_VECTOR (2 downto 0);
y: out BIT);
end mux_8_1;

architecture Behavioral of mux_8_1 is

begin
process (a, s)
begin
case s is
when "000" => y <= a (0);
when "001" => y <= a (1);
when "010" => y <= a (2);
when "011" => y <= a (3);
when "100" => y <= a (4);
when "101" => y <= a (5);
when "110" => y <= a (6);
when "111" => y <= a (7);
when others => y <= '0';
end case;
end process;
end Behavioral;

2. Implement 1:8 demultiplexer using case statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity demux_1_8 is
Port (a: in BIT;
s: in BIT_VECTOR (2 downto 0);
y: out BIT_VECTOR (7 downto 0));
end demux_1_8;

architecture Behavioral of demux_1_8 is


begin
process (a, s)
begin
case s is
when "000" => y (0) <= a;
when "001" => y (1) <= a;
when "010" => y (2) <= a;
when "011" => y (3) <= a;
when "100" => y (4) <= a;
when "101" => y (5) <= a;
when "110" => y (6) <= a;
when "111" => y (7) <= a;
end case;
end process;
end Behavioral;

3. Implement 8:1 multiplexer using if else statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity mux_8_1 is
Port (a: in BIT_VECTOR (7 downto 0);
s: in BIT_VECTOR (2 downto 0);
y: out BIT);
end mux_8_1;

architecture Behavioral of mux_8_1 is

begin
process (a, s)
begin
if (s = “000”) then
y <= a (0);
elsif (s = “001”) then
y <= a (1);
elsif (s= "010") then
y <= a (2);
elsif (s= "011") then
y <= a (3);
elsif (s= "100") then
y <= a (4);
elsif (s= "101") then
y <= a (5);
elsif (s= "110") then
y <= a (6);
else
y <= a (7);
end if;
end process;
end Behavioral;

4.Implement 1:8 demultiplexer using if else statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity demux_1_8 is
Port (a: in BIT;
s: in BIT_VECTOR (2 downto 0);
y: out BIT_VECTOR (7 downto 0));
end demux_1_8;

architecture Behavioral of demux_1_8 is


begin
process (a, s)
begin
if (s= "000") then
y (0) <= a;
elsif (s= "001") then
y (1) <= a;
elsif (s= "010") then
y (2) <= a;
elsif (s= "011") then
y (3) <= a;
elsif (s= "100") then
y (4) <= a;
elsif (s= "101") then
y (5) <= a;
elseif (s= "110") then
y (6) <= a;
else
y (7) <= a;
end if;
end process;
end Behavioral;

5.Implement 3:8 decoder using case statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity decoder_3to8_case is
Port (a: in BIT_VECTOR (2 downto 0);
y: out BIT_VECTOR (7 downto 0));
end decoder_3to8_case;

architecture Behavioral of decoder_3to8_case is

begin
process(a)
begin
case a is
when "000" => y <="00000001";
when "001" => y <="00000010";
when "010" => y <="00000100";
when "011" => y <="00001000";
when "100" => y <="00010000";
when "101" => y <="00100000";
when "110" => y <="01000000";
when "111" => y <="10000000";
end case;
end process;
end Behavioral;

6.Implement 8:3 encoder using case statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity encoder_8to3 is
Port (a: in BIT_VECTOR (7 downto 0);
y: out BIT_VECTOR (2 downto 0));
end encoder_8to3;

architecture Behavioral of encoder_8to3 is

begin
process(a)
begin
case a is
when "00000001" => y <= "000";
when "00000010" => y <= "001";
when "00000100" => y <= "010";
when "00001000" => y <= "011";
when "00010000" => y <= "100";
when "00100000" => y <= "101";
when "01000000" => y <= "110";
when "10000000" => y <= "111";
when others => y <="111";
end case;
end process;
end Behavioral;
7.Implement 3:8 decoder using if else statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity decoder_3to8_case is
Port (a: in BIT_VECTOR (2 downto 0);
y: out BIT_VECTOR (7 downto 0));
end decoder_3to8_case;

architecture Behavioral of decoder_3to8_case is

begin
process(a)
begin
if (a= "000") then
y <="00000001";
elsif (a= "001") then
y <="00000010";
elsif (a= "010”) then
y <="00000100";
elsif (a= "011") then
y <="00001000";
elsif (a= "100") then
y <="00010000";
elsif (a= "101") then
y <="00100000";
elsif (a= "110") then
y <="01000000";
else
y <="10000000";
end if;
end process;
end Behavioral;

8.Implement 8:3 encoder using if else statement.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity encoder_8to3 is
Port (a: in BIT_VECTOR (7 downto 0);
y: out BIT_VECTOR (2 downto 0));
end encoder_8to3;

architecture Behavioral of encoder_8to3 is

begin
process(a)
begin
if (a= "00000001") then
y <= "000";
elsif (a= "00000010") then
y <= "001";
elsif (a= "00000100") then
y <= "010";
elsif (a= "00001000") then
y <= "011";
elsif (a= "00010000") then
y <= "100";
elsif (a= "00100000") then
y <= "101";
elsif (a= "01000000") then
y <= "110";
elsif (a= "10000000") then
y <= "111";
else
y <="111";
end if;
end process;
end Behavioral;

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