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Verilog Code For Traffic Lights

The document describes a traffic light controller module that uses a Moore finite state machine to control two traffic lights (La and Lb) based on sensor inputs (Ta and Tb). It defines 4 states to control the light patterns - green/red, red/yellow, red/green, yellow/red. The state transitions are triggered by changes in the sensor values at each clock cycle. A testbench module is also defined to simulate the controller behavior.

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Ashish Rai
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© © All Rights Reserved
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Download as TXT, PDF, TXT or read online on Scribd
627 views

Verilog Code For Traffic Lights

The document describes a traffic light controller module that uses a Moore finite state machine to control two traffic lights (La and Lb) based on sensor inputs (Ta and Tb). It defines 4 states to control the light patterns - green/red, red/yellow, red/green, yellow/red. The state transitions are triggered by changes in the sensor values at each clock cycle. A testbench module is also defined to simulate the controller behavior.

Uploaded by

Ashish Rai
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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/* Implementation of the traffic light controller */

module traffic_controller(clk, reset, Ta, Tb, La, Lb);


input clk, reset, Ta, Tb; //inputs are Ta&Tb from the sensors

output reg [2:0] La,Lb; // in the lights - 001 for green; 010 for yellow; 100 for
red

/*the possible combinations of both the traffic lights are: */


parameter S1 = 2'b00; // La=001 & Lb=100 // i.e., green and RED
parameter S2 = 2'b01; // La=100 & Lb=010 // i.e., red and YELLOW
parameter S3 = 2'b10; // La=100 & Lb=001 // i.e., red and GREEN
parameter S4 = 2'b11; // La=010 & Lb=100 // i.e., yellow and RED

reg [1:0]present, next;

/*for the state transition at the posedge of clock*/


always@(posedge clk, posedge reset)
if(reset) present <= S1;
//the initial state is S1 which is here assumed
else present <= next;

/*moore machine approach*/


always@(present, Ta, Tb)
case(present)
S1 : begin
La = 3'b001; Lb = 3'b100;
if(Ta==0&&Tb==1) next = S2;
else next = S1;
end
S2 : begin
La=3'b100; Lb = 3'b010;
next = S3;
end
S3 : begin
La = 3'b100; Lb= 3'b001;
if(Ta==1&&Tb==0) next = S4;
else next = S3;
end
S4 : begin
La = 3'b010; Lb = 3'b100;
next = S1;
end
default : begin
La = 3'b001; Lb = 3'b100;
next = S1;
end
endcase

endmodule

// Ashish Rai
// 180102014

module test_traffic;
reg clk, reset, Ta, Tb;
wire [2:0]La,Lb;
traffic_controller junction(clk, reset, Ta, Tb, La, Lb);
initial
begin
clk = 0;
forever #2.5 clk = ~clk;
end
initial
fork
reset = 0;
#7 Ta=0;Tb=0;
#12 Ta=1;
#17 Ta=0;Tb=1;
#22 Ta=1;
#27 Tb=0;
#32 Ta=1;Tb=1;
#37 Tb=0;
#50 $finish;
join

endmodule

// Ashish Rai
// 180102014

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