X9C102, X9C103, X9C104, X9C503: Features
X9C102, X9C103, X9C104, X9C503: Features
X9C102, X9C103, X9C104, X9C503: Features
Block Diagram
U/D 7-BIT 99 RH/VH
INC UP/DOWN
CS COUNTER
98
VH/RH 7-BIT 96
UP/DOWN (U/D) NON-VOLATILE ONE
CONTROL MEMORY OF
INCREMENT (INC) AND RW/VW ONE-
MEMORY HUNDRED TRANSFER RESISTOR
DEVICE (CS) DECODER GATES ARRAY
SELECT VL/RL
2
VSS (GROUND) STORE AND
RECALL 1
GENERAL VCC CONTROL
CIRCUITRY 0
GND
RL/VL
DETAILED RW/VW
Ordering Information
PART PART RTOTAL TEMP RANGE PACKAGE PACKAGE
NUMBER MARKING (k) (°C) (RoHS Compliant) DWG. #
X9C102PZ (Notes 2, 3) X9C102P Z 1 0 to +70 8 Ld PDIP MDP0031
X9C102PIZ (Notes 2, 3) X9C102P ZI -40 to +85 8 Ld PDIP MDP0031
X9C102SZ (Notes 1, 2) X9C102S Z 0 to +70 8 Ld SOIC M8.15E
X9C102SIZ (Notes 1, 2) X9C102S ZI -40 to +85 8 Ld SOIC M8.15E
X9C103PZ (Notes 2, 3) X9C103P Z 10 0 to +70 8 Ld PDIP MDP0031
X9C103PIZ (Notes 2, 3) X9C103P ZI -40 to +85 8 Ld PDIP MDP0031
X9C103SZ (Notes 1, 2) X9C103S Z 0 to +70 8 Ld SOIC M8.15
X9C103SIZ (Notes 1, 2) X9C103S ZI -40 to +85 8 Ld SOIC M8.15
X9C503PZ (Notes 2, 3) X9C503P Z 50 0 to +70 8 Ld PDIP MDP0031
X9C503PIZ (Notes 2, 3) X9C503P ZI -40 to +85 8 Ld PDIP MDP0031
X9C503SZ (Notes 1, 2) X9C503S Z 0 to +70 8 Ld SOIC M8.15E
X9C503SIZ (Notes 1, 2) X9C503S ZI -40 to +85 8 Ld SOIC M8.15E
X9C104PIZ (Notes 2, 3) X9C104P ZI 100 -40 to +85 8 Ld PDIP MDP0031
X9C104SZ (Notes 1, 2) X9C104S Z 0 to +70 8 Ld SOIC M8.15E
X9C104SIZ (Notes 1, 2) X9C104S ZI -40 to +85 8 Ld SOIC M8.15E
NOTES:
1. Add “T1” suffix for tape and reel. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Descriptions
PIN
NUMBER PIN NAME DESCRIPTION
1 INC INCREMENT The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or
decrement the counter in the direction indicated by the logic level on the U/D input.
2 U/D UP/DOWN The U/D input controls the direction of the wiper movement and whether the counter is incremented or
decremented.
3 VH/RH VH/RH The high (VH/RH) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of
a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
4 VSS VSS
5 VW/RW VW/RW VW/RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically
40.
6 RL/VL RL/VL The low (VL/RL) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a
mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
7 CS CS The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when
CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102, X9C103,
X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again.
8 VCC VCC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
LIMITS
TYP
SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) MAX UNIT
POTENTIOMETER CHARACTERISTICS
RTOTAL End-to-End Resistance Variation -20 +20 %
Resolution 1 %
Relative Linearity (Note 5) VW(n + 1)(ACTUAL) - [VW(n) + MI] -0.2 +0.2 MI (Note 6)
RTOTAL Temperature Coefficient X9C103, X9C503, X9C104 ±300 (Note 8) ppm/°C
DC OPERATING CHARACTERISTICS
ISB Standby Supply Current CS = VCC - 0.3V, U/D and 200 750 µA
INC = VSS or VCC - 0.3V
ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC ±10 µA
CIN CS, INC, U/D Input Capacitance (Note 8) VCC = 5V, VIN = VSS, TA = +25°C, 10 pF
f = 1MHz
Electrical Specifications Over recommended operating conditions unless otherwise stated. (Continued)
LIMITS
TYP
SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) MAX UNIT
AC OPERATION CHARACTERISTICS
NOTES:
4. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum.
5. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI.
6. 1 MI = Minimum Increment = RTOT/99.
7. Typical values are for TA = +25°C and nominal supply voltage.
8. This parameter is not 100% tested.
RW
AC Conditions of Test
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 10ns
AC Timing Diagram
CS
tCYC
tCI tIL tIH tIC tCPH
90% 90%
INC 10%
tID tDI tF tR
U/D
tIW
VW MI (NOTE)
NOTE: MI REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER POSITION.
by the system or until a power-down/up cycle recalled the May change Will change
previously stored data. from Low to from Low to
High High
This procedure allows the system to always power-up to a pre- May change Will change
set value stored in non-volatile memory; then during system from High to from High to
Low Low
operation, minor adjustments could be made. The adjustments
might be based on user preference, i.e.: system parameter Don’t Care: Changing:
Changes State Not
changes due to temperature drift, etc. Allowed Known
N/A Center Line
The state of U/D may be changed while CS remains LOW. This is High
allows the host system to enable the device and then move the Impedance
wiper up and down until the proper trim is attained.
Performance Characteristics
Contact the factory for more information.
Applications Information
Electronic digitally controlled (XCDP) potentiometers provide
three powerful application advantages:
VH/RH
VW/RW
VL/RL
Basic Circuits
R1 +V +V +5V
+V VS + LM308A
+5V VO
–
VW OP-07
VREF + X -5V
VOUT VW/RW
–
+V R2
-5V
R1
VW/RW
VOUT = VW/RW
VO = (1+R2/R1)VS
(a) (b)
R1 R2
LT311A
VIN 317 VO (REG) VS VS –
VO
100k +
R1
–
VO
+
Iadj TL072
}
R2 10k R1 R2
10k 10k
VUL = {R1/(R1 + R2)} VO(MAX)
VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VLL = {R1/(R1 + R2)} VO(MIN)
+12V -12V
(FOR ADDITIONAL CIRCUITS SEE AN1145)
Revision History
Rev. Date Description
4.00 Jan 11, 2019 Updated Ordering Information table to remove Obsolete and Retired parts.
Added Revision History.
Updated PODs for X9C102, X9C104, and X9C503 SOICs from: MDP0027 to: M8.15E and X9C103 SOIC from:
MDP0027 to: M8.15, to include the Land Pattern design and convert dimensions from table to graphics.
Updated Intersil disclaimer to Renesas disclaimer.
Package Outline Drawings For the most recent package outline drawing, see M8.15.
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
8°
1 2 3 0°
0.25 (0.010)
0.19 (0.008)
TOP VIEW SIDE VIEW “B”
2.20 (0.087)
1 8
SEATING PLANE
3 6
-C-
4 5
1.27 (0.050) 0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013) 5.20(0.205)
NOTES:
9. Dimensioning and tolerancing per ANSI Y14.5M-1994.
10. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
11. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
12. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
13. Terminal numbers are shown for reference only.
14. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
15. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
16. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
M8.15E For the most recent package outline drawing, see M8.15E.
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10 A
DETAIL "A" 0.22 ± 0.03
6.0 ± 0.20
3.90 ± 0.10
PIN NO.1
ID MARK
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
0.175 ± 0.075 SEATING PLANE
0.10 C
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27) (0.60)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
Plastic Dual-In-Line Packages (PDIP) For the most recent package outline drawing, see MDP0031.
D E N
PIN #1
A2 A INDEX
E1
SEATING
PLANE c
L
A1
eA 1 2 N/2
NOTE 5
e b eB b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES
A 0.210 0.210 0.210 0.210 0.210 MAX
A1 0.015 0.015 0.015 0.015 0.015 MIN
A2 0.130 0.130 0.130 0.130 0.130 ±0.005
b 0.018 0.018 0.018 0.018 0.018 ±0.002
b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015
c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002
D 0.375 0.750 0.750 0.890 1.020 ±0.010 1
E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010
E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2
e 0.100 0.100 0.100 0.100 0.100 Basic
eA 0.300 0.300 0.300 0.300 0.300 Basic
eB 0.345 0.345 0.345 0.345 0.345 ±0.025
L 0.125 0.125 0.125 0.125 0.125 ±0.010
N 8 14 16 18 20 Reference
Rev. C 2/07
NOTES:
17. Plastic or metal protrusions of 0.010” maximum per side are not included.
18. Plastic interlead protrusions of 0.010” maximum per side are not included.
19. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
20. Dimension eB is measured with the lead tips unconstrained.
21. 8 and 16 lead packages have half end-leads as shown.