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PCC CS 302 3rd Internal

This document contains details of an internal examination for Computer Organization for second year B.Tech students at Gargi Memorial Institute of Technology. It includes short answer and long answer questions related to topics like cache memory organization, memory addressing techniques, memory interfacing with CPU, memory hierarchy and performance analysis. The long answer questions require calculations to determine memory subsystem parameters like address field sizes for different mapping techniques, number of RAM chips required for a given memory size, bus connections between CPU and memory, classification of instructions, construction of common bus system using tri-state buffers, and determining main memory access time to achieve a target effective access time given cache and disk access times and hit ratios.

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200 views1 page

PCC CS 302 3rd Internal

This document contains details of an internal examination for Computer Organization for second year B.Tech students at Gargi Memorial Institute of Technology. It includes short answer and long answer questions related to topics like cache memory organization, memory addressing techniques, memory interfacing with CPU, memory hierarchy and performance analysis. The long answer questions require calculations to determine memory subsystem parameters like address field sizes for different mapping techniques, number of RAM chips required for a given memory size, bus connections between CPU and memory, classification of instructions, construction of common bus system using tri-state buffers, and determining main memory access time to achieve a target effective access time given cache and disk access times and hit ratios.

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GargiMemorial cse
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Gargi Memorial Institute of Technology Campus

3rd Internal Examination for 2nd year B. Tech course for the year 2019-2020
(Semester III)
Subject: Computer Organization
Department: CSE
Subject Code: PCC CS 302
Full Marks: 15 Time: 1 hour
Short Answer Type(5*1 marks)

1. A hit is considered when a


a)word is found in cache b) Word is found in RAM
c) word is found in virtual memory d)Word is found hard disk
2. Which of the memory is volatile in nature
a)ROM b)DVD-ROM
c)CD-ROM d)RAM
3. How many memory location can be accessed by a 32 bit computer?
a)4Mb b)34kb
c)34Gb d)4GB
4. How many address bit is required for a 1024*8 memory?
a)4 b)3
c)2 d)10
5. Associative memory is a
a)point addressable memory b)very cheap memory
c)content addressable memory d)none of these
Short Answer Type(5*1 marks)

6.A cache has 64KB capacity,128 bytes lines and 4 way se associative .The CPU generates a 32 bit address for accessing
data in the memory.

a)How many lines and set does the cache have?


b)How many entries are required in the tag field?
c)How many bits of tags are required n each entry in tag array?
7.Classify the different cache writing technique?Categorige the locality of reference principle with example?

Long Answer types(1*10 marks)Answer any one

11. a)Determine the subfield (in bits) in the address for Direct mapping, Associative mapping, Set associative
mapping
 256 mb main memory
 1mb cache memory
 Block size 128 bytes
 8 block in a cache set
b) How many 256*4 RAM chip are needed to provide a memory capacity of 2048 bytes? Show the inter-
connection diagram? ((3*2)+4

12.a))Show the bus connection with a CPU to connect four RAM chips of size 256*8 bits each and a ROM chip of 521*8
bit size. Assume the CPU has 8 bit data bus and 16 bit address bus?
b)A hierarchical cache-main memory subsystem has the following specification: Cache access time=160ns,Main
memory access time=960ns,Hit ratio=0.9 Calculate the a)Avg access time of the memory system b)Efficiency
of the memory system
5+3+2

13.a))Classify MRI and Non-MRI instruction?


b)Describe tri-state buffer constructing a single line common bus system?
c)Define guard bits?
d) A three level memory system having cache access time of 15 ns and disk access time of 80 ns has a cache
hit ratio of 0.96 and main memory hit ratio of 0.9.What should be the main memory access time to achieve
effective access time of 25 ns?

2+2+1+5

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