Microprocessor

Packaging
The Key Link in the Chain

Koushik Banerjee
Technical Advisor
Assembly Technology Development
Intel Corporation

1
 Microprocessors

1971 2001

2
 Global Packaging R&D

China
Shanghai
Philippines
Cavite
Arizona
Chandler Malaysia
Penang

Virtual
Virtual ATD
ATD
3
Main R&D facility in
Chandler, AZ

4
Computing needs
driving
complexity

First to introduce organic in

mainstream CPUs

First to introduce flip chip in

mainstream CPUs
Intel 486TM Pentium®
Processor Processor
Pentium® Pro Pentium® II
Processor Processor
Pentium® III
Processor
Pentium® 4
Processor
Itanium®
Processor

25 MHz 1.0+ GHz

Ceramic Wire-bond
To Organic To Flip Chip 5
 Looking ahead …
Complexity and Challenges
to support Moore’s Law
1. Silicon to package interconnect
2. Within package interconnect
3. Power management
4. Adding more functionality

Goal
Goal :: Bring
Bring technology
technology innovation
innovation into
into
High
High volume
volume manufacturing
manufacturing at at aa LOW
LOW COST
COST
6
 Silicon ? Package
Relationship
Anatomy 101
Silicon Processor:
The “brain” of the computer
(generates instructions)

Packaging:
The rest of the body
(Communicates instructions
to the outside world, adds
protection)

No
No Package
Package =
= No
No Product
Product !!
Great
Great Packaging
Packaging =
= Great
Great Products
Products !!
!! 7
 The Key Link in the Chain
Opportunity
Opportunity
Transistor-to-Transistor Innovative,
Innovative, efficient,
efficient,
Ckt Blk to Ckt Blk high
high performance,
performance, low-
low-
cost
cost packages
packages are
are aa
significant
significant competitive
competitive
advantage
advantage
Chip-to-Package

Package-
to-Board
Board-to-System

8
Example – Enabling
Custom solutions
Silicon
Silicon Enabler
Enabler

Value
ValueAdd
Add::custom
custom
solutions
solutionsbased
based
on
onmarket
marketsegment
segment
9
 Breaking Barriers to
Moore’s Law 1 Billion
K
Transistors
1,000,000

100,000 Pentium®4 Processor

Pentium® II Processor
10,000 Pentium® III Processor
Pentium® Processor Pentium® Pro Processor
1,000
i486™ Processor
i386™ Processor
100
80286
The
TheNumber
Numberof ofTransistors
TransistorsPer
Per
10 8086 Chip
Chipwill
willDouble
DoubleEvery
Every1818
Months
Months
1
’75 ’80 ’85 ’90 ’95 ’00 ’05 ’10 ’15
Source: Intel

Integrated
Integrated Packaging
Packaging ++ Silicon
Silicon Technology
Technology
development
development isis essential
essential
10
Challenge # 1

Silicon to package
interconnect

11
 Approaching 10K flip
chip bumps on a die
Flip Chip (C4)
interconnect
Number of flip chip bumps

Underfill
10K
Silicon

Package

0
Pentium III® ItaniumTM
Family Family Future
Pentium 4 ®
Family generations

Driver
Driver –– increased
increased silicon
silicon
functionality
functionality 12
Solution : Aggressive Bump
Pitch Scaling to keep down
die size Solder
Bumps

Key Challenges :
• Plating bumps
• Chip Attach Process
• Underfill
Human • Joint integrity
Hair • HVM scalable process
Strand

13
Which leads us to …

Challenge # 2

Within package
Interconnect

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Solution : High Density
Interconnect
Very high
escape
routing
density
from the
die

Package
Traces

Lines narrower
Driver
Driver :: Need
Need high
high wiring
wiring than hair
density
density
Human Hair 15
Dimensional Stack-Up

Line in Silicon
130 nm
(100X magnification)

Line in Package
25 um
(100X magnification)
Line in Motherboard
5 mils (0.005”)
(100X magnification)

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 Approaching 40K micro
vias inside a package
# of micro-vias in package

Chip Attach
40K Micro-vias Pads

0
Pentium III® ItaniumTM Package X -section
Family Family
Pentium 4 ® Future
Family generations

Driver
Driver –– High
High I/O
I/O count
count &
& power
power
supply
supply 17
Solution : Advanced
lithography (new term in packaging !)
C/A pads Key Challenges :
Wire
• Developing HDI (high
density interconnect) at
LOW COST
• High Volume
Manufacturing Capable

Via Build-Up
dielectric
Core

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Core frequency trend …
doubling every 2 years
100,000

10,000

1,000

Frequency P6
100
(MHz) Pentium® proc
486
10 8085 386
8086 286
1 8080
8008
0.1 4004
’70 ’80 ’90 ’00 ’10

Source : Intel Architecture Labs

In addition …
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 FSB frequency ramp
continues
Max Mega transfers / second

400

133
66

Pentium® II Pentium® III Pentium® 4

Processor Processor Processor Future Generation Processors

Microprocessor Generation
20
Solution : High Performance
Interconnect Technology
Benefits of organic
1. Copper – Low resistance
2. Low dielectric constant
3. Cheaper
High Performance Silicon
Copper Interconnects
Key Challenge :
? Optimize the entire substrate
architecture (material
properties, layer stack-up,
via placement, power
bussing etc.)
Organic Packaging
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Solution : Better designs

A poor design can

ruin processor
performance

Key Challenges :
? Signal Timing
? Innovative routing – layout
? Optimizing power / ground distribution
? Co-design of the complete silicon ? package interconnect
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Switching gears from
interconnect to …

Challenge # 3

Power Management

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 Power Increasing, silicon
getting smaller
Pentium®
Power 100 processors
(Watts)
286 486
8086
10 386
8085
8080
8008
1 4004

0.1

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Source : Intel Architecture Labs

Two Challenges …
Getting power in & getting heat out
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 Importance of a quiet Power
Supply

High
Low
Ideal state
High
Low

Reality – noise

OR
High
Low
OR
This is what Voltage Scaling can do
25
Need lots of charge, very
quickly …
Increasing distance from supply

Hot Water Inefficient

Heater design

Still Waiting !!

Close
Proximity
to supply
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Solution : Optimize design
for power delivery
Key Challenge:
?2X improvement in
Cpkg capacitance and
Lpkg
inductance needed /
Cpkg (uF)

lpkg (pH)
generation
?Need to optimize the
complete silicon ?
package integrated
0.18 um Future power delivery
Generation Generation
processors 130 nm processors solution
Generation
processors

27
Solution : Reduce system
design burden – heat removal
Temp – Package
Temp – Silicon Temp – Ambient
Case (T c)
(Tj) (Ta)

Temperature Gradient
OEM
Packaging Provide Solutions
Provide Solutions for this interface
for this interface of the budget
of the budget

Integrated
Integrated Thermal
Thermal Solutions
Solutions inin the
the
package
package reduce
reduce heat
heat flux
flux –– easier
easier to
to cool
cool in
in
the
the system
system
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Example : Pentium4 ®

High conductivity
Thermal Interface
Integrated High Material
Conductivity Heat
Spreader

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Example : Itanium ®

Schematic of
Schematic of how
how aa typical
typical heat
heat pipe
pipe works
works
Water Vapor
Wick Structure

Heater Block
Vapor Condenses
Cooler Section Evaporation
Integrated heat pipe Of Heat Pipe Cooler Section
technology interfacing Of Heat Pipe

directly to the
Condensed water flows back
silicon Heat Source
through the wick structure by
capillary action
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And finally …

Challenge # 4

Adding more
functionality

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Solution : High Density
interconnect = more
integration

High Density
Interconnect enables
a large cache
memory integration
in a small space

Leveraging packaging instead

of adding onto silicon 32
Solution : Massive
integration = more features

On CPU Voltage
regulation

RASM

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In Summary …

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We talked about future
Complexity and Challenges
to support Moore’s Law
1. Silicon to package interconnect
2. Within package interconnect
3. Power management
4. Adding more functionality

Intel’s Packaging Strategy

Innovative Technology
Making Technology Affordable
Smart designs
Integrated silicon + packaging solutions
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For more information, please visit ….

http://www.intel.com/research/silicon/packaging.htm

http://developer.intel.com/technology/itj/
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