1

Arm Cortex Architecture

Ahir Aditya Meet Bhanushali
17bec006 17bec015
Institute of technology Institute of technology
Nirma university, Ahmedabad Nirma university, Ahmedabad

Abstract—These discussion gives an idea about the various

ARM architectures and its verity, performance, instruction sets,
resisters, pipelining process, comparison with x86 and application
in various areas.

I. INTRODUCTION
The Advance RICS Machines (ARM) was first to introduce
the reduced instruction set architecture (RICS) to reduce the
code size and increase the code density for better performance
of microprocessor. It was introduced in 1990s. over the time
the need of reducing space consumption and improvement in
performance was required. So, in 2006 the ARM came with Figure I-1: capability and performance
the cortex architecture to overcome the space consumption
problems and interrupt capacity. II. EVOLUTION OF ARM ARCHITECTURE
The 32bit microcontroller market was targeted by ARM With the time ARM has developed many new versions of
with the release of first 32bit cortex architecture. The first of its architecture and added many new system blocks in this
the cortex architecture was released in 2006 by ARM which design. First version was ARMv1. After that many versions
provides many extra features with very low gate count and like ARMv2, ARMv3, etc. was introduced by ARM. Latest
very less instruction using RISC which was only provided by version is ARMv8 which comes under cortex-A55, cortex-
high end processors.[1] A75, cortex-A76 holding and has 32/64-bit core bit width.
The two major problem faced by 32bit market was power This is used under application profile and used by many well-
consumption and efficiency of the processors, which was known manufacturer companies like Samsung, Nvidia, etc.
overcome by this architecture. The use of c programming The ARM architecture ARM1176TZ(F)-S is also used in
language and well-established architecture resulted into the high end applications such as smartphone. The ARMv5E was
reduction of development time and reduction in testing cost. also acquaint with the ARM9E processors families. This
This processor architecture was built on the success of the architecture further enhanced to perform digital signal
previous 32bit ARM7 architecture with over 1 billion processing (DSP) for multimedia applications. Going further
processors produced each year. The non-maskable interrupt ARMv6 was introduced with new memory feature and single
for the specific tasks, nested vector inputs, optional memory instruction multiple data (SIMD) instructions.
protection unit as well as the atomic bit manipulation makes With the introduction of ARM11 new technologies came
the cortex architecture desirable to users. into pictures like optimized Thumb 2 instruction set which is
The ARM cortex family is RISC architecture which high end processor and cost efficient.[3]
consists of large uniform register file, load and store The ARMv7 architecture is classified in three different
architecture. Due to this we achieve high performance, low profiles:
code size, low power consumption and low silicon area. It uses  A profile
THUMB instruction set which can change the instruction  R profile
length accordingly from 32bit to 16bit and work with both  M profile
without any interface problem.[2]

.
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T
A
B
L
E

I
U
N
I
T
S

F
O
R
Figure II-2: architecture versions and features
M
A
G
N
E III. PROCESSOR NAMING
T
ARM uses specific naming pattern to give name to their
I
processors.
C It also uses specific suffices to show processors
features. For example, if we take case of ARM7TDMI here
P
ARM7 stands for architecture version 7, T indicates thumb
Figure II-1: versions of cortex architecture R
instruction
O
support, D indicates JTAG debugging, M for fast
The A profile is intended for application use. It consists of multiplier,
P I for an embedded ICE module.[4]
E In general, we can identify features of any ARM processor
32bit and 63bit ARM processors. The 32bit ARM A profile
R
architecture uses ARMv7 architecture in implementation. The by
T
following methodology:
main difference between ARM R profile and ARM M profile I
is that ARM A profile has a memory management unit (MMU) E ARM[x][y][z][T][D][M][I][E][J][F][S]
S
as many modern operating system requires MMU to run. The v
64bit ARM A profile uses the ARMv8-A architecture to e  x: family
implement. r  y: memory management/protection
t
The R profile is intended for real-time and safety critical i
 z: cache
applications. It is the family of 32bit ARM processors. This c  T: Thumb mode
profile is used where very high level of safety is required. Such a  D: JTAG debugging
l
as automobile braking system where human safety is involved  M: fast multiplier
or which is major concern. It has features such as non l  I: embedded ICE microcell
overlapping memory regions, increased exception handling i  E: enhanced instruction
capacity, memory protection unit (MPU), fast non-maskable n
e  J: Jazalle, hardware accelerated java
interrupts, etc. which makes it useful in such safety critical s  F: floating point unit
applications.
a
 S: synthesizable version
The M profile is used in microcontrollers, ASICs, ASSPs,
r
FPGAs and SoCs. It consists of 32bit ARM RICS processors. e IV. INSTRUCTION SET
It is one of the most shipped processor family of ARM cortex.
Some cortex M cores have FPU option which when included o how the software will control the hardware is defined by its
called “cortex Mx with FPU” or “cortex-MxF”. The cortex instruction
p set. Basically, it tells us that how the
t
communication is going to happen between the software and
M0/ M0+/ M1 has the ARMv6 M architecture, cortex M3 has i
the ARMv7 M architecture and cortex M4/ M7 has ARMv7-E hardware.
o The ARM architecture supports three types of
architecture. Coprocessors was not allowed with cortex M instruction
n set:
until the cortex M35 was introduced. M35 allows coprocessors
a  A64
l
with new ARMv8-M architecture.  A32
ARM architecture is evolved over the time and many i  T32
n Where A64 and A32 has fixed instruction length of 32bit.
versions of architecture is introduced till now with enhanced
performance and added features having the different T32
t came into picture as a replacement for 32bit instruction
instruction sets and hardware units. set
a which uses 16bit fixed length instruction set. And has a
b
high code density. Over the time T32 evolved into 16bit and
l
32bit
e
mixed length instruction set which gives trade off
between
s performance and instruction length.
.

S
t
a
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Figure IV-1: instruction sets

The A32 is 32bit load and store instruction set where all
the instructions are conditionally executed in a single cycle. It Figure IV-2: thumb-2 code density
has uniform 16*32bit register file. It has fixed 32bit instruction
length which ease the decoding of codes and pipelining V. RESISTERS
process at the cost of reduced code density. Later on, thumb ARM architecture has 16 resisters of 32bit which includes
instruction set was introduced to reduce 32bit to 16bit with no stack pointer, program counter and link resister. In which R0
effect on other parameters and increased code density. After to R7 are same for all CPU modes; they are never banked.
thumb1 instruction set thumb2 instruction set is introduced Resister R8 to R12 are same across all CPU modes except FIQ
which includes both 32bit and 16bit instruction as per mode. R13 is referred as stack pointer, R14 is referred as link
requirement and gives tradeoff between performance and code resister and R15 is referred as program counter. The last
density. resister is called current program status resister (CPSR) which
has 32bit.
 Data processing instruction
SUB r0, r5, #5 VI. PIPELINES AND IMPLEMENT ISSUE
-r0=r5-5
 Branching instruction The ARM7 and all earlier architecture has three stage
B <label> pipelining procedure which is fetch, decode and execute.
-branch forward Higher performance designs have deeper pipelining. Like
 Memory access instruction ARM9 cortex-A8 has thirteen stages pipelining. Pipelining is
LDR r0, [r1] most useful in high speed computers as it increases the speed
-load word of r1 into r0 of parallel execution of instructions. Though always it is not
 Thumb instruction directly proportional with speed up but it gives the better
It is 16bit instruction set which gives better code performance compared to other system architectures.[5]
density but not generally considered for hand
coding.
 Thumb 2 instruction
It is extension to thumb instruction which adds
32bit instructions to thumb technology and it is
implemented in almost all ARM processors. The
mix of 16bit and 32bit is automatically selected by
compiler. As there are no switching between thumb
technologies.
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loading and saving data from/to memory while x86 can

operate on direct memory as well. ARM is also 32-bit
architecture, favouring four-byte operations over others, so
ARM is a simpler architecture leading to small silicon area and
lots of power save feature while x86 becoming power beast in
terms of both power consumption and production.[6]
ARM has more registers, supported prediction for most
instructions long before Intel added it, has a "thumb" mode
that's intended primarily to increase code density-So a program
fits in less memory and has long incorporated all sorts of
techniques to save power.

Intel put a lot more emphasis on speed than power

consumption. They started emphasizing power consumption
primarily in the context of laptops. For laptops, their typical
power goal was 6 watts for fairly small laptops. More recently
Figure VI-1: pipelining process they've started to target mobile devices. but their approach has
been substantially different from ARM, emphasizing
In pipelining process an effort is made to achieve the fabrication technology where the arm has mostly emphasized
tradeoffs and overheads limiting the speedup of the micro-architecture.
computer architecture. Using a mathematical model created There is a wide range of microcontrollers and ASSP/ASIC
by taking the roleplay of various instruction into count the applications that require a simple processor with a small
speedup of the system is calculated. Using the pipelining instruction set, while still need to have very capable interrupt
process the IPC count is increased so system gives better handling capacity. while the cortex-M1 processor is optimized
performance. for FGPA designs, it was not optimized for low-power
applications so that it is not suitable for these applications. as a
result, ARM decided to design a new processor based on the
ARMv6-M architecture and optimized it for low-power
designs and low-cost microcontrollers.
The outcome was the cortex-M0 processor, at a minimum
gate count of just 12K gates it enabled many ultra-low-power
designs to integrate a high-performance processor, together
with the sensor, wireless communications chipset, smart
analog components, etc. the ARMv6-M architecture is also
used in SC000, one of the Secure Core processor products
developed for Smart Cards and other security products.

Figure VI-2: cortex 13 stage pipelining

VII. APPLICATIONS
Since the x86 is the older architecture that ARM has been
Competing , We are going to focus on only the difference
between ARM and x86.The main advantages of the arm, are in
power consumption Which made it attractive for all battery-
operated devices and performance saving features like out-of-
order execution, Which Intel has been working on getting into
their newer x86 processor. since ARM is RICS architecture
while x86 being a CISC. The core difference between those in
ARM is operated only on registers with few instructions for
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[6] Understanding ARM Architectures By David Chisnall Aug

23, 2010

Figure VII-1: cortex A8

CONCLUSION

ARM cortex architecture has many features that can be

used in many areas. It uses the different instruction set which
reduces code size up to 60% results into increased code
density and performance. Over the time ARM has introduced
many versions and families of architecture which is task
specified and have a particular features and system blocks for
specific use. ARM improved the performance of its
architectures by using pipelining process which reduces the
execution time for better performance.

REFERENCES
[1] https://www.sciencedirect.com. Retrieved 9/1/2019

[2] Acorn RISC Machine (ARM) Family Data Manual

By Prentice Hall, 1990

[3] http://infocenter.arm.com. Retrieved 9/1/2019

[4] https://community.arm.com. Retrieved 9/1/2019

[5] https://en.wikipedia.org/wiki/ARM_architecture.
Retrieved 9/1/2019