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Comparateur 1bit Structurelle

This document contains VHDL code for several digital logic components including comparators, half adders, full adders, and counters. It implements these components using both structural and behavioral modeling with different architectures.

Uploaded by

Mohamed Chamess
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
75 views5 pages

Comparateur 1bit Structurelle

This document contains VHDL code for several digital logic components including comparators, half adders, full adders, and counters. It implements these components using both structural and behavioral modeling with different architectures.

Uploaded by

Mohamed Chamess
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VHDL

Comparateur 1bit structurelle


library ieee;

use ieee.std_logic_1164.all;

entity cmp1bit is

port(a,b:In std_logic; E,I,S:out std_logic);

end cmp1bit;

Architecture archcmp1bit of cmp1bit is

component non is

port(a0:In std_logic; b0:out std_logic);

end component;

component et is

port(a3,c3:In std_logic; b3:out std_logic);

end component;

component nxou is

port(a5,c5:In std_logic; b5:out std_logic);

end component;

signal s0,s1 :std_logic;

begin

l0: non port map (b,s0);

l1: non port map (a,s1);

l2: et port map (a,s0,S);

l3: et port map (s1,b,I);

l4: nxou port map (a,b,E);

end archcmp1bit;

Comparateur comportemental
library ieee;

use ieee.std_logic_1164.all;

entity Comparateurcmp is

port(A,B:IN std_logic; E,S,I:OUT std_logic);


end Comparateurcmp;

Architecture ArchComparateurcmp of Comparateurcmp is

begin

P1:Process(A,B)

Begin

if(A='0' and B='0') then E<='1'; S<='0'; I<='0';

else

if(A='1' and B='0') then E<='0'; S<='1'; I<='0';

else

if(A='0' and B='1') then E<='0'; S<='0'; I<='1';

else

E<='1'; S<='0'; I<='0';

end if;

end if;

end if;

end process;

end ArchComparateurcmp;

Comparateur Float
library ieee;

use ieee.std_logic_1164.all;

entity Comparateurflot is

port(A,B:IN std_logic; E,S,I:OUT std_logic);

end Comparateurflot;

Architecture ArchComparateurflot of Comparateurflot is

begin

E<= A xnor B;

S<= A and not(B);

I<= not(A) and B;

end ArchComparateurflot;
Demi add float
library ieee;

use ieee.std_logic_1164.all;

entity demi_add is

port (a,b:in std_logic; c,s:out std_logic);

end demi_add;

architecture arch_demi_add of demi_add is

begin

c<=a and b;

s<= a xor b;

end arch_demi_add;

Demi add Comportemental


library ieee;

use ieee.std_logic_1164.all;

entity demi_addcomp is

port (a,b:in std_logic; c,s:out std_logic);

end demi_addcomp;

architecture arch_demi_addcomp of demi_addcomp is

begin

process(a,b)

variable vect:std_logic_vector(1 downto 0);

begin

vect:=a&b;

if(vect="11")then s<='0';c<='1';

elsif(vect="00") then s<='0';c<='0';

else s<='1';c<='0';

end if;

end process;

end arch_demi_addcomp;

Demi add struct


library ieee;
use ieee.std_logic_1164.all;

entity demiadd is

port( a0,b0:in std_logic; s0,c0:out std_logic);

end demiadd;

architecture archdemiadd of demiadd is

component et is

port(a1,b1: in std_logic; c1:out std_logic);

end component;

component xou is

port (a2,b2:in std_logic; s2:out std_logic);

end component;

begin

liaison1: et port map (a0,b0,c0);

liaison2: xou port map (a0,b0,s0);

end archdemiadd;

Full add float


library ieee;

use ieee.std_logic_1164.all;

entity full_addflot is

port (a,b,cin:in std_logic; c,s:out std_logic);

end full_addflot;

architecture arch_full_addflot of full_addflot is

begin

c<=(cin and(a xor b))or(a and b);

s<=a xor b xor cin;

end arch_full_addflot;

Full add comp


library ieee;

use ieee.std_logic_1164.all;

entity full_addflot is
port (a,b,cin:in std_logic; c,s:out std_logic);

end full_addflot;

architecture arch_full_addflot of full_addflot is

begin

c<=(cin and(a xor b))or(a and b);

s<=a xor b xor cin;

end arch_full_addflot;

Compteur
library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity Compteur is

port(clk:In std_logic; Q:out std_logic_vector(3 downto 0));

end Compteur;

Architecture ArchCompteur of Compteur is

signal c:std_logic_vector(3 downto 0):="0000";

begin

p1:process(clk,c)

begin

if (clk'event and clk = '1') then

c<=c+1;

end if;

Q<=a;

end process;

end ArchCompteur;

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