The Modern Digital Design Flow

The purpose of a hardware description languages is to describe digital circuitry using a text-
based language. HDLs provide a means to describe large digital systems without the need for
schematics, which can become impractical in very large designs. HDLs have evolved to support
logic simulation at different levels of abstraction. This provides designers the ability to begin
designing and verifying functionality of large systems at a high level of abstraction and
postpone the details of the circuit implementation until later in the design cycle. This enables
a top-down design approach that is scalable across different logic families. HDLs have also
evolved to support automated synthesis, which allows the CAD tools to take a functional
description of a system (e.g., a truth table) and automatically create the gate-level circuitry to
be implemented in real hardware. This allows designers to focus their attention on designing
the behavior of a system and not spend as much time performing the formal logic synthesis
steps as in the classical digital design approach. The goal of this chapter is to provide the
background and context of the modern digital design flow using an HDL-based approach.
There are two dominant hardware description languages in use today. They are VHDL and
Verilog. VHDL stands for very high-speed integrated circuit hardware description language.
Verilog is not an acronym but rather a trade name. The use of these two HDLs is split nearly
equally within the digital design industry.

Why does VHDL support modeling techniques that aren’t synthesizable?

(A) Since synthesis wasn’t within the original scope of the VHDL project, there wasn’t
sufficient time to make everything synthesizable.

(B) At the time VHDL was created, synthesis was deemed too difficult to implement.

(C) To allow VHDL to be used as a generic programming language.

(D) VHDL needs to support all steps in the modern digital design flow, some of which are un-
synthesizable such as test pattern generation and timing verification.

VHDL Constructs

VHDL model construction covers the built-in features of a VHDL model including the file
structure, data types, operators, and declarations. This provides a foundation of VHDL that will
lead to modelling examples. VHDL is not case sensitive. Each VHDL assignment, definition,
or declaration is terminated with a semicolon (;). As such, line wraps are allowed and do not
signify the end of an assignment, definition, or declaration. Line wraps can be used to make
the VHDL more readable. Comments in VHDL are preceded with two dashes (i.e., --) and
continue until the end of the line. All user-defined names in VHDL must start with an
alphabetic letter, not a number. User-defined names are not allowed to be the same as any
VHDL keyword.
The following notations will be used when introducing new constructs:

italics: User-defined name

<>: A required characteristic such as a data type, input/output, etc.

Data Types

In VHDL, every signal, constant, variable, and function must be assigned a data type. The IEEE
standard package provides a variety of pre-defined data types. Some data types are
synthesizable, while others are only for modelling abstract behavior. The following are the
most commonly used data types in the VHDL standard package.

Enumerated Types

An enumerated type is one in which the exact values that the type can take on are defined. Type
Values that the type can take on bit {0, 1} boolean {false, true} character {“any of the 256
ASCII characters defined in ISO 8859-1”} The type bit is synthesizable, while Boolean and
character are not. The individual scalar values are indicated by putting them inside single
quotes (e.g., ‘0,’ ‘a,’ ‘true’).

Range Types

A range type is one that can take on any value within a range.

integer: Whole numbers between 2,147,483,648 and +2,147,483,647.

real: Fractional numbers between 1.7e38 and +1.7e38.

The integer type is a 32-bit, signed, two’s complement number and is synthesizable. If the full
range of integer values is not desired, this type can be bounded by including range to. The real
type is a 32-bit, floating point value and is not directly synthesizable unless an additional
package is included that defines the floating-point format. The values of these types are
indicated by simply using the number without quotes (e.g., 33, 3.14).

Physical Types

A physical type is one that contains both a value and units. In VHDL, time is the primary
supported physical type. The base unit for time is fs, meaning that, if no units are provided, the
value is assumed to be in femtoseconds. The value of time is held as a 32-bit, signed number
and is not synthesizable.

Vector Types

A vector type is one that consists of a linear array of scalar types.

bit_vector: A linear array of type bit

string: A linear array of type character.

The size of a vector type is defined by including the maximum index, the keyword downto,
and the minimum index. For example, if a signal called BUS_A was given the type bit_vector(7
downto 0), it would create a vector of 8 scalars, each of type bit. The leftmost scalar would
have an index of 7 and the rightmost scalar would have an index of 0. Each of the individual
scalars within the vector can be accessed by providing the index number in parentheses. For
example, BUS_A (0) would access the scalar in the rightmost position. The indices do not
always need to have a minimum value of 0, but this is the most common indexing approach in
logic design. The type bit_vector is synthesizable, while string is not. The values of these types
are indicated by enclosing them inside double quotes (e.g., “0011,” “abcd”).

VHDL Model Construction

A VHDL design describes a single system in a single file. The file has the suffix *.vhd. Within
the file, there are two parts that describe the system: the entity and the architecture. The entity
describes the interface to the system (i.e., the inputs and outputs) and the architecture describes
the behavior. The functionality of VHDL (e.g., operators, signal types, functions, etc.) is
defined in the package. Packages are grouped within a library. IEEE defines the base set of
functionalities for VHDL in the standard package. This package is contained within a library
called IEEE. The library and package inclusion are stated at the beginning of a VHDL file
before the entity and architecture. Additional functionality can be added to VHDL by including
other packages, but all packages are based on the core functionality defined in the standard
package. As a result, it is not necessary to explicitly state that a design is using the IEEE
standard package because it is inherent in the use of VHDL. All functionality described here is
for the IEEE standard package. Figure shows a graphical depiction of a VHDL file.

Libraries and Packages

As mentioned earlier, the IEEE standard package is implied when using VHDL; however, we
can use it as an example of how to include packages in VHDL. The keyword library is used to
signify that packages are going to be added to the VHDL design from the specified library. The
name of the library follows this keyword. To include a specific package from the library, a new
line is used with the keyword use followed by the package details. The package syntax has
three fields separated with a period. The first field is the library name. The second field is the
package name. The third field is the specific functionality of the package to be included. If all
functionality of a package is to be used, then the keyword all is used in the third field. Examples
of how to include some of the commonly used packages from the IEEE library are shown
below.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;

The Entity

The entity in VHDL describes the inputs and outputs of the system. These are called ports.
Each port needs to have its name, mode, and type specified. The name is user-defined. The
mode describes the direction data is transferred through the port and can take on values of in,
out, inout, and buffer. The type is one of the legal data types described above. Port names with
the same mode and type can be listed on the same line separated by commas. The definition of
an entity is given below.
entity entity_name is
port (port_name : <mode> <type>;
port_name : <mode> <type>);
end entity;

Example shows multiple approaches for defining an entity.

The Architecture

The architecture in VHDL describes the behavior of a system. There are numerous techniques
to describe behavior in VHDL that span multiple levels of abstraction. The architecture is
where the majority of the design work is conducted. The form of a generic architecture is given
below.
architecture architecture_name of <entity associated with> is
-- user-defined enumerated type declarations (optional)
-- signal declarations (optional)
-- constant declarations (optional)
-- component declarations (optional)
begin
-- behavioral description of the system goes here
end architecture;

Signal Declarations

A signal that is used for internal connections within a system is declared in the architecture.
Each signal must be declared with a type. The signal can only be used to make connections of
like types. A signal is declared with the keyword signal followed by a user-defined name, colon,
and the type. Signals of like type can be declared on the same line separated with a comma. All
of the legal data types described above can be used for signals. Signals represent wires within
the system so they do not have a direction or mode. Signals cannot have the same name as a
port in the system in which they reside. The syntax for a signal declaration is as follows:
signal name : <type>;
Example:
signal node1 : bit;
signal a1, b1 : integer;
signal Bus3 : bit_vector (15 downto 0);
signal C_int : integer range 0 to 255;
VHDL supports a hierarchical design approach. Signal names can be the same within a sub-
system as those at a higher level without conflict. Figure 2.2 shows an example of legal signal
naming in a hierarchical design.

Constant Declarations

A constant is useful for representing a quantity that will be used multiple times in the
architecture. The syntax for declaring a constant is as follows:

constant constant_name : <type> := <value>;

Example:

constant BUS_WIDTH : integer := 32;

Once declared, the constant name can now be used throughout the architecture. The following
example illustrates how we can use a constant to define the size of a vector. Notice that since
we defined the constant to be the actual width of the vector (i.e., 32-bits), we need to subtract
one from its value when defining the indices (i.e., 31 down to 0).
Example:
signal BUS_A : bit_vector (BUS_WIDTH-1 downto 0);
 Component Declarations
A component is the term used for a VHDL sub-system that is instantiated within a higher-level
system. If a component is going to be used within a system, it must be declared in the
architecture before the begin statement. The syntax for a component declaration is as follows:

component component_name
port (port_name : <mode> <type>;
port_name : <mode> <type>);
end component;

The port definitions of the component must match the port definitions of the sub-system’s
entity exactly. As such, these lines are typically copied directly from the lower-level systems
VHDL entity description. Once declared, a component can be instantiated after the begin
statement in the architecture as many times as needed.