Lab

1: Schematic Entry


Overview
In this task, you will use Custom Designer to draw an inverter gate, create the testbench for it, run
simulation with HSPICE and analyze the waveform using WaveView. Please follow the steps
exactly as specified.


Instructions

Login to your workstation, and open a Terminal.

Change to labs/Work1 directory

cd ~/labs/Work1


Invoke CustomDesigner console window:

cdesigner &

From the Custom Designer Console window, open the library manager, Tools -> Library
Manager.
Under the Libraries column, select the lab1 library and choose File -> New -> CellView.
Under Cell Name, enter: inverter
Choose Schematic as the View Name. The Editor will be automatically set to Schematic Editor.
Click OK. This will open up the schematic editor. We begin by adding instances (components) to
the schematic.

Add the pmos4t instance from SAED_PDK_90 library using the Add -> Instance command or by
clicking on the Add Instance button.

1) Select the library SAED_PDK_90

2) Select cell pmos4t
3) Choose View symbol
4) Move your mouse cursor on the
schematic canvas, and the pmos4t
symbol will be attached to your cursor,
place it as shown in the figure below.

The first transistor is named M0 by default. The Add Instance command remains active until
aborted (press the ESC key).

Repeat the above steps to place the nmos4t transistor slightly below the PMOS transistor. Press
Escape key to cancel the Add Instance operation. When done your schematic should like this:

Use the following icons on the toolbar to zoom and pan your schematic:

If you need to move any of the transistors, click on Edit -> Move or select the Move button and
then select the object you want to move. The selected object will move with your cursor. Try
moving the transistors around.

Next add wires to the schematic, click Add -> Wire or choose the add wire button

Draw the wires to the circuit using your mouse, see figure below for wire connections. To
deselect wire adding, press ESC. PMOS bulk to be connected to drain, while NMOS bulk to source.

Wire Connections


Now you need to give name to the wires. Choose Add -> Wire Name or click on

You will see a wire name space on the top of your schematic window to enter your wire name.
After typing the name, select a wire in the schematic to add the wire name to it.

See the figure below for all the wire names.

To add pins to the schematic, go to Add -> Pin or choose the Add Pin button, to add pins for the
input (VIN, AVDD, AVSS) and output (VOUT). Before placing the pins on to the schematic, choose
the pin type (input or output) in the Type box:


When completed your circuit should look like this:

Next we will modify the width of the transistors. For pmos4t, assign width of 0.5u and for
nmos4t, 0.25u. To assign the width, cancel any existing operation by pressing ESC. Select the
pmos4t transistor, and press Q key. This will bring up the Property Editor.

In the Property Editor box, select value for Width per Finger and change it to 0.5u and press
Enter to accept the change (you can also click the green check mark button on the Property
Editor toolbar).



Now select the nmos4t transistor, and change the Width per Finger to 0.25. Your schematic will
reflect the changes.

Check if there is anything wrong with your schematic by selecting Design -> Check and Save. If
there are errors (typically incomplete wiring), you will see the error location highlighted. Fix any
errors or ask instructor for help.

If there are no errors, you can proceed to generate a symbol for your inverter to be used in the
testbench or any other designs. Choose Design -> New CellView -> From CellView. Make sure
the information in the box matches the figure shown below, and click OK. This will create a
symbol view of the inverter.

Once you click Ok, the symbol view of the inverter will be generated and opened up in the
Symbol View Editor. Here you can change the shape of the symbol, location of pins etc. However
for this lab exercise, we will use the default symbol view settings. Click Design -> Close to close
the Symbol view. Then close the schematic view of the inverter.


Now we will create a testbench for the Inverter circuit and run simulation using HSPICE.

From the Custom Designer Console window, open the library manager, Tools -> Library
Manager.
Under the Libraries column, select the lab1 library, then choose File -> New -> CellView.

Under Cell Name, enter: inverter_tb
Choose Schematic as the View Name. The Editor will be automatically set to Schematic Editor.
Click OK. This will open up the schematic editor.

Place the instance of the inverter on the schematic. Go to Add -> Instance. In the Add Instance
window, select the library lab1, “inverter” as the cell and symbol for the view to select the
inverter you just made and place one instance of it on the schematic.

Then from the Add Instance window, select the analogLib, place vsource, vpulse and gnd. Use
the figure below for reference. Your actual reference name (V1, V2) may differ but that can be
ignored. In the diagram below, vpulse is V1, and vsource is V2.

Add wires to connect the voltage sources and ground to your inverter. See the figure below for
reference.

For VOUT, you can end the wire by
double clicking.
Name the two wires shown as VIN
and VOUT. There is no need to
rename rest of the wires, as they are
power lines.










Add an output pin to VOUT using the Add-> Pin command.

Then select the vsource, press Q to get the Property Editor, and change the DC voltage to 1.2 (no
need to add the unit V as its already included). Press Enter to accept the changes.

Next select vpulse, and in the Property Editor, add in the following (Press Enter after entering
each value):
Voltage1 = 0V
Voltage2 = 1.2V
Delay time = 100p
Rise time = 10p
Fall time = 10p
Pulse width = 2n
Period = 4n

Your circuit should now look something like this (except for the instance name of vsource and
vpulse which can differ):

Check if there is anything wrong with your schematic by selecting Design -> Check and Save. Fix
any errors if exist, or ask instructor for help.

We are now ready to simulate the design.


To begin simulation, select Tools -> SAE. The simulation and analysis environment (SAE)
window will appear. This is where you configure all simulation and analysis option.

First we will have to specify the SPICE models to be used for simulation of the two transistors.
The SPICE model library is SAED_PDK90nm/hspice/SAED90nm.lib.
Click Setup -> Model Files. Click the first line under the Model File column, and navigate to the
directory SAED_PDK90nm/hspice, and choose SAED90nm.lib and in the second column, under
section choose TT_12. See the figure below for reference (in the figure below, /home/user is the
home directory, your home directory might be different):

Select the library file first then only select the process corner


Click OK on the Model Files window to save your selections.

Next we will setup the Analysis. Choose Setup -> Analysis. Fill the data as shown below:

Click OK when done.



The inverter has two signals of interest, VIN (input) and VOUT (output). In the main SAE
window, there is section Output – this is where you specify which signals you want to view
automatically after you run the simulation.
Click under the Expression column, and click on


See the figure below for reference.



1) Click inside this box first









2) Then click on this icon



This is will take you back to the schematic view, select the WIRE labeled VOUT. You can now see
VOUT listed in the Expression column box.
Click the second row under the Expression column, and just like above, click

You will again go back to the schematic view, this time select the WIRE labeled VIN.
The signals listed under the expression column will be automatically displayed in the waveform
view upon completion of simulation.
The SAE window should look like this:

Now lets run the simulation. Select Simulation -> Netlist and Run.
You will see the Job monitor windows showing the status of the simulation run.



Wait until the Status changes to Finished. If the status shows “Failed”, ask the instructor for help.


After a short while, you will get the waveform viewer, Custom WaveView launching and
automatically loading the waveforms for the two signals we have monitored above (VIN and
VOUT). By default, both VIN and VOUT will be placed in the same window like this:

To view them separately (easier to debug), click on Panel -> Actions -> Ungroup. You can also
just select the two waveform signals in the left most column, Right Click and choose Ungroup.
Your window will look like this:






As we can see from the waveform window, VOUT is the inversion of VIN. This proves the design
is working correctly. If you want to save your waveform file, choose WaveView -> Dump
Screen.
In prompt, choose JPEG and enter a file name and directory. This will save the waveform as JPEG
file. This competes the simulation run.

Exit WaveView, File -> Exit.
Exit CD, by clicking on File -> Exit on the Console Window.
This completes lab1. Move on to next lab.

Lab 3: Custom Layout

Overview
In this task, you will use Custom Designer to draw an inverter gate layout. The layout will based
on the schematic of the inverter gate. Please follow the steps exactly as specified.

You will not fix any DRC violations in this lab. When dimensions are not given, draw based
on your best guess (or estimate). We will handle any resulting DRC violations in another
lab.

The steps to create a layout is as follows:


Define and Customize

Grids

Add Shapes


Edit Shapes


Create Interconnects


Create Pins


Create Labels


Create Cell Boundary



Instructions

Lets first open the schematic view of the Inverter. Launch Custom Designer from labs/Work1
directory:

cdesigner

Click on File -> Open Design. Select the library, lab3. Select the cell, inverter. Under the view
column, double click on schematic. This will launch the schematic editor.
(Similarly, you can open any other design view such as symbol or layout by simply double
clicking on the view).

The inverter design has 2 transistors – 1 PMOS (M0) and 1 NMOS (M1). You will draw the layout
for this gate. You will use this layout design in lab 4 and 5.

Create layout CellView for Cell inverter, from the Schematic editor window, select Design -> New
Select the library, lab3. Select the cell, inverter. Under the View Name column, Select layout.
Under the Editor column, Select Layout Editor. Click OK.


New Layout Editor (LE) windows opens.

To change display grids use Options > Design command.

Click on the Snapping & Grids tab in Layout Design Options window.

Change snap Grid Spacing value to 0.01 (Default is 0.005)
Select Gravity options under Snapping & Grids tab. Click OK to save changes

To enable the display of relative coordinates,
In LE window use Options > Display command.

Click on Cursor Tab. Check Dynamic Measurement, click Check None.

Enable DX/DY as shown in the figure above.
Click OK to save changes.

Select NWELL layer of purpose drawing from Object/Layer Panel.



Create rectangle for NWELL with the dimensions x=3.14um and y=2.005um using Create ->
Rectangle command or button from the left hand side then draw a rectangle on the LE
canvas.

Use Create -> Ruler command to help with the measurement. You can remove the ruler by
using Shift-K.



The NWELL rectangle is created as shown in the figure below:
 NWELL

The measurement shown is from
the ruler. Press Shift-K to remove them

Create diffusion areas for PMOS, NMOS and body connections. From the schematic of inverter, it
is known that the width of the PMOS should be 0.500u and the width of NMOS is 0.250u. The
length of both MOS is 1.3um. There are two vertical rectangles that will be the body connections.
Use the Create Rectangle command to draw the rectangles of type DIFF as shown below:

Body (x=0.46u, y=1.16u)

You can adjust the size later to meet DRC
requirements

Choose layer PIMP and draw rectangle sized x=1.75um, y=1.8um to cover the diffusion area as
shown in figure below:

PIMP is drawn to the edge of the NWELL where NWELL meets NIMP (which we will draw next)
Create rectangle with layer NIMP (green rectangle below) with size x=1.75um, y=1.32um and
place it as shown in figure below.

Body connections will have opposite implantation. Using Create->Rectangle, draw NIMP on the
upper body connection, and PIMP on the lower body connections.

NIMP (x=1.05u, y=1.8)

PIMP (x=1.05, y=1.32)

Choose layer PO (poly) and create gates with 0.1um width. Select Create->Path to draw the
strip of poly through PMOS and NMOS diffusion areas as shown in figure below. Create a
rectangle of type poly in the center of the poly strip (0.33ux0.345u), which will be used as input
signal.

Choose layer CO, to find this layer, type C in Filter line in Object/Layer Panel as shown below:

Create rectangle with the layer CO (contact) sized 0.13 by 0.13
Place it in layer DIFF as shown in following figure.

Create and place the remaining contacts of the same size as shown below. Maintain 0.13um
minimal distance between contacts. You can use Copy/Paste operation to place the contacts.

Choose layer M1, Select Create -> Path command, in Path toolbar that appears, specify the width
to be 0.16


Complete part of the circuit inverter layout as shown in Figure.




Width= 0.16u

0.33x0.985

Width=0.25




0.33 x 0.765

Width= 0.16



Select the M1PIN layer. Select Create->Text->Label place text labels labeled as AVDD, AVSS, VIN
and VOUT. Complete connections as shown in Figure


Match the label names in layout as the labeled pins in the schematic in order to pass LVS (Layout
vs Schematic)

Save your layout, click on Design -> Save.

You have now completed the layout drawing of an Inverter.
Close the Inverter design by selecting Design -> Close.

Move on to the next lab.


Lab 4: Design Rule Check (DRC)


Overview
In this lab, you will perform design rule check on a layout of an inverter gate. You will learn how
to run a design rule check on a layout, identify the source of the errors and fix the errors.

Instructions

Lets first open the layout view of the Inverter. Launch Custom Designer from labs/Work1
directory:

cdesigner

Click on File -> Open Design. Select the library, lab3. Select the cell, inverter_drc. Under the
view column, double click on layout. This will launch the layout editor.

Invoke the DRC setup window using Verification -> DRC -> Setup and Run command.

Home directory name

will vary depending on
your login name.

Some of the options are filled with default values:
Run Dir option is filled with <current working directory>/<cellname>.<pvtool>.drc value.
Layout section is filled with Library, Cell and View names parameters.

Under the Job Parameters section,
Make sure the Tools section is showing “IC Validator”.
Specify Runset file rules.drc.9m_saed90_icv.rs using the browse button from the directory:
SAED_PDK90nm/icv/drc

Enable Launch Debugger and View Output to open DRC errors results window automatically.
Press OK to start the run

When ICV job is completed, the status of ICV run and errors are displayed in the Text window as
shown in figure below:


Click on the “inverter_drc.LAYOUT_Errors” Tab, to see a list of DRC violations (scroll up to the
beginning).

After completing the run, you will get the following VUE window, which gives a summary of the
DRC run, and errors found:

Click on DRC Errors tab to view the errors. You might need to enlarge the window to have a
better view.
Under Layout Cells, select inverter_drc. DRC errors found in the inverter design are listed under
Violations column on the right. Select the first violtion, CO.E7, in Violations column as shown in
the following figure:





Under Violation Details column information about the violation is displayed.
When the rule is selected, the location of violation in the inverter cell is shown in the LE window
(See the figure below)

Clear the error highlights in the LE window using the Clear Error Highlights button in VUE.

Fix the error by resizing the Metal M1 so that the CONT is enclosed by M1. You can do this by
selecting the metal M1, then press Q to get the property window. Change the value of the metal
width to a higher number (0.25) in order for the metal to fully enclose the contact.

Select CO.W.1 contact rule. The violation is highlighted as shown

Clear the error highlight and resized the contact size to 0.13umx0.13um
Save the design.

Close ICV VUE windows and Custom Designer Text Viewer window. Re-run Hercules DRC using
Verification->DRC->Run.
(This command is used if there are no changes to the DRC Setup form.)

Click on the DRC Errors Tab in VUE window. Notice the number of DRC errors have been
reduced. You can continue to fix the remaining errors (optional) or proceed with this lab
exercise.

If there are no errors, you will not get the VUE window. The Custom Designer Text viewer will
appear. Click on the Inverter.LAYOUT_ERRORS tab, and you will get message show no DRC
violations like in the following figure:



Try running DRC on the inverter design from the library, sol. This is a DRC clean design.

Exit CD. Move on to the next lab.


Lab 5: Layout vs. Schematic (LVS)


Overview
In this lab, you will perform LVS checks on a layout of an inverter gate. You will learn how to run
a LVS checks on a layout, identify the source of the errors and fix the errors.

Notice that in order to pass LVS, schematic names and layout names must match one to one. Also
transistor dimensions for gate width and length in layout and schematic must match.

Instructions:

Lets first open the layout view of the Inverter. Launch Custom Designer from labs/Work1
directory:

cdesigner

Click on File -> Open Design. Select the library, lab5. Select the cell, inverter. Under the View
column, double click on layout. This will launch the layout editor.

Invoke the LVS setup window using Verification -> LVS -> Setup and Run command.

Default values for some of the options have already been filled. The Run Dir is filled with the
value <current working directory>/<cellname>.<pvtool>.lvs. The section Layout parameters
Library, Cell and View names are filled with the current active cellview. The Schematic
parameters Library, Cell names are filled with the current active Layout Editor cell, as this
window is invoked from layout. The View is set to schematic default.
Under Job Parameters section, select the file “rules.lvs.9m_saed90.rs” as the Runset File from
the following directory:
SAED_PDK90nm/icv/lvs/rules.lvs.9m_saed90.rs
Make sure that Launch Debugger and View Output is checked (by default, View Output is not
checked).

Click OK to run LVS checks.


Check console window for error and warning messages as shown below.


After completion of ICV LVS run and if there are LVS errors, you will get the VUE window
illustrated in the figure below (you will also get the schematic window, for now just move the
schematic window aside and look at the VUE window).

Click on LVS Errors tab:



Under Equivalence List blocks that fail and need debugging are listed under Unmatched.

Click on inverter_lvs::inverter_lvs and VUE window will have the view shown in Figure.

Click on 2 in the Matched ports with different text (2 records). The corresponding error will
be shown as in the figure below:



Click on AVDD/VDD an AVSS/VSS to see the errors highlighted in both the Schematic Editor and
Layout Editor. The errors are caused by mismatch in the power net names. Make active LE
window and rename VDD to AVDD and VSS to AVSS as is in schematic.

Save your design.
Close VUE & Custom Designer Text Viewer window. Rerun LVS using the command Verification
> LVS > Run.

If there are no other errors, VUE window will appear showing:

Exit CD. Proceed to the next lab.


Lab 6: Parasitic Extraction


Overview
In this lab, you will perform RC (parasitic) extraction on a layout of an inverter gate.

Instructions:
Let’s first open the layout view of the Inverter. Launch Custom Designer from labs/Work1
directory:

cdesigner

Click on File -> Open Design. Select the library, lab6. Select the cell, inverter. Under the View
column, double click on layout. This will launch the layout editor.

To be able to run parasitic extraction, your design must first pass LVS.
Invoke the LVS setup window using Verification -> LVS -> Setup and Run command. Make sure
“Launch Debugger” and “View Output” is checked. The VUE window should come up and shows
the status as “PASS”.

Close the VUE and Schematic Editor window. You will be working on the Layout Window for
now.

Click on Verification -> LPE -> Setup and Run. The follow window will appear:

Make sure the View Output and Open Parasitic View are checked. Click on the Extraction
Options tab.




Click on the folder icon beside the Runset Report File, and select the file, pex_runset_report,
from the directory: labs/Work1/pvjob_lab6.inverter.icv.lvs/

Switch to the Output Options tab. Set the format as OA as shown in the figure below:

Click OK. This will start the extraction process which will take a while. Look at the output log
while the extraction is going on. Once done, you will get a new layout window showing the
parasitic annotated onto the layout. See figure below.


Try zooming in to see the parasitic annotation. Once done close all the layout window. Bring up
the Library Manager window. Click on File – Refresh. You will now see a new view for the cell
Inverter called starrc. This is the parasitic information in OA format. You can use this parasitic
information to back annotate on to your schematic to perform a much more accurate simulation.

In the Library Manager window, under the Cells, select inverter_tb and under View, double-
click on schematic to open the inverter testbench schematic, inverter_tb. This is the same
testbench that was used in lab 1 (see figure below). Close the schematic window.

Now the parasitics need to be loaded into the inverter cell used in the circuit. From the Custom
Designer Console window, go to File -> New -> CellView.

In the New CellView window, create a new configurations file as follows:
Select lab6
Select inverter_tb for the cell.
Set view name to config (The editor should be set to Hierarchy Editor)
See the figure below for reference:

Click on OK. This will create a new config view for the testbench, and launch the Hierarchy
Editor window:

Key in the information as shown in the figure below:

Set the following:
- View to schematic
- Search list to schematic hspice symbol
- Stop list to symbol

Once you key in the above information, the window information will be updated automatically as
shown below:

Under the Selected column for the line highlighted above, select the option starrc, as shown
below:

Select starrc


Click on the Save icon
When done, your hierarchy editor should look like this:









Click on Open Configured
Design icon. This will lauch
the schematic editor of the
testbench.















The Schematic Editor should come up with the same testbench as before loaded in. Double click
on the Inverter symbol. Instead of getting the schematic of the inverter, you now will get the
layout view of the inverter with the parasitic annotated in. When you run the simulation, Custom
Designer will use the back-annotation data for simulation together with your inverter netlist.
Click on the Return to Top toolbar icon to go back to the testbench schematic view:

To run the simulation, choose Tools –> SAE. Load the pre-configured Open Access state, Session
-> Load State. Set the state as sim_ready, and click OK. (See figure below)

Under Setup -> Model Files, choose the model file, SAED90n .lib from the directory
SAED_PDK90nm/hspice. Set the corner (Section) as TT12.

Run the simulation; click Simulation -> Netlist and Run. The Job monitor (shown below) will
appear indicating the status of the simulation.

Wait until the Status changes to FINISHED. Status FINISHED indicates the simulation completed
successfully. If you get status failed, check the model file setting in Setup -> Model Files.

After simulation finishes, the waveform window will appear in short while with the INPUT and
OUTPUT signal loaded in. Inspect the signals and verify the functionality is still correct.

Exit the Custom Design tool, by clicking on File -> Exit in the console window.

This completes lab session. Thank you.