Implementation of SHA-1 Algorithm, Using Verilog
Implementation of SHA-1 Algorithm, Using Verilog
using Verilog
Ankit Varshney Anand Mahesh Kumar
Electronics and Communications Engineering Electronics and
MIT, Manipal Communications
Engineering
MIT, Manipal
e. Let,
5. Computing the Message Digest H0 = H0 + A,
H1 = H1 + B,
Method H2 = H2 + C,
The message we padded during the padding process will H3 = H3 + D,
be used to get the block. A buffer has the 5 words labelled
as A, B, C, D, E. Another buffer has the 5 words labelled as H4 = H4 + E.
H1, H2, H3, H4, H0. The words of our 80-word sequence
On completing the processing of the padded message we
obtain the aforementioned variables (H0 - H4). These four
variables are concatenated as
H = H0 H1 H2 H3 H4
The variable ‘H’ thus obtained contains the final 160-bit
message that is known as the SHA1 Encoded Message of
the input message M(i).
III. APPLICATIONS
This entire algorithm could be implemented as a SOC. This
SOC has a wide range of applications including, Electronic
Lockers, Car Sharing Applications, Password storage and
Verification, Enabling secure data transfer, secure telephony
and video communications.
IV. CONCLUSION
The entire algorithm was tested using the simulation tool
Vivado. This thus proves that the algorithm can be run on
the appropriate FPGA for further testing and be made into a
SOC that can be used for a wide variety of applications as
mentioned in this report.
V. REFERENCES
[1]https://www.ipa.go.jp/security/rfc/RFC3174EN.htm
[2] https://brlliant.org/wiki/secure-hashing-algorithms/
[3] https://www.forrestheller.com/
[4] http://www.sha1-online.com/