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VHDL - Final Exam Instructions:: Department of Computer Engineering - VHDL First Semester, Sy 2019 - 2020

This document provides instructions for a VHDL final exam project to create a timer for a cubing game using a FPGA board. Students must work individually, are allowed additional hardware, and must provide documentation. The deadline is October 15 with no extensions. The timer must have power and reset switches, display time on 7-segment displays, and start/stop timing when both sensors are pressed. It also needs save and previous buttons to record and recall times. A real-time clock must be used and the timer will be tested by classmates for full functionality.

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Paula louise Flores
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52 views1 page

VHDL - Final Exam Instructions:: Department of Computer Engineering - VHDL First Semester, Sy 2019 - 2020

This document provides instructions for a VHDL final exam project to create a timer for a cubing game using a FPGA board. Students must work individually, are allowed additional hardware, and must provide documentation. The deadline is October 15 with no extensions. The timer must have power and reset switches, display time on 7-segment displays, and start/stop timing when both sensors are pressed. It also needs save and previous buttons to record and recall times. A real-time clock must be used and the timer will be tested by classmates for full functionality.

Uploaded by

Paula louise Flores
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL – FINAL EXAM

Instructions:

1. This is an individual work.


2. The use of additional hardware is allowed.
3. Provide a documentation.
4. Deadline will be on October 15. STRICTLY NO EXTENSIONS
5. Use a modular approach in your coding. Use behavioral structure.

CUBE TIMER/STOPWATCH

Create a timer for a cubing game or similar; for example, solving a rubiks cube. The timer should have
two touch sensors or any hardware substitute, a seven-segment displays, switches and LEDs. The timer is
programmed in VHDL and loaded to a FPGA board. The timer should work under the following circumstances;

The timer should have a power SWITCH.

If the power switch is OFF the timer should not function or every hardware must be disabled or turned

off.

If the timer switch is ON;

seven-segment displays should display zeros;

both sensors/hardware should be touched/pressed to enable start of timing/counting up;

two LED are use to indicate that sensors/hardware are touched/pressed, one for the left side and

one for the right side;

a RESET button is included to restart the time display of the seven-segment to zeros’

a SAVE button is included to save the time recording displayed;

a PREVIOUS button is included to recall the save time recordings, the display should start from
the recent save recordings. Use a button to navigate the recordings.

NOTE: A real-time clock should be use on your project.

To test or to check your work, an actual game is initiated and be used by your classmate. This exam is in reference
on how a speed stack timer works. See videos.

The rating will be perfect or zero, there are no in-betweens rating. You will be rated based on the required full
functionality of the project.

ACKNOWLEDGEMENT

_________________________ _________________________________________________________

DATE SIGNATURE OVER PRINTED NAME

DEPARTMENT OF COMPUTER ENGINEERING | VHDL First Semester, SY 2019 - 2020

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