UNISONIC TECHNOLOGIES CO.
, LTD
TEA2025D LINEAR INTEGRATED CIRCUIT
STEREO AUDIO AMPLIFIER
DESCRIPTION
The UTC TEA2025D is a monolithic integrated circuit that
intended for use as dual or bridge power audio amplifier portable
radio cassette players.
SOP-20
FEATURES
* Dual or bridge connection modes.
* Few external components.
* Supply voltage down to 3V.
* High channel separation.
* Very low switch on\off noise. *Pb-free plating product number: TEA2025DL
* Max gain of 45dB with adjust external resistor.
* Soft clipping.
* Thermal protection.
* 3V<VCC<15V
* P=2*1W,VCC=6V,RL=4Ω
* P=2*2.3W,VCC=9V,RL=4Ω
* P=2*0.1W,VCC=3V,RL=4Ω
■ ORDERING INFORMATION
Order Number
Package Packing
Normal Lead Free Plating
TEA2025D-S20-R TEA2025DL-S20-R SOP-20 Tape Reel
TEA2025D-S20-T TEA2025DL-S20-T SOP-20 Tube
TEA2025DL-S20-R
(1)Packing Type (1) R: Tape Reel, T: Tube
(2)Package Type (2) S20: SOP-20
(3)Lead Plating (3) L: Lead Free Plating, Blank: Pb/Sn
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TEA2025D LINEAR INTEGRATED CIRCUIT
■ PIN CONFIGURATION
BRIDGE 1 20 Vcc
OUT2 2 19 OUT1
BOOT2 3 18 BOOT1
GND 4 17 GND
GND 5 16 GND
GND 6 15 GND
GND 7 14 GND
FEEDBACK FEEDBACK
8 13
IN 2(+) 9 12 IN 1(+)
SVR 10 11 GND(Sub)
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TEA2025D LINEAR INTEGRATED CIRCUIT
■ BLOCK DIAGRAM
GND(Sub ) IN 1+ FEED GND GND BOOT 1 OUT1
50Ω 10kΩ
THERMAL
PROTECT
-
1 1
+
START
CIRCUIT 5kΩ
SVR DECOUPLING Vss +
BRIDGE
IN 2+ -
2 2 50Ω
+
10kΩ
50Ω
FEED GND GND BOOT 2 OUT2
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TEA2025D LINEAR INTEGRATED CIRCUIT
■ ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage VSS 15 V
Output Peak Current IO(PEAK) 1.5 A
Junction Temperature TJ 150 °C
Storage Temperature TSTG 150 °C
Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
■ THERMAL DATA
PARAMETER SYMBOL RATINGS UNIT
Thermal Resistance Junction-case θJC 15 °C/W
Thermal Resistance Junction-ambient θJA 65 °C/W
Note: The θJA is measured with 4 cm2 copper area heatsink.
■ ELECTRICAL CHARACTERISTICS (Ta=25°C, VCC=9V, Stereo unless otherwise specified)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Supply Voltage VSS 3 12 V
Quiescent Current IQ 35 50 mA
Quiescent Output Voltage VOUT 4.5 V
Stereo 43 45 47 dB
Voltage Gain GV
Bridge 49 51 53 dB
Voltage Gain Difference ∆GV(DIFF) ±1 dB
Input Impedance RI 30 kΩ
RL=4Ω 0.1
VSS=3V
RL=32Ω 0.02
RL=4Ω 0.7 1
RL=8Ω 0.6
VSS=6V
RL=16Ω POUT Stereo 8 (per channel) 0.25
RL=32Ω 0.13
RL=4Ω 1.7 2.3
Output Power (d=10%) VSS=9V W
RL=8Ω 1.3
RL=8Ω VSS=12V 2.4
RL=16Ω 0.18
VSS=3V
RL=32Ω 0.06
RL=4Ω POUT Bridge 2.8
VSS=6V
RL=8Ω 1.5
RL=8Ω VSS=9V 4.7
Stereo 0.3 1.5 %
Distortion d VSS=9V; RL=4Ω
Bridge 0.5 %
Supply Voltage Rejection SVR f=100Hz,VR=0.5V,Rg=0 40 46 dB
Rg=0 1.5 3 mV
Input Noise Voltage eN(IN)
Rg=104Ω 3 6 mV
Cross-Talk CT f=1KHz, Rg=10KΩ 40 52 dB
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TEA2025D LINEAR INTEGRATED CIRCUIT
■ APPLICATION INFORMATION
Input Capacitor
Input capacitor is PNP type allowing source to be referenced to ground.
In this way no input coupling capacitor is required. However, a series capacitor(0.22µF) to the input side can be
useful in case of noise due to variable resistor contact.
Bootstrap
The bootstrap connection allows to increase the output swing.
The suggested value for the bootstrap capacitors (100µF) avoids a reduction of the output signal also at low
frequencies and low supply voltage.
Voltage Gain Adjust
STEREO MODE
The voltage gain is determined by on-chip resistors R1 and R2 together with the external RfC1 series connected
between pin 8(13) and ground. The frequency response is given approximated by:
VOUT R1
= 1
VIN Rf +R2+ JWC1
With Rf=0,C1=100µF, the gain results 46dB with pole at f=32Hz
The purpose of RfI is to reduce the gain. It is recommended to not reduce it under 36dB.
BRIDGE MODE
Figure 7
8(13) R2
2(19)
50 R1
Rf
C1 10K
The bridge configuration is realized very easily thanks to an internal voltage divider which provides (at pin 1)the CH1
output signal after reduction. It is enough to connect pin8(inverting input of CH 2 )with a capacitor to pin 1 and to
connect to ground the pin 9.
The total gain of the bridge is given by:
VOUT R1 R3 R1
VIN
= 1 (1+ R4 1 )
Rf +R2+ JWC1 R2+R4+ JWC1
and with the suggested values (C1=C2=100µF,Rf=0)means:
Gv=52dB
Figure 8
IN
OUT OUT
R1 R1
10K 10K R3
R2 R2 5K
R4
50
With first pole at f=32Hz
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TEA2025D LINEAR INTEGRATED CIRCUIT
■ APPLICATION INFORMATION(Cont.)
Output Capacitors.
The low cut off frequency due to output capacitor depending on the load is given by:
1
FL =
2πCOUT *RL
With COUT 470µF and RL=4 ohm it means FL=80Hz.
Stability
A good layout is recommended in order to avoid oscillations. In general, the designer must pay attention on the
following points:
-Short wires of components and short connections.
-No ground loops.
-Bypass of supply voltage with capacitors as nearest as possible to the supply I.C. pin. The low value (polyester)
capacitors must have good temperature and frequency characteristics.
-No sockets.
The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There is no device
damage in the case of excessive junction temperature: all that happens is that POUT (and therefore PD) and Id are
reduced.
APPLICATION SUGGESTION
The recommended values of the components are those shown on stereo application circuit of Fig.2 different values
can be used, the following table can help the designer.
Larger
Component Recommended Purpose Smaller Than
Than
Input DC Decoupling in Case of
C1,C2 0.22µF Slider Contact Noise of Variable
Resistor
Degradation of SVR, Increase of THD at
C3 100µF Ripple Rejection
Low Frequency and Low Voltage
C4,C5 100µF Bootstrap
C6,C7 470µF Output DC Decoupling Increase of Low Frequency Cut-off
C8,C9 0.15µF Frequency Stability Danger of Oscillations
C10,C11 100µF Inverting Input DC Decoupling Increase of Low Frequency Cut-off
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TEA2025D LINEAR INTEGRATED CIRCUIT
■ TYPICAL APPLICATION CIRCUIT
Figure 1:Bridge Application(Powerdip) Figure 2:Stereo Application (Powerdip)
+V 8 +V 8
100 µF 100 µF
0 .22 µF C1
C4
0 .22 µF
IN 12 20 100 µF IN.1 12 20 100 µF
13 18 13 18 C6
100 C10 470µF
100µF OUT.1
µF 19 19
9 C8
TEA 0 .15 µF TEA 0 .15 µF RL
2025 D RL C2 0 .22 µF
8 IN.2 9 2025 D
3 3
100µF C5 C7
100µF 8 100µF 470 µF
1 2 C11
100 OUT.2
µF 2
10 4,5 ,6,7,11, 0 .15 µF 10 4,5,6 ,7,11, C9 RL
14,15,16,17 14 ,15 ,16 ,17 0 .15 µF
100µF C3
100µF
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TEA2025D LINEAR INTEGRATED CIRCUIT
■ TYPICAL CHARACTERISTICS
Supply Current vs.Supply Voltage
(RL=4Ω) Output Voltage vs. Supply Voltage
I(mA) VOUT(V)
50 8
40 6
5
30 4
3
20 2
STEREO STEREO
1
10 0
3 6 9 12 15 3 6 9 12 15
Vss(V) Vss(V)
Output Power vs. Supply Voltage THD vs. Output Power
(THD=10%,f=1KHz) (f=1KHz,Vss=6V)
PoUT(W) THD(%)
3.5 10
3 RI=8Ω
RI=8Ω
RI=16Ω
2.5 RI=4Ω
RI=4Ω
2
1
1.5
1 RI=16Ω
0.5 STEREO
STEREO
0 0.1
3 6 9 12 15 0 0.2 0.4 0.6 0.8 1
Vss(V) PoUT(W)
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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