Scribd
Upload
63 views3 pages

Verilog Code

This Verilog code defines a module that implements a binary coded decimal (BCD) counter with 3 bits. It contains registers to store the present and next states, which are defined by parameters representing the state codes. The always blocks handle the state transition on each clock edge and set the output according to the current state and input. The case statement determines the next state and output value based on the current state and input bit.

Uploaded by

keerthu raj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
63 views3 pages

Verilog Code

This Verilog code defines a module that implements a binary coded decimal (BCD) counter with 3 bits. It contains registers to store the present and next states, which are defined by parameters representing the state codes. The always blocks handle the state transition on each clock edge and set the output according to the current state and input. The case statement determines the next state and output value based on the current state and input bit.

Uploaded by

keerthu raj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

Verilog code:

module bcd_3(out,bi,clk,rst);

output out;

input bi,clk,rst;

parameter s0=3'b000,s1=3'b001,s2=3'b101,s3=3'b111,s4=3'b011,s5=3'b110,s6=3'b010;// states

reg [2:0] pst,nst;//present state ,next state

reg out;

always @(posedge clk or negedge rst)

if(rst==0)

pst<=s0;

else

pst<=nst;

always @(pst or bi)

begin

out=0;

case(pst)

s0:if(bi==0)

begin

nst=s1;

out=1;

end

else

nst=s2;

s1:if(bi==0)

begin
nst=s3;

out=1;

end

else

nst=s4;

s2:begin

nst=s4;

out=bi;

end

s3:begin

nst=s5;

out=bi;

end

s4:if(bi==0)

begin

nst=s5;

out=1;

end

else

nst=s6;

s5:begin

nst=s0;

out=1;

end

s6:begin
nst=s0;

out=1;

end

endcase

end

endmodule

output:

You might also like