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INTRODUCTION TO LATCH & FLIP-FLOP

LATCH
•  S-R Latch
•  Gated S-R Latch
•  Gated D Latch

FLIP-FLOPS
•  Edge-Triggered D Flip-Flop
•  S-R Flip-Flop
•  J-K Flip-Flop
•  T Flip-Flop

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FACULTY OF COMPUTER SCIENCE & INFORMATION SYSTEM 2

Combinational Logic Circuit:

Introduction to Latch & Flip-Flop

•  The output depend on the input

•  It has no memory element
•  Therefore it cannot memorize the previous output

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Sequential Logic Circuit:

Sequential Logic Circuit:

Event Driven Clock Driven Pulse Driven

(Asynchronous) (Synchronous)

•  It has memory element Cyclic Non-Cyclic

•  The output depend on the input, as well as the previous output
from the feedback elements

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Latch Flip-Flop

•  Latch is a type of temporary storage device LOW HIGH •  Flip-flop (FF) are synchronous bi-stable storage devices
capable of storing one bit, where the output state only
•  It has two stable states (bi-stable). changes at a specified point on a triggering input called the
INFO :
Clock (C).
A bi-stable
state is one •  So FF are edge-triggered, means that the output changes
with two-stable are synchronized with the Clock signal.
•  Latch is level sensitive, or level-triggered.
output states.
–  are dependent on the voltage level •  This may either be a LOW-to-HIGH (rising edge) or a HIGH-to-
applied , not on any signal transition. LOW (falling edge) transition.

•  Type of Flip-Flop:
•  Type of Latch : S à  Set INFO :
i) D Rising edge = positive edge
i) S-R
R à  Reset ii) S-R Falling edge = negative edge
ii) Gated S-R
D à  Data iii) J-K
iii) Gated D J K à Two control inputs
iv) T
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Difference:
Latch vs Flip-Flop

Latch Set

Reset

•  Set is HIGH, Reset is LOW à Q will be HIGH •  Set à means that Q output is HIGH
•  Set is LOW, Reset is HIGH à Q will be LOW •  Reset à means that Q output is LOW

Flip-flop Set

Reset

Clock
Jam

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S-R Latch

•  The output of each gate is connected to an input of the

opposite data.
•  This produces a regenerative feedback.

Latches

i) S-R
ii) Gated S-R
iii) Gated D
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S-R Latch: Logic symbol

Active-HIGH Active-LOW

INPUTS OUTPUTS INPUTS OUTPUTS

COMMENTS COMMENTS
S R Q Q S R Q Q
No change. Latch remains in
0 0 NC NC 0 0 1 1 Invalid condition
present state

0 1 0 1 Latch RESET 0 1 1 0 Latch SET

1 0 1 0 Latch SET 1 0 0 1 Latch RESET

No change. Latch remains in

1 1 0 0 Invalid condition 1 1 NC NC present state

Explanation :
§  The Q and not-Q outputs are supposed to be in opposite states.
§  Q=1 and not-Q=0 is defined as Set (by making S=1 and R=0)
§  Q=0 and not-Q=1 is conversely defined as Reset
(by making S=0 and R=1)
§  When S and R are both equal to 0, the multivibrator's outputs
“Not Change” in their prior states.
§  If Q and not-Q happen to be forced to the same state
(both 0 or both 1), that state is referred to as invalid.
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Example: S-R Latch (Active HIGH)

Explaination:

continue...
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Ex
tr
a Gated S-R Latch

Exercise 7.1: If the S and R waveform in (a) are applied to the •  Is a gated latch requires an enable input (EN).
inputs of latch (active-LOW), determine the
waveform that will be observed on the Q output in •  The S and R inputs control the state to which the latch
(b). Assume that Q is initially LOW. will go when a HIGH level is applied to the EN input.
•  The latch will not change until EN is HIGH, but as long as
it remains HIGH, the output is controlled by the state of
the S and R input.

•  The invalid state occurs when both S and R are

simultaneously HIGH. INFO :
EN = 1, Latch is On
EN = 0, Latch is Off

Resource: Floyd, Digital Fundamentals, 10th Edition 17 18

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Gated S-R Latch: Truth Table

EN S R Output
0 0 0 No Change
0 0 1 No Change
0 1 0 No Change
S-R Latch
(Active LOW) 0 1 1 No Change
1 0EN 0S R ChangeOutput
No
Y = Z =1 1 00 0/1
1 0/1 Q=0 No Change
Y = (S ⋅ EN ) Z = (R ⋅ EN ) 1 11 00 0 Q=1 No Change
1 11 10 1 Invalid Q=0
1 1 0 Q=1
1 1 1 Invalid
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Example: Gated S-R Latch. Example: Gated S-R Latch.

Find the waveform for Q. Assume that Find the waveform for Q. Assume that Q is
Q is initially LOW. initially LOW.
S

EN

Q
Resource: Floyd, Digital Fundamentals, 10th Edition 21 22

Example: Gated S-R Latch.

Find the waveform for Q. Assume
Exercise 7.2:
that Q is initially LOW.

EN

Q
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Gated D Latch:
Logic diagram & logic symbol
Gated D Latch

Gated D Latch:
Truth Table
EN D Output
0 0 No Change
0 1 No Change
1 0 Q=0
1 1 Q=1

S-R Latch INFO :

EN = 1, Latch is On
Gated S-R Latch EN = 0, Latch is Off
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Example: Gated D Latch.

Find the waveform for Q. Assume that
Q is initially LOW.

Condition 1: D = 0, therefore S = 0, R = 1 which make Q = 0

Condition 2: D = 1, therefore S = 1, R = 0 which make Q = 1

EN=1  Q=D

27 Resource: Floyd, Digital Fundamentals, 10th Edition 28

Solution:

Flip-Flops

i) Edge-Triggered D
ii) S-R
iii) J-K
iv) T (Toggle)
Resource: Floyd, Digital Fundamentals, 10th Edition 29 30

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EN / CLK

(Positive
edge- Gated
triggered) Latch Q

Flip-flop
Q
(Negative
edge-
triggered)

Level-triggered EN
edge-triggered CLK
Figure : Edge-Triggered FF logic symbol
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S-R Flip-Flop

S R CLK Output Comments

Q Q TRUTH TABLE
0 0 Q0 Q0 No Change = clock transition LOW
RESET to HIGH
0 1 0 1 Q0= output level prior to
1 0 1 0 SET clock transition

1 1 ? ? Invalid

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Example: S-R Flip-Flop.

Find the waveform for Q and Q.
Assume that the the positive edge-triggered
flip-flop is initially RESET.

35 Resource: Floyd, Digital Fundamentals, 10th Edition 36

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Solution:
Once Q is
determined, Q’
is easily found
since it is simply
the complement
Clock S R Q of Q.
Pulse
1 LOW LOW Does not change
2 LOW HIGH LOW (RESET)
3 HIGH LOW HIGH (SET)
4 LOW HIGH LOW (RESET)
5 HIGH LOW HIGH (SET)
6 HIGH LOW Stay HIGH
Resource: Floyd, Digital Fundamentals, 10th Edition 37 38

D Flip-Flop

D  Data or Delay

§  D FF is useful when a single data bit (1 or 0) is to be stored.

§  The addition of an inverter to an S-R FF creates basic D FF (for positive edge-triggered)
where a positive edge-triggered type is shown.

Remember, Q follows D at the active or triggering clock edge.

39 Resource: Floyd, Digital Fundamentals, 10th Edition 40

J-K Flip-Flop

TRUTH TABLE
§  The JK FF is versatile and is a widely used type
of FF. = clock transition LOW
to HIGH
§  The difference between J-K and S-R: Q0= output level prior to
clock transition
J-K has no invalid state as SR. Positive or
negative
triggered ?

Logic Symbol
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Positive or Positive
Example: J-K Flip-Flop. negative triggered
Find the waveform for Q. triggered?
Assume that Q is initially LOW. Solution:

Resource: Floyd, Digital Fundamentals, 10th Edition 43 44

Positive or negative
Example: J-K Flip-Flop. negative triggered
Find the waveform for Q. triggered? Solution:
Assume that Q is initially LOW.

Resource: Floyd, Digital Fundamentals, 10th Edition 45 Resource: Floyd, Digital Fundamentals, 10th Edition 46

T Flip-Flop

Timing
Diagram for
§  Also called as toggle flip flop. T Flip-Flop
(Negative-
§  Frequently used in building counters Edge
Trigger)

T J T

Logic Symbol

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Priority FF Input
Highest PRE, CLR (Asynchronous input)
Medium Clock
Lowest S-R, J-K, D, T (Synchronous input)

Preset PRE or direct SET

Clear CLR or direct RESET

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HIGH

Example: J-K Flip-Flop.

Find the waveform for Q.
Assume that Q is initially LOW.
Q

clk
pulse
PRE CLR J K FF Comment

1,2,3 0 11 1 1 SET JK inputs - dont care

4,5,6,
1 1 1 1 Toggle Synchronous mode.
7
8,9 1
1 0 1 1 RESET JK inputs - dont care

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HIGH

Positive or Positive
Exercise 7.3: PRE and CLR negative triggered
triggered?
Find the waveform for Q.
Assume that Q is initially LOW.
Solution:

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Ex Extra notes :
tr
a Master Slave Flip Flops (JK Example)
Positive or
Exercise 7.4: PRE and CLR negative
Find the waveform for Q. triggered?
Assume that Q is initially HIGH.

There are 2 sections called as :

Master section - a) External JK input, b) A gated latch

Slave section - a) Inputs = outputs of Master, b) Inverted clock pulse
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