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FALLSEM2019-20 EEE4024 TH VL2019201001067 Reference Material I 02-Aug-2019 Computer Arithmetic

The document describes several algorithms for performing arithmetic operations in computers, including addition, subtraction, multiplication, and division. Addition and subtraction are performed using sign-magnitude representation by comparing sign bits, taking 2's complements as needed, and propagating carries. Multiplication algorithms include shifting partial products and accumulating the results, with optimizations like Booth recoding. Division methods include restoring and non-restoring approaches. The arithmetic logic unit (ALU) performs these operations using combinational or sequential logic. Floating point involves aligning numbers by their exponents before operations and renormalizing the results.

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118 views45 pages

FALLSEM2019-20 EEE4024 TH VL2019201001067 Reference Material I 02-Aug-2019 Computer Arithmetic

The document describes several algorithms for performing arithmetic operations in computers, including addition, subtraction, multiplication, and division. Addition and subtraction are performed using sign-magnitude representation by comparing sign bits, taking 2's complements as needed, and propagating carries. Multiplication algorithms include shifting partial products and accumulating the results, with optimizations like Booth recoding. Division methods include restoring and non-restoring approaches. The arithmetic logic unit (ALU) performs these operations using combinational or sequential logic. Floating point involves aligning numbers by their exponents before operations and renormalizing the results.

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kripa
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Computer Arithmetic

Marimuthu R
Addition/Subtraction Using Sign–Magnitude
Complementer
Algorithm - Addition
➢Magnitude & sign bit of Augend are loaded in register “A” and “As” respectively.
➢Magnitude & sign bit of Addend are loaded in register “B” and “Bs” respectively.
➢Compare the sign bit by performing EXOR. i.e As ⊕ Bs
➢If the sign bit is zero, perform addition (A+B) and transfer carry (E) bit to
overflow (AVF). Register “A” and sign bit “As” holds the result.
➢If the sign bit is one, take 2’s complement of B and add with A. i.e (A+~B+1)
and clear overflow bit.
➢When you get carry from 2’s complement:
➢ ignore the carry and the answer is positive. (A>=B)
➢ Clear As bit and the register A holds the result.

➢When you don’t get carry from 2’s complement:


➢ Take a 2’s complement of A. (A = ~A+1)
➢ Invert the sign bit (“As”) register “A” & “As” holds the result.
Algorithm - Subtraction
➢Magnitude & sign bit of Minuend are loaded in register “A” and “As” respectively.
➢Magnitude & sign bit of Subtrahend are loaded in register “B” and “Bs”
respectively.
➢Compare the sign bit by performing EXOR. i.e As ⊕ Bs
➢If the sign bit is one, perform addition (A+B) and transfer carry (E) bit to
overflow (AVF). Register “A” and sign bit “As” holds the result.
➢If the sign bit is zero, take 2’s complement of B and add with A. i.e (A+~B+1)
and clear overflow bit.
➢When you get carry from 2’s complement:
➢ ignore the carry and the answer is positive. (A>=B)
➢ Clear As bit and the register A holds the result.
➢When you don’t get carry from 2’s complement:
➢ Take a 2’s complement of A. (A = ~A+1)
➢ Invert the sign bit (“As”) register “A” & “As” holds the result.
Flowchart
Example
1. (+12)+(+06)
2. (+72)+(-68)
3. (-120)-(-89)
4. (+222)-(+187)
Addition/Subtraction – 2’s Complement
Flow Chart
Multiplication
Multiplication is performed in different manner in computer. They are:

1. Instead of providing registers to store and add simultaneously, it is


convenient to provide an adder for the summation of two numbers.
2. Instead of shifting left, the partial product is shifted right. This avoid
the complexity in the resulting register.
3. Also, when corresponding bit of multiplier is 0, there is no need to
add all zeros to the partial product.
Multiplication
Algorithm
1. Load multiplicand in register “B” and multiplier in register “Q”. Also,
load corresponding sign bits in “Bs” and “Qs” respectively.
2. XOR between “Bs” & “Qs” provide the sign bit of the result which is
stored in “As” & “Qs”.
3. Initialize “E”, register “A” to zero.
4. Load “n-1” value (n= number of multiplier bits) in Sequence
Counter (SC).
5. Check “Qn” (LSB of register Q), if the bit is “1”, perform A +B, shift
right the EAQ and subtract “SC” value by 1.
6. If “Qn” is zero, shift right the EAQ and subtract “SC” value by 1.
7. Repeat step 5 or 6 until “SC” value becomes zero.
Flow Chart
Example

(a) 23 x 19
(b) 120 x 24
(c) -22 x 18
(d) -15 x -22
Booth Algorithm
• Applicable for both +ve and –ve numbers (2’s complement).
• Recoded the multiplier bits.
• It helps to reduce the number of additions in the multiplier.
(Approximately n/2 times) where n is number of bits in the multiplier.
• It operates on the fact that strings of 0’s in the multiplier require no
addition but arithmetic shifting is required.
• String of 1’s in the multiplier from bit weight 2i+n-1 to 2i can be treated
as 2i+n – 2i (For +ve numbers).
• Ex, 01111 (15 in decimal) is recoded as 24 – 20 = 15.
• For negative numbers, the recoding formula is -2i
Booth Algorithm
Booth Recoding: It is based on LSB of multiplier bit (Qn) and an
imaginary bit (Qn+1) and it’s initially assumed as zero. (QnQn+1)

➢If both the 00 or 11: No addition or subtraction is required. Only


arithmetic shift right is required.
➢If the bits are 10: 2’s complement of multiplicand is added with
register A.
➢If the bits are 01: Add multiplicand value with register A.
Booth Multiplier – Hardware Details
Flow Chart
Example

56 x 34
-178 x 88
-12 x -24
Modified Booth Recoding
Also called “Bit Pair Recoding”
Procedure:
➢Group the Booth recoded multiplier bits in pairs.
➢Fast multiplication algorithm when compare to Booth.
➢ Applicable for even number of bits.
Ex: (Worst Case Booth Multiplier)
0 1 0 1 0 1 0 1 0 1
+1 -1 +1 -1 +1 -1 +1 -1 +1 -1
Modified Booth Recoding
Modified Booth Recoding
Modified Booth Algorithm
• 12 x -5
• 13 x -6
• 27 x 17
Robertson Multiplier
➢Applicable for signed 2’s complement numbers.
Algorithm:
1. Initialize register “A” =0; Count = 0; Sign Bit (S) = 0 and store multiplicand in
“M” & multiplier in register “Q”.
2. Check Q[0] value. Q[0] = 1, add “A” with “M” else add “A” with zero.
3. Update S using the following expression: (M[n] & Q[0]) | Sold.
4. Perform right shift of (Sign Bit, A & Q) and increment the count. Go to step 2
until count value not equal to n. (n is length of the multiplier).
When count value is equal to n, perform the following
5. Check Q[0] value. Q[0] = 1, Subtract “A” with “M” else subtract “A” with zero.
6. Update S using the expression M[n] XOR Q[0].
7. Perform right shift of (Sign Bit, A & Q) and increment the count. Final product
in A & Q.
Robertson Multiplier
Ex:
-6 x -3
-12 x 8
Restoring Algorithm
Applicable for +ve numbers only.
Algorithm: Do the following “n” times

➢Shift A and Q left one binary position.


➢Subtract M from A, and place the answer back in A
➢If the sign of A is 1, set q0 to 0 and add M back to A (restore A);
otherwise set q0 to 1.
Restoring Division
Non - Restoring Algorithm

Applicable for +ve numbers only.


Algorithm: Do the following “n” times
Step I
➢If the sign of A is 0, Shift A and Q left one binary position and subtract
M from A; otherwise, shift A and Q left and add M to A.
➢If the sign of A is 0, set q0 to 1; otherwise set q0 to 0.
Step II
➢ If the sign of A is 1, add M to A.
Carry Look Ahead Adder

➢ Carry is calculated based on initial carry.

Co = AB + (A^B)C-1
ALU

➢Arithmetic Logic Unit


➢It is a digital circuit that performs arithmetic (add, sub etc) and logical
(AND, OR, NOT) operations.
➢John Von Neumann proposed ALU in 1945.
ALU
Two types of ALU. They are
Combinational:
➢Logic gates are used to construct this ALU ex. Adders, coders and
MUX
➢It can’t store the values & output depends on present inputs.
Sequential:
➢Combinational circuit & memory elements are used to construct this
ALU. Ex. FF, Counter, Shift Registers.
➢Output depends on present input and previous outputs.
Combinational Circuit ALU
Combinational Circuit ALU
Sequential ALU
Sequential ALU
Design Procedure of Sequential Circuit

➢Make a state table based on problem statement. The table should


has present states, input, next states and outputs.
➢Assign binary codes to the states in the state table.
➢Use excitation table of the FF and simplify the output expression (if
possible).
➢Construct the circuit.
Logic Diagram for Analysis
BCD Multiplier
BCD Multiplier
BCD Division
Floating Point Addition/Subtraction

Steps:
➢Compare the magnitude of two exponents and make suitable
alignments to the number with the smaller magnitude of exponent.
➢Perform the addition/Subtraction.
➢Perform normalization by shifting the resulting mantissa and
adjusting the resulting exponent.
EX:
1.1100 x 24 and 1.100 x 22
Floating Point Addition/Subtraction

X = 0100 0010 0000 1111 0000 0000 0000 0000


Y = 0100 0001 1010 0100 0000 0000 0000 0000

X = 0011 1111 0001 1001 1001 1001 1001 1001


Y = 0011 1101 1100 1100 1100 1100 1100 1100
Floating Point Multiplication & Division
Multiplication:
➢Add the exponents
➢Multiply the mantissas and determine the sign of the result.
➢Normalize the resulting value, if necessary.

Division:
➢Subtract the exponents
➢Divide the mantissas and determine the sign of the result.
➢Normalize the resulting value, if necessary.
Floating Point Multiplication & Division

0.621 x 0.721

-0.3 x 500.25

1.000 x 2-2 / -1.0100 x 2-1

91.34375/0.14453125

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