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Sanketika Vidya Parishad Engineering College: Date

This document is a letter from the Department of Electronics and Communication Engineering at Sanketika Vidya Parishad Engineering College to the Controller of Examinations at Andhra University regarding the M.Tech VLSI Sem-IV project viva-voce panel. It includes details of 7 students, their registration numbers, names, project titles, and guides. It notifies the controller that the online fee receipt and student details are attached for conducting the project viva-voce examinations.

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118 views2 pages

Sanketika Vidya Parishad Engineering College: Date

This document is a letter from the Department of Electronics and Communication Engineering at Sanketika Vidya Parishad Engineering College to the Controller of Examinations at Andhra University regarding the M.Tech VLSI Sem-IV project viva-voce panel. It includes details of 7 students, their registration numbers, names, project titles, and guides. It notifies the controller that the online fee receipt and student details are attached for conducting the project viva-voce examinations.

Uploaded by

bhaskarpsn
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SANKETIKA VIDYA PARISHAD ENGINEERING COLLEGE


(Approved by AICTE, New Delhi & Affiliated to Andhra University, Visakhapatnam)
P M Palem, VISAKHAPATNAM – 530 041
E:[email protected] w:www.svpec.edu.in P: (0891) 2781375, Ex -106

Date:

To

The controller of Examination

Andhra University ,

Visakhapatnam.

Sub : Regarding ECE,M-TECH ,VLSI ,SEM-IV ,Project viva-voce Panel .

Dear sir ,

Hereby we are submitting the receipt of on line fee and list of students with project
Thesis report for conducting of M.TECH , VLSI ,SEM-IV ,Project viva-voce .

This is for your information and necessary action .

Student details and project titles of individual students are attached .

VLSI (2017-19 ) STUDENTS DETAILS

SL REGD NO NAME OF THE Title of the project Guide name


NO STUDENT
1 317232940001 DOWLAPALLI GUNASRI Design and implementation of high speed Mr PSN Bhaskar
IEEE 754 double-precision floating point
multiplier .
2 317232940002 MIDATANA VENKAYA A 45nm CMOS technology exploring low Mr Y.SRAVAN
NAIDU power and fast 4 bit full adder using KUMAR
XOR/XNOR gates
3 317232940003 MUSUNURU VENILA High speed carry skip adder Mrs YPM
implementation using AOI and OAI based SURYAKIRAN
on transmission gates .
4 317232940004 SAMBANA DALINAIDU Design and performance analysis of low Mr
density parity check encoder and decoder . A.Ramakrishna
5 317232940005 VEGIREDDI SWAPNA Performance analysis of 32 bit VEDIC Dr Nihar ranjan
multiplier design using nikilam and kogge panda
stone adder .
6 317232940006 YERRA RAMCHARAN An exportable high speed ecc processor Mr manas ranjan
using RSD performed in FPGA biswal
7 317232940007 GUNNABATHULA High performance and low power 4-bit Dr. nihar panda
NANDINI comparator using onofic technique .

Principal
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SANKETIKA VIDYA PARISHAD ENGINEERING COLLEGE
(Approved by AICTE, New Delhi & Affiliated to Andhra University, Visakhapatnam)
P M Palem, VISAKHAPATNAM – 530 041
E:[email protected] w:www.svpec.edu.in P: (0891) 2781375, Ex -106

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