Verilog for design

History of Verilog
• Gateway Design Automation started
developing this language in 1985
• Phil Moorby designed the basic language and
the simulator
• Cadence Design System acquired Gateway in
1989
• Cadence opens Verilog in 1990
 History of Verilog (contd.)
• OVI (Open Verilog International): 1990
• 1993-1995 IEEE standardized 1364 LRM
• OVI merged with IEEE
• OVI proposes Verilog-AMS
• IEEE standardized Verilog 2000 LRM
 What is Verilog?
• Most popular Hardware Description Language (HDL)
• Easy to learn and master – syntactically similar to C
• Can be used to model system in almost all stages of EDA flow
– Behavioural
– RTL
– Structural
– Switch
– Analog – Verilog AMS
• Enhanced and exists in different version
– Verilog 95
– Verilog 2001 (V2K)
– System Verilog (SV)
• This training will follow Verilog 95 standard and its design aspects

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 Structural design
• AOI – AND OR INVERT • Verilog defines module as a unit
of boolean logic
• Module will have input and
A
B output ports
Y
C • Output ports will be driven by
D
some boolean equations with
• 4 gates to describe input ports as parameters
– 2 AND gates
– 1 OR gate
module
– 1 INVERTER
A
• Interconnection between gates B
Y = AOI(A,B,C,D) Y
C
D Output
port
Input ports

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 Structural representation
• AOI module • Verilog file AOI.v
// AOI module definition
module AOI(A, B, C, D, Y);
// port declaration
A e input A, B, C, D;
i1
B g output Y;
i3 i4 Y
C // internal wire declaration
i2
D f
wire e, f, g;
// gate instantiations
and i1(e, A, B);
and i2(f, C, D);
or i3(g, e, f);
not i4(Y, g);
endmodule

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 Module definition
• AOI module • Verilog file AOI.v
// AOI module definition
module AOI(A, B, C, D, Y);
// port declaration
A e input A, B, C, D;
i1
B g output Y;
i3 i4 Y
C // internal wire declaration
i2
D f
wire e, f, g;
// gate instantiations
and i1(e, A, B);
and i2(f, C, D);
or i3(g, e, f);
not i4(Y, g);
endmodule

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 Port declarations
• AOI module • Verilog file AOI.v
// AOI module definition
module AOI(A, B, C, D, Y);
// port declaration
A e input A, B, C, D;
i1
B g output Y;
i3 i4 Y
C // internal wire declaration
i2
D f
wire e, f, g;
// gate instantiations
and i1(e, A, B);
and i2(f, C, D);
or i3(g, e, f);
not i4(Y, g);
endmodule

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 Internal net declarations
• AOI module • Verilog file AOI.v
// AOI module definition
module AOI(A, B, C, D, Y);
// port declaration
A e input A, B, C, D;
i1
B g output Y;
i3 i4 Y
C // internal wire declaration
i2
D f
wire e, f, g;
// gate instantiations
and i1(e, A, B);
and i2(f, C, D);
or i3(g, e, f);
not i4(Y, g);
endmodule

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 Instantiations
• AOI module • Verilog file AOI.v
// AOI module definition
module AOI(A, B, C, D, Y);
// port declaration
A e input A, B, C, D;
B i1
g output Y;
i3 i4 Y
C i2
// internal wire declaration
D f
wire e, f, g;
// gate instantiations
and i1(e, A, B);
and i2(f, C, D);
or i3(g, e, f);
not i4(Y, g);
endmodule

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 Behavioral representation
• AOI module • Verilog file AOI.v
// AOI module definition
module AOI(A, B, C, D, Y);
// port declaration
A input A, B, C, D;
B output Y;
logic cloud Y
C // boolean logic equation
D
assign Y = ~((A & B) | (C & D));
endmodule

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 Test AOI - testbench
• To test AOI • A top-level Verilog module is
– Drive input ports created known as testbench
– Monitor or check output ports • Testbench will instantiate AOI
• To drive input ports module
– Use columns of truth-table • Testbench will use a block for
– Driving value set is known as driving test-vectors
test-vector

testbench
test-vectors
A
0110 A test-vector
B B
AOI module Y driver
C
AOI Y
C block
D D

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 Verilog testbench
• Testbench module • Verilog file testbench.v
module testbench;
reg TA, TB, TC, TD;
wire TY;
testbench
// module instantiation
TA A
AOI inst1(TA, TB, TC, TD, TY);
test-vector initial // drive test vectors
driver TB B inst1 Y begin
block TC C
TA = 1’b0; TB = 1’b0;
TD D TC = 1’b0; TD = 1’b0;
#10 TD = 1’b1;
– No ports #10 TC = 1’b1; TD = 1’b0;
– Instantiates AOI #10 TD = 1’b1;
#10 TB = 1’b1;
TC = 1’b0; TD = 1’b0;
end
endmodule

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 Reg declaration for test-vectors
• Testbench module • Verilog file testbench.v
module testbench;
reg TA, TB, TC, TD;
wire TY;
testbench
// module instantiation
A
AOI inst(TA, TB, TC, TD, TY);
TA
test-vector
initial // drive test vectors
driver TB B AOI Y
begin
TC C
block TA = 1’b0; TB = 1’b0;
TD D TC = 1’b0; TD = 1’b0;
#10 TD = 1’b1;
#10 TC = 1’b1; TD = 1’b0;
#10 TD = 1’b1;
#10 TB = 1’b1;
TC = 1’b0; TD = 1’b0;
end
endmodule

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 Driver block generating test-vectors
• initial block • Verilog file testbench.v
module testbench;
reg TA, TB, TC, TD;
wire TY;
testbench
// module instantiation
A
AOI inst(TA, TB, TC, TD, TY);
TA
test-vector
initial // drive test vectors
driver TB B AOI Y
begin
TC C
block TA = 1’b0; TB = 1’b0;
– Uses truth
TD D table columns TC = 1’b0; TD = 1’b0;
#10 TD = 1’b1;
#10 TC = 1’b1; TD = 1’b0;
#10 TD = 1’b1;
ABCD Y #10 TB = 1’b1;
0000 1 TC = 1’b0; TD = 1’b0;
end
0001 1
endmodule
0010 1
0011 0
0100 1
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 Monitor block for outputs
• Whenever output value • Verilog file testbench.v
changes, monitor should module testbench;

display that reg TA, TB, TC, TD;

wire TY;
0: 0000 : 1 // module instantiation
10: 0001 : 1 AOI inst(TA, TB, TC, TD, TY);
20: 0010 : 1 initial // monitor output
30: 0011 : 0 begin
40: 0100 : 1 // VCD waveform capture
$dumpvars;
// Log based data monitor
$monitor($time, “: “,
TA, TB, TC, TD, “ : “, TY);
// Control simulation time
#100 $finish;
end
endmodule

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 Concurrent execution units
• Verilog module can have following concurrent execution units
– Continuous assignment statements – assign
– Instantiations (module, gate, udp etc)
– Initial block – initial
– Always block – always
• Such units can execute concurrently – irrespective of where they are
declared
• Each of such unit represents logic cones driving internal reg / wires or
output / inout ports (ports are by of default wire type)
• Instantiation and assign statements can only drive wires
• initial and always blocks can only drive reg signals

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 Continuous assignment
wire x; • Continuous assignments
assign x = a + b – c * d; represents a wire driven by a
logic cone i.e. boolean equation.
• Executes whenever there is any
change in any driving net of the
logic cone
• Wires are only driven as wires can
a
b
c
x be driven continuously
d

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 Module instantiation
wire x, y, z; • Module instantiation will a insert a
AOI i1(a, b, c, d, x); copy of a parent / instantiating
AOI i2(e, f, c, g, y); module in the upper module
AOI i3(b, h, x, y, z); • Only wires can be connected to the
output / inout ports of the instances
• Each instance of same parent module
will represent distinct unit of logic
– There will be no sharing or
a i1
b interference of logic between two
c
x
instances of same parent module
d – Instances are copy of the entire logic
h i3
of the parent module
e i2 z
f
y
g

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 Initial block
reg x, y; • Initial block is mainly used in
initial testbench for generating directed
begin test-vectors
x = 1’b0; y = 1’b0;
• Executes once and starts at the
#20 x = 1’b1;
beginning of the simulation
#10 x = 1’b0; y = 1’b1;
#50 y = 1’b0; • Can only drive reg signals
#30 x = 1’b1; y = 1’b1; • Represents a timed sequence of
signal values – waveform
– Timing delays are used to create
the timed sequence
– If no timing delay or waits are
used, initial block ends
instantaneously at zero time

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 Examples of initial block
• Clock generator • Common timing controls used in
// Clock generator initial blocks
module clockgen(clock); – Timing delays / waits
parameter period = 10; • #10;
output clock; • wait(10);
reg clock; • @(x or y);
initial – System tasks
begin • $display
clock = 1’b0; • $monitor
forever • $dumpfile
#(period/2) clock = ~clock; • $dumpvars
end • $stop
endmodule • $finish

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 Random test-vector generation and
self-checking of AOI module
• Testbench module
module testbench;
parameter N = 10;
reg TA, TB, TC, TD;
wire TY;
AOI inst(TA, TB, TC, TD, TY);
Top level testbench module
initial begin // random test generator
repeat (N)
Random #10 { TA, TB, TC, TD } = $random;
test-vector
generator #10 $finish;
initial block
end
initial // self checking block
Self-checking
initial block
forever begin
@(TA or TB or TC or TD or TY) #1;
if (TY != ~((TA & TB) | (TC & TD)))
$display(“ERROR[%0d]: ”, $time,
TA, TB, TC, TD, “ : “, TY);
end
endmodule

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 Always block
• Difference between initial and • Always block is used for
always block executions implementation of
– Complex combinational logic
– Sequential logic - flip flop
– Finite state machine (FSM)
Start of
simulation • Executes repeatedly infinite
number of times
• Can only drive reg signals
initial block always block
• Triggered by any change in signals
in the sensitivity list
– @(x or y or z)
– @(posedge clock)
End of
simulation

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 combinational always
• 2x1 Multiplexer • ALU

ACC_in
a 1
ACC_out
q
B
b 0
op
s

always @(s or a or b) always @(ACC_in or B)

if (s) if (op == `ADD)
q = a; ACC_out = ACC_in + B;
else else if (op == `SUB)
q = b; ACC_out = ACC_in - B;
else if …

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 Sequential always
• Flip flop • Latch

Data Q Data Q

Clock Enable

always @(posedge Clock) always @(Enable or Data)

Q = Data; if (enable)
Q = Data;

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 Blocking and Non-blocking
Assignments
• Assignment integer x, y, z;
LHS_expr1 = RHS_expr2; always @(posedge clock)
begin
LHS_expr3 <= RHS_expr4;
x <= x + 1;
• When the assignment is y = x + 1;
evaluated z <= x + y;
– Blocking assignment updates LHS end
by RHS If x was 5 before clock comes, at clock
– Non-blocking assignment edge the always will be executed and
evaluates RHS and schedules to values of
LHS. The LHS is updated by the
scheduled value, when execution
waits for an event

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 Blocking and Non-blocking
Assignments
• Assignment integer x, y, z;
LHS_expr1 = RHS_expr2; always @(posedge clock)
begin
LHS_expr3 <= RHS_expr4;
x <= x + 1;
• When the assignment is y = x + 1;
evaluated z <= x + y;
– Blocking assignment updates LHS end
by RHS If x was 5 before clock comes, at clock
– Non-blocking assignment edge the always will be executed and
evaluates RHS and schedules to values of
LHS. The LHS is updated by the – x will be 5 + 1 = 6
scheduled value, when execution – y will be 5 + 1 = 6
waits for an event – z will be 5 + 6 = 11

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 Blocking and Non-blocking
Assignments continued
• Swap logic • Design guidelines
always @(posedge clock) – Separate combinational and
begin sequential blocks, so that later
x <= y; only represents flip flops
y <= x; – For combinational block, use
end only blocking assignments
– For sequential block, use only
• If always block has no other non-blocking assignments
timing wait except the sensitivity – Do not mix them. If you mix, you
list, you can consider that might find:
scheduled non-blocking • Unexplainable behavior
assignment happens at the end of • Simulation output varies with
always block simulation tool

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 Representation of vector or bus
• Bus or vectors are represented as • Bitwise operation
reg [3:0] data4; reg [3:0] data;
output [0:7] q; assign is_all_zero = & data;
• Bus is just collection of a number of • Bit select
signals with same name but different // Multiplexer
indices assign q = data[i];
• One can perform following vector • Part select
operations // Address latch enable
– Bit wise operation address[15:8] = address_high;
if (ale) address[7:0] = data;
– Bit select
– Part select • Concatenation
// Bit reversal
– Concatenation
reg [3:0] data;
data = { data[0], data[1],
data[2], data[3] };

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 Representation of 4-valued logic
• Verilog introduces two more values except • Tristate buffers are mainly used for
normal 0 and 1 modeling bidirectional / inout ports
– 0: Low value e.g. 1’b1 input read;
– 1: High value e.g. 4’b1111 inout [7:0] data;
– x: Unknown wire data_in; reg data_out;
– z: Tristate or undriven assign data = read ?
• Note, in w’Tv, say 16’h8CD2 data_out : 8’bzzzz_zzzz;
– w represents width in bits assign data_in = data;
– T represents type – d, b, o, h
– v represents value – 0-9, A-F, x, z
• Tristate buffer Memory

q = enable ? data : 1’bz; data_in

data
data_out

data q read

enable

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 Design of bus interface units
• Consider that the slave becomes • ready driving logic
ready after 4 clocks from master – Assert ready signal at 4 clocks after
asserts valid valid assertion
• So slave bus interface logic has – De-asserted when valid is de-
– ready driving unit asserted
– Data transfer unit – Note, valid here means clocked
value of valid at slave
• Data transfer logic
– Data is transferred when both valid
Slave and ready are asserted
‘ready‘
ready driving
Bus
Interface
– Note, clocked value of valid and
valid logic
Logic ready are checked at slave. Also
clock
note, clocked value of ready means,
one clock after driving ready
Data
transfer
data logic

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 Slave implementation
• ready driving logic
module ready_logic(clock, valid, ready);
input clock, valid;  Data transfer logic
output ready; module data_transfer_logic(clock, valid,
reg ready; ready, data);
reg [4:0] count; input clock, valid, ready;
always @(posedge clock) input [7:0] data;
if (valid) always @(posedge clock)
begin if (valid && ready)
if (count < 4) // some serialization logic
count <= count + 1; $display(“Slave: %0d: Data
Tranferred: %h\n”, $time, data);
else
endmodule
ready <= 1’b1;
end
else  Assignment: Write
begin
 Slave Bus Interface Unit module
count <= 0;
ready <= 1’b0;
 Master Bus Interface Unit as testbench
end
endmodule

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