Page 1 of 35

ABSTRACT

The waveform generator design presented in this paper can be used in

automatic control and measurement, electronic music synthesis and data
encoding [1]. The scope of the paper is limited to applications in electronic
circuit design and measurement.

A full methodology and approach is presented for designing a square and

triangular symmetric waveform generator with frequency control. It is often
desirable to produce a signal with a certain frequency and to control this
frequency in a linear fashion with an input voltage. In the proposed design
varying the input voltage allows for a linear control of the resulting
frequency.

Fundamental principles of operation of the circuit are presented and

explained. The design is based entirely on the fundamentals of Op-Amp
circuit operation. Particularly, a hysteresis bistable (fundamentally a
comparator) and an integrator circuit together with an input voltage control
are used. The simulation results and laboratory test results are presented
and discussed as well as deviations from theoretical results are analyzed.
Several recommendations for future improvements are made.

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Table of Contents
ABSTRACT ...................................................................................................................................................... 2
Table of Contents .......................................................................................................................................... 3
OBJECTIVES AND PURPOSE ........................................................................................................................... 4
INTRODUCTION ............................................................................................................................................. 5
THEORY ......................................................................................................................................................... 6
The comparator ........................................................................................................................................ 6
The histerisis bistable ................................................................................................................................ 7
The inverting integrator ............................................................................................................................ 9
Inverting integrator and bistable combined ........................................................................................... 11
Derivation of the equation of frequency ................................................................................................ 13
DESIGN ANALYSIS ........................................................................................................................................ 15
Input voltage control .............................................................................................................................. 16
Selecting the Op-Amps............................................................................................................................ 23
Amplitude Control................................................................................................................................... 24
Frequency Range Select .......................................................................................................................... 24
EXPERIMENTAL PROCEDURE ...................................................................................................................... 27
Testing the integrator-bistable-attenuator configuration ...................................................................... 27
Testing the switch with the voltage control circuit ................................................................................ 27
Testing the final design ........................................................................................................................... 28
RESULTS and OBSERVATIONS ..................................................................................................................... 29
CONCLUSION AND RECOMMENDATIONS................................................................................................... 33
REFERENCES ................................................................................................................................................ 34
APPENDIX .................................................................................................................................................... 34

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OBJECTIVES AND PURPOSE

Using OP-AMPS and discrete components only, the objective is to

design, simulate, implement and test a Linear Voltage-controlled
Multi-function Waveform Generator. In this design the device will
output square and triangular waveforms only.

The main challenge of the study was to design a circuit that would produce
the triangular and square waveforms without any input signal. The purpose
of such an electronic device is to provide variable frequency for control and
measurement. In many applications the frequency is required to be linearly
dependant on the control voltage with a constant of proportionality K [1].

Page 4 of 35
INTRODUCTION

The entire design is based on the fundamental principles of Op-Amp

operation. The Op-Amp amplifies the difference between its positive
and negative terminals and produces an output at its output
terminal. When it is configured to have no negative feedback (also
called an open-loop configuration) the Op-Amp will simply act as a
comparator. This means that the Op-Amp will always be in a
saturated state, either negative or positive. Even though the Op-
Amp open-loop gain is very large (usually on the order of 106v/v),
the comparator’s output will always be saturated at the value of
either one of the power supply’s values, since the transistor based
inner circuitry of the Op-Amp has saturation point limited at the DC
power supply voltage.

The simple comparator, if slightly modified, becomes a powerful tool

for square waveform generation. The comparator is applied in the
current design by adding few additional components to control the
critical points at which the comparator changes its state.
A triangular and a square waveform generator can be implemented
using linear and non-linear circuits [1]. The first circuit that comes
to mind for triangular waveform generation from a pulse is the
integrator. A pulse input to the integrator is required, in order to
produce a triangular waveform on the output. One circuit that is
able to provide a pulse response to an input voltage is a special type
of a comparator, known as the Hysterisis Bistable circuit (discussed
later in the report). Thus, the approach for the general design is to
combine these two circuit blocks in such a way that would allow the
extraction of triangular and square waveforms, this would in turn
allow a voltage controlled frequency.

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THEORY

The theory behind the project is based on the fundamental

principles of operation of the Op-Amp circuit. That is, the Op-Amp
amplifies the difference between its negative and positive input
terminals and provides the amplified result at the output terminal
[2]. This is the basis for using the Hysterisis Bistable and an
integrator circuits in the design.

The comparator
To understand the hysteresis bistable consider the simple
comparator shown in Figure 1. The principle of its operation in is
straightforward: in the case of Figure 1. when the input voltage is
greater than zero (i.e. greater than the voltage applied at the
negative terminal) the output of the comparator will saturate at the
L+, positive power supply level. It will remain saturated until the
Input voltage goes below zero, the comparator then will saturate at
the negative power supply value, L- [2]. In this example the
threshold or the critical point for state change of the comparator is
the zero volts. Also notice that that as the input goes above zero the
comparator saturates at L+ level, and as the input goes below zero
the comparator saturates at L- level. The circuit with this behavior is
known as the non-inverting comparator.

Figure 1. A non-inverting comparator with zero threshold voltage level.

The inverting counterpart of the comparator in Figure 1 is depicted

in Figure 2 on the next page.

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 Figure 2. An inverting comparator with zero volts threshold point.

Here the threshold or the critical point is also zero volts (the
grounded positive terminal). The difference is that as the input
reaches a value greater than zero the difference between the two
terminals becomes negative, amplifying this negative value the Op-
Amp saturates at the negative power supply level, L-. Similarly,
when the input reaches a negative value the output saturates at the
positive power supply level, L+. The circuit with this behavior is
knows as an inverting comparator.

The histerisis bistable

Keeping in mind the inverting comparator consider the circuit shown
in Figure 3.

Figure 3. An inverting bistable with threshold levels controlled by the values of R1 and R2.

The only difference with the inverting comparator is the resistor

network in the positive feedback path. Notice the absence of
negative feedback and the presence of a positive one. This
configuration is known as an inverting Bistable due to the fact that it
has only two stable states. The analysis of this circuit is
straightforward. Assuming negligible current into the input terminals
of the Op-Amp (this assumption is valid since the input resistance of
the Op-Amp is much greater than the resistors used at the input and
in the feedback path) the resistor network effectively forms a
voltage divider. Instead of the zero volts as the threshold point for

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state change then, the threshold point is now the voltage at the V+
node which can be determined using the voltage divider rule.

𝑅1
[𝑉 +] = 𝑉𝑜𝐵 ∗ (𝑒𝑞 1)
𝑅1 + 𝑅2

Also suppose the Op-Amp is at its negative saturation state, then

VoB = [L-] and equation 1 becomes:

𝑅1
[𝑉 +] = [𝐿 −] ∗ (𝑒𝑞 2)
𝑅1 + 𝑅2

Now the fact that the Op-Amp is at the negative saturation state
tells us that [Vin] > [V+] and the state will switch to the positive
state as soon as Vin becomes less than V+. Thus the threshold
voltage is not zero anymore as was the case for a simple
comparator but is at a point controlled by the two resistors in the
input and in the positive feedback loop [2]. To determine the
threshold point that [Vin] must reach for the Op-Amp to switch to
the positive state we substitute [Vtl](V Threshold Low) for [V+].
Thus, for the circuit to switch state to L+, [Vin] must reach the
point:

𝑅1
[𝑉𝑡𝑙 ] = [𝐿 −] ∗ (𝑒𝑞 3)
𝑅1 + 𝑅2

In a similar manner, the threshold high point can be found, i.e. the
point when the bistable switches to its negative state. Since the
Bistable is an inverting one, this point will have a positive value.

𝑅1
[𝑉𝑡ℎ ] = [𝐿 +] ∗ (𝑒𝑞4)
𝑅1 + 𝑅2

Figure 4 on the next page shows the transfer characteristic of the

inverting Bistable circuit.

Page 8 of 35
 Figure 4. The transfer characteristic of the inverting bistable

When Vin>Vtl, i.e Vin starts from the positive side the state is at L-.
As soon as Vin reaches the negative threshold-low value the state
switches to L+. Similarly, when the input starts at some negative
point the output is saturated at L+ and as soon as the threshold-
high value is reached by the input the state changes to L-.
It is clear from the presented theory that the Bistable configuration
is capable of generating a square waveform. What is needed in
conjunction with the Bistable is an external event that would trigger
the state of the Bistable.

The inverting integrator

Before going any further, we need to review the principles of the
integrator operation in response to a pulse input. An integrator
circuit is based on an Op-Amp with a capacitor in the feedback path
and a resistor at the input. Figure 5 shows a typical integrator.

Figure 5. A typical integrator shows the current that charges the capacitor.

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The analysis of this circuit for a pulse input can be broken down into
two cases

1. Vin > 0
2. Vin < 0

In the first case Vin > 0 and a node equation at node Vx gives

𝑉𝑖𝑛 – 𝑉𝑥 𝑑𝑉𝑐
= 𝐶∗ (𝑒𝑞5)
𝑅 𝑑𝑡

Where VX is the voltage at the positive terminal of the Op-Amp and

VC is the voltage across the capacitor. Now the capacitor charges by
the constant current from the pulse input, therefore negative
feedback is present and the negative terminal tracks the positive
terminal of the Op-Amp. Thus VX = 0 and thus:

𝑉𝑖𝑛 𝑑𝑉𝑐
= 𝐶∗ (𝑒𝑞 6)
𝑅 𝑑𝑡

but also 𝑉𝑜 = 0 − 𝑉𝑐 = −𝑉𝑐 and when it is substituted into eq 6 and

the equation is solved for 𝑉𝑜 . The result is:

𝑡
𝑉𝑖𝑛 𝑉𝑖𝑛
𝑉0 = � − 𝑑𝑡 = − ∗ 𝑡 + 𝑉𝑐 (0) (𝑒𝑞 7)
0 𝑅𝐶 𝑅𝐶

Now, as the circuit is just powered up, the capacitor initial voltage
will be zero, therefore the final result is:

𝑉𝑖𝑛
𝑉0 = − ∗𝑡 (𝑒𝑞 8)
𝑅𝐶

The first observation from this equation is that the integrator is

inverting and with positive pulse input a triangular waveform of
negative slope will be produced and a positive slope will produced

Page 10 of 35
for the negative side of the pulse. The second observation is that the
slope of this line is 𝑉𝑖𝑛 ⁄𝑅𝐶
For the second case, when 𝑉𝑖𝑛 < 0 the result is identical except now
the slope of the integrator output is positive (𝑉𝑖𝑛 < 0 therefore
−𝑉𝑖𝑛 > 0). The input and output relationship plot of the integrator is
shown in Figure 6.

Figure 6 Integrator response to a pulse input.

Summarizing the principles of operation of the bistable and the integrator it

is clear that an integrator would do the job of a triangular wave generation if
the input to the integrator is a pulse. Therefore, it makes sense to combine
the Bistable and the integrator in a feedback configuration as shown in figure
7.

Figure 7. Integrator with a non-inverting Bistable. Draft design demonstration and frequency equation derivation.

Inverting integrator and bistable combined

In this configuration a non inverting Bistable has been used since
the feedback loop must have negative loop gain in order for the

Page 11 of 35
system to be stable. This diagram is the first step towards the final
design and this circuit can be used to verify theoretical results. In
this configuration the output at 𝑉𝑜𝑢𝑡 is a triangular wave with
amplitude V[threshold high] and V[threshold low] and the output
taken at the VoB node is a square wave with amplitude L+ and L-.
The functionality of this circuit is completely based on the discussion
of the operation of the Bistable circuit and of the integrator. Recall
that the Bistable changes its state when the input reaches particular
values [V threshold high] and [V threshold low]. A non-inverting
Bistable switches to saturation at L+ when the input reaches the
high threshold point and it switches its state to L- when the input
reaches the low threshold point. To analyze the circuit in Figure 7
suppose the power supply was just turned on and thus the bistable
was in one of its states, say [L+]. Now [L+] is also the input to the
integrator, therefore the integrator will start producing a straight
line with a negative slope of [-L+/RC]. Keep in mind that the
integrator output is connected directly to the input of the Bistable.
Thus, as the integrator output decreases linearly (negative slope)
this output is being fed directly into the bistable. At some point the
integrator output will reach the threshold low value of the Bistable.
This will force the Bistable to switch its state to L-, which in turn will
be fed back to the integrator. This new input will force the integrator
to switch the slope of its output from negative to positive and thus
the integrator output will now be an increasing line with positive
slope [-L-/RC]. This will continue until the integrator output (which
is the input of the Bistable) reaches the threshold high value of the
Bistable and the cycle will repeat again indefinitely. Figure 8 is a
visual aid for the above explanation.

Figure 8. The output of the Integrator-Bistable feedback loop showing the threshold voltage values
and their effect on the resulting waveform.

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The final design is based precisely on the described behaviour of the two
circuits.

Derivation of the equation of frequency

The goal of the design is to obtain a linear relationship between the
resulting frequency of the waveforms and the controlling voltage
source. To complete this section let’s derive the frequency equation
for the circuit in Figure 7. Refer to Figure 9 for visual aid.

Figure 9. Derivation of the frequency equation.

Within the time period between times T1 and T2 the slope of the
increasing line of the triangular waveform is known to be [-L-/RC].
But also the slope can be determined by the equation of the line
within T1 and T2. Therefore:

𝑉𝑡ℎ − 𝑉𝑡𝑙
𝑠𝑙𝑜𝑝𝑒 = (𝑒𝑞 9)
𝑇2 − 𝑇1

Where 𝑇2 − 𝑇1 is half the full period, 𝑇/2 for a symmetric waveform.

It is also known that

−𝐿−
𝑠𝑙𝑜𝑝𝑒 = (𝑒𝑞 10)
𝑅𝐶

The result of equating the above two equations is:

Page 13 of 35
 𝑉𝑡ℎ − 𝑉𝑡𝑙 −𝐿−
= (𝑒𝑞 10)
𝑇/2 𝑅𝐶

From which there is no difficulty to extract an expression for the full

period:

(𝑉𝑡ℎ − 𝑉𝑡𝑙 ) ∗ 2 ∗ 𝑅𝐶
𝑇 = (𝑒𝑞 11)
−𝐿−

Now since [-L-] = [L+] and [f = 1/T] the final result can be written
as:

−𝐿−
𝑓 = (𝑒𝑞 12)
(𝑉𝑡ℎ − 𝑉𝑡𝑙 ) ∗ 2 ∗ 𝑅𝐶

It must be emphasized that this result was derived with the

assumption that the waveform is symmetric and thus the result is
valid strictly for the case of symmetric, 50% duty cycle waveforms
(which is the case in the current design). This result is the basis for
the design analysis.

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DESIGN ANALYSIS

Several practical constraints come into play when transitioning from

theoretical analysis to design. Even though equation 12 is
completely valid several considerations must still be made:

1. Equation 12 is directly proportional to the power supply

voltage
2. It would impractical to temper with power supply to adjust the
frequency in the desired range.

Observe that the high and low levels of the power supply (L+ and L-
) are fed back directly into the input to the integrator. Keep in mind
that our goal is to design a circuit to implement linear frequency
control with input voltage with a relationship:

𝑓0 = 𝐾 ∗ 𝑉𝑖𝑛 (𝑒𝑞 13)

Where

1
𝐾 = (𝑒𝑞 14)
2 ∗ (𝑉𝑡ℎ − 𝑉𝑡𝑙 )𝑅𝐶

K is the proportionality constant, or equivalently the slope of the line

describing the frequency-voltage relationship of the final circuit as
shown in the next figure.

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 Figure 10. The required frequency-voltage relationship of the final design.

What must be achieved then for a linear frequency control by a

voltage, is:

1. A fixed slope
2. Variable pulse supply to the integrator to produce the
frequency in the desired range.

Input voltage control

Based on the discussion above it is then required to manipulate the
integrator input such that it is user controlled and completely
independent of the power supply. One practical circuit that provides
the solution is depicted in Figure 11.

Figure 11. The circuit used to provide control over the input voltage to
Integrator and thus linear control of frequency.

The analysis of the circuit in Figure 11 should be broken down into two
parts:

1. Switch is Open
2. Switch is closed

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Figure 12 shows the analysis for the first case.

Figure 12. The analysis of the integrator input control circuit

for the case of the open switch.

In this case, current into the positive terminal of the Op-Amp is negligibly
small (as long as the resistor Rx values are significantly lower than the input
resistance of the op-Amp); therefore the voltage at the positive terminal is
Vc. Now since there is negative feedback, the negative terminal will track the
positive terminal and therefore the voltage at the negative terminal is also
Vc. It follows that there is no current through the input resistor at the
negative terminal (since there is no voltage difference across it). This in turn
means that there cannot be any current through the feedback resistor. This
leads to the conclusion that the output is equal to Vc. What the analysis
shows is that when the switch is closed the output follows the input.
For the second case Figure 12 shows the analysis.

Figure 13. The analysis of the integrator input voltage control circuit
for the case of the closed switch.

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In this case the switch forms a short circuit with the ground and therefore
the positive terminal of the Op-Amp is grounded. Also, since there is
negative feedback the positive and the negative terminals track, therefore
the negative terminal is also at zero volts. This means that current exists
through both the input resistances and the current is the same in both
branches. Now since there is no current into the negative terminal, this
current, I, also passes through the feedback resistor and thus forms a
voltage difference across that resistor. From the analysis shown in the figure
the output voltage equals [–Vc]. What this tells us is that when the switch is
closed, the output is the negative of the input, and this is a very useful and
important conclusion.

The circuit in Figure 11 then permits us to have complete control over the
input to the integrator. This input voltage is completely independent of the
power supply or any other internal properties of the circuit. By Equation 13,
since the proportionality coefficient, K, is fixed at the required value, Vc
allows the user to control linearly the frequency of the generated
waveforms. One thing to note is that the resistor values Rx must be selected
such that their values are much lower than the specified input resistance of
the utilized op-amp. This is necessary in order for the Op-Amp to be
considered ideal in this particular application. This means that the current
into the Op-Amp’s terminals can be neglected to simplify the analysis and
implementation.

The circuit blocks discussed so far can now be put together in the diagram
shown in Figure 14.

Figure 14. The design with input voltage control.

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Things to notice are the voltage limiter and the switch components. The
limiter is necessary to isolate the switch from the power supply and to
simplify the design and maintainability of the switch. The limiter consists of a
zener diode and a small signal diode to provide constant voltage (~7.5v) to
the input of the switch. This way it is easier to adjust all the components for
the constant voltage coming out of the limiter. Then as long as the Bistable
output stays above the limiter cut-off point the switch will always have the
required voltage to operate. The components of the limiter are shown in
Figure 15.

Figure 15. The limiter at the input of the switch.

The value of the resistor 𝑅𝑙𝑖𝑚 was chosen such that the current through the
diodes would be satisfied for the specified voltage drop. The output of the
limiter was then directed to a voltage divider as shown in Figure 16. The
divider was necessary for the protection of the switch from overload by a too
large voltage at the input. The diode was necessary to protect the MOSFET
from too large negative gate-source voltage.

Figure 16. The implementation of the switch circuit.

The procedure for the analysis of the full circuit was as follows. The
integrator-bistable configuration was analyzed separately from the voltage
control, the switch and the limiter circuits. These components are
independent and therefore it makes little sense to analyze them together.
Instead, an inverting attenuator was used in the integrator-bistable feedback

Page 19 of 35
loop in order to test the circuit’s response to a changing input voltage. The
input voltage was changed simply by varying the value of the attenuator
feedback resistor. This is shown in Figure 17.

Figure 17. The waveform generator circuit at the testing stage. The attenuator is used to adjust the input to the integrator by
varying its feedback resistance. This allows for debugging of the operating parameters.

It must be noted that an inverting bistable is used in the final design

(discussed in the Theory section) since with the voltage control circuit in
place the loop gain must be negative for the circuit to function. The
simulation results for this configuration are shown in the next 2 figures

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Page 21 of 35
Using the equations and principles derived in the Theory section for the
operation of the inverting Bistable and inverting integrator, the necessary
component values for the circuit were determined.

As per the specifications, the required maximum frequency is 4000Hz and

the range of input voltage adjustment is 0-5V. Initially, the circuit was
tested to operate at 4000Hz at 5V input. Since VC will be adjusted from 0 to
5 Volts and the maximum frequency is 4000Hz, a slope of 800Hz/volt was
required. Also, the required amplitude of the triangular and the square
waves is known to be 4V peak, which means that the Bistable threshold
voltage is 4 volts. All of this information is brought together in Equation 15:

1 1
𝐾 = 800 = = (𝑒𝑞 15)
2 ∗ (𝑉𝑡ℎ − 𝑉𝑡𝑙 )𝑅𝐶 2 ∗ �4 − (−4)� ∗ RC

Now this is the only equation for the analysis but there are two unknowns, R
and C. Due to a much wider choice of resistances than capacitances, the
capacitor was selected and fixed. The value used was 0.01uF. Based on this
value the integrator resistance was calculated from Equation 15 to be:

𝑅 = 7.81𝑘Ω 𝑎𝑛𝑑 𝐶 = 0.01µ𝐹

For the resistance values R1 and R2 of the bistable, equation 4 gives:

𝑅1 𝑅1
[𝑉𝑡ℎ] = 4 = [𝐿 +] ∗ = 15 ∗ (𝑒𝑞 16)
𝑅1 + 𝑅2 𝑅1 + 𝑅2

From this equation the relationship between R1 and R2 was derived and the
resistors were picked based on the availability of the components in the
design kit. This calculation however is imprecise because the real Op-Amp
will not saturate exactly at the power supply level. For this reason the circuit
was first simulated with the resistor values for the ideal case, the saturation
limits of the op-amp were observed and the resistor values were
recalculated. Based on the simulation results the chosen values were:

Page 22 of 35
 𝑅1 = 10𝑘Ω, 𝑅2 = 22𝑘Ω

For the limiter circuit three components were needed, a current limiting
resistor, two zener diodes and two small signal diodes. The selected zener
diodes were 1N4734A (6.2v at 40mA) and the selected small signal ones
were 1N4148 (1.0V at 10mA). These would give a combined clamping at
approximately 7.5V (since the current through small signal diode was
expected to be higher than 10mA).
A 180Ω current limiting resistor was chosen from the ones available to
provide current of approximately 30mA.

For the switch protection voltage divider and diode, the chosen diode was a
small signal 1N4148 and the resistors were chosen to provide approximately
3V gate-source voltage to fully close the transistor. The utilized transistor
had 0.7V threshold gate-source voltage. The voltage division resistors were
selected to be equal, thus to supply ~3.5 volts to the transistor for proper
operation.

Selecting the Op-Amps

The designed circuit must output square waveforms at two points (one at
the input to the integrator and the other at the output of the bistable). It is
known, however, that the op-amp circuits have a limitation on the maximum
rate of change of the signal at their outputs and the ideal square wave has
an infinite rate of change at the transition points. This characteristic is called
the Slew-rate of the Op-Amp and is defined as the maximum rate of change
of the output signal the Op-Amp can provide before the signal gets distorted.
From the available Op-Amps, the ones with highest slew rate characteristic
were the LM318 ICs. These are able to provide at least 50V/us signal rate of
change at the output. Since there was no better choice available in the
design kit the LM318 ICs were selected to be used in the voltage control
circuit and in the bistable circuit. The only remaining Op-Amp was the LM741
which has a much lower specified Slew-Rate at about 0.5V/us. This limitation
was taken into account when designing the integrator circuit and analysis
was performed in order to determine whether this circuit was capable of
outputting the square wave without distortion with the required maximum
frequency. Thus in order for the signal to be undistorted the maximum rate
of change of our signal must be less than the specified slew-rate of the Op-
Amp. It is known from the designed circuit that the maximum slope of the
triangular wave is:

Page 23 of 35
 5[𝑉] 0.641[𝑉 ] 0.5[𝑉 ]
𝑠𝑙𝑜𝑝𝑒𝑚𝑎𝑥 = = < (𝑒𝑞 17)
𝑅𝐶 µ𝑠 µ𝑠

The result means that it was safe to use the 741 Op-Amp for the integrator
configuration because the output waveform would not be limited by the slew
rate at the maximum required frequency. Therefore, it will not be limited at
the lower frequencies.

Amplitude Control
To implement the amplitude control of the triangular and the square
waveforms a simple voltage divider circuit with a potentiometer was used.
The output was taken from this circuit as shown in the next figure.

Figure 18. The voltage dividers used for amplitude control. The user can adjust the
potentiometer value for amplitude range 0 – 4 volts.

The resistor values were chosen based on the measurements of the

triangular and square wave amplitudes performed in the laboratory.

Frequency Range Select

The specifications require the final design to operate at two frequency
ranges. The first range of operation has already been designed and
discussed in detail. The only difference in the ranges of operations is the
constant of proportionality of the frequency-voltage dependence. For the
second range the frequency-voltage slope is:

4000
𝑠𝑙𝑜𝑝𝑒2 = 𝐻𝑧/𝑣𝑜𝑙𝑡 = 160 𝐻𝑧/𝑣𝑜𝑙𝑡 = 𝐾 (𝑒𝑞 18)
25
Page 24 of 35
The only practical way to change the slope of operation from 800Hz/volt to
160Hz/volt is to calculate the value of the RC network resistor which would
provide this slope. From the derived theory, this resistor value is 200kΩ,
however tests have shown that the resistor must be selected to be of twice
lower value to achieve the required slope in reality. Therefore, a 100kΩ
resistor was the final choice. The final design is shown in the next figure.

Figure 19. The Final Design with frequency range select and amplitude control.

The simulation results for the final design for frequency range 1 and no
amplitude control are shown in the next two figures.

Page 25 of 35
Figure 20. The waveform obtained through simulation of the final design.

Figure 21. The circuit used for simulating the design.

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EXPERIMENTAL PROCEDURE

The experimental procedure can be summarized in the following

steps:

1. Test integrator-bistable-attenuator circuit block separately

2. Test the switch with the voltage control circuit
3. If components 1. and 2. are showing expected results then
connect them together and test the final configuration.
4. If components 1. and 2. do not operate as expected then split
1 and 2 into their constituent parts and test each part
separately.
5. Verify results
6. Make adjustments as necessary
7. Gather data

Testing the integrator-bistable-attenuator configuration

In the first step the circuit components were connected as shown in
Figure 16. As per specifications, the maximum expected voltage at
the input of the integrator is 5 volts. Accordingly, the attenuator
resistors were selected to provide attenuation of the signal on the
output of the bistable, which from the simulation results was
expected to be at about 12.8v peak-to-peak or 6.4 volts peak.
Based on these values the attenuation was varied from 6v/v down
to 3v/v to verify circuit operation.

Testing the switch with the voltage control circuit

The switch and the voltage control circuits were tested to verify that the
transistor properly opened and closed, that the input stage transistor diode
properly limited the negative voltage on the transistor input and that voltage
control provided the expected result as discussed in the ‘Input voltage
control’ subsection. The voltage divider on the transistor input stage was
selected to provide approximately 3 volts gate-source voltage to ensure
proper transistor operation.

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Testing the final design
After verification of the discrete circuit blocks, the final design was
assembled as shown in the following figure.

Figure 22. The Final Design with frequency range select and amplitude control.

From the final design test the frequency data was gathered at
various values of the input voltage. This data is plotted in the next
section and the results are discussed.

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RESULTS and OBSERVATIONS

Some things to note before discussing the observations:

1. At the time of final testing LM318 Op-Amps were not

available. Thus three 741s were used for the entire design.
2. The resistors of the voltage control circuit, Rx, were selected
improperly. Their value was too high for the design purposes.
The implications will be discussed shortly.

First, the circuit was tested with the LM318 Op-Amp model before
the LM318 Op-Amp was made unavailable. The oscilloscope image
of that test is shown below. Note that this test was performed on
the circuit with a feedback attenuator (Figure 16).

Figure 23. The oscilloscope reading for the initial test of the final design with LM318 Op-Amps at the
Bistable and voltage control stages

There are several observations worth mentioning:

1. The duty cycle of the final design is not 50%

2. Therefore, the triangular wave rise and fall slopes vary.
3. There is a D.C. shift of the resulting square wave

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The test result of the final circuit with user voltage (and therefore
frequency) control (with amplitude control) is shown in the next
figure. Note that the final design consisted of LM741 op-amps and
not LM318s. Therefore a Slew-Rate distorted square wave is
expected. Due to this distortion a mismatch is also expected in the
switching points of the bistable and the points where the integrator
reaches the threshold levels. The final result is shown below:

Figure 24. The oscilloscope reading of the final design. The slew rate distortion of the 741 Op-Amps can be observed. Due to
this distortion the triangular wave peaks do not coincide with the square wave’s rise and fall points.

As mentioned before, frequency values were recorded for selected values of

input voltage for both ranges of operation of the final product. The next
figure shows the final plot of the frequency voltage relationship for the first
range of operation:

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 Frequency-Voltage relationship in the 1st range of
operation [f/5 Hz/volt]
5
4.4
4 4.1
3.7
3.3
3
f [Hz] 2.7
2 2

1 1

0
0 1 2 3 4 5 6
Vin

Figure 25. The plot of the final data obtained for range 1 of operation

It is clear from the plot that the resulting frequency-voltage relationship is

not perfectly linear. It is also evident that there is a cutoff input voltage
point below which no output is observed. The main cause of these
discrepancies is the resistor selection of the input voltage control circuit. The
values selected, as shown in Figure 20, were 1MΩ. This value is not only
comparable, but is 3 times larger than the specified minimum value and one
half of the specified maximum value of the input resistance of the 741. The
major implication is that the input current of the op-amp cannot be
neglected. This means that up to some input point the op-amp will be
drawing on more current than is required for the circuit to operate as the
desired voltage controller. This point on the plot of Figure 23 is the 2 volts
point of the input voltage.

The result of the second range of operation is shown in Figure 24 on the

next page.

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 Frequency-Voltage relationship in the 2nd range of operation
[f/25 Hz/volt]
250

200 206
177
150 151
f [Hz] 123
100 93
63
50
29
0
0 1 2 3 4 5 6
Vin [volts]

Figure 26. The frequency-input voltage relationship for the second range of operation of the design.

First thing to note from the graph is that the resulting slope significantly
deviates from the required one. The graph, however, shows an ideal linear
relationship between the input voltage and frequency. As was the case in
Figure 23, here also a cut-off point is present for the circuit to commence
operation. The reason for this discrepancy is as discussed above. The reason
for the improper slope lies entirely in the practical limitations of the design
because the theoretical analysis was done correctly and was tested through
simulations. It is needed to test several resistor values for the integrator
input to determine the one that insures the required slope.

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CONCLUSION AND RECOMMENDATIONS

It is worth noting that the major design stumbling blocks were

successfully overcome in this design and triangular and square
waveforms are being successfully generated. It remains to make
adjustments and improvements to the circuit in order to meet the
precise specifications. These adjustments and improvements can be
summarized as follows

• Implement the same design with LM318 Op-Amps at the

voltage control stage and at the bistable stage.

• Adjust the slope of the second range of operation of the circuit

by selecting resistor values based on experimental
measurement of the frequency.

• Eliminate the non symmetrical duty cycle by means of a limiter circuit

before closing the bistable feedback such that the dependence of the
bistable output on the power supply is eliminated. This way Vth will
not change once a power supply is changed. (as long as the supply
voltage is higher than limiter cutoff voltage).This will provide precise
high and low threshold points to incorporate in the analysis and
design.

• With the above point, it will also be possible to eliminate the two
separate amplitude control circuits and combine the amplitude control
into one separate block thus adding maintainability to the circuit.

• Implement DC offset compensations. Every Op-Amp has finite value of

offset current entering the positive and negative terminals and a small
input offset voltage between the positive and negative terminals.
Eliminating this offset will allow the circuit to provide more predictable
and precise results.

• Implement the voltage control circuit with resistor values ~50k. In

order to eliminate the cut-off point of the input voltage, the resistor
values of the voltage control circuit must be made significantly lower
than the specified input resistance of the utilized Op-Amp.

Page 33 of 35
REFERENCES
1. M. Kassam ELE 504 Major Design Project, Department of Electrical and
Computer Engineering, Ryerson University, 2011.
2. A. Sedra, K. Smith Microelectronic Circuits, Oxford University Press;
Sixth Edition (Dec 15 2009).

Page 34 of 35
APPENDIX

Components Used
ALD1106 PBL 0863
LM741CN EA26 2
LM741CN K6D009
LM318N HARRIS 8318
PH4148 DIODE
1N4734A ZENER
H8F4734A ZENER
1mF 85 C Polarized Coupling Capacitor
o

RESISTORS
H0 E0T 10k Potentiometer 2
1M 3
100k 2
10k 2
15k 1
2.2k 2
6.8k 2
8.1k 1

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